Nonvolatile semiconductor memory devices, systems on chip, and related methods

Abstract

The invention provides a nonvolatile semiconductor memory device, a system on chip and a related method. The nonvolatile semiconductor memory device comprises a plurality of column lines and row lines; the row decoder is used for generating a row gating signal according to the row address signal so as to start a row line; the column decoder is used for generating a column gating signal according to the column address signal so as to start a column line; and a memory array comprising: a plurality of non-volatile memory cells, each non-volatile memory cell being constructed at an intersection of a row line and a column line; each nonvolatile memory unit is coupled to one of a plurality of row lines through a row enable switch and is coupled to one of a plurality of column lines through at least one column enable switch, and the row enable switch enables the started row line to enable the nonvolatile memory unit according to a column strobe signal. The column enable switch enables the started column line to enable the nonvolatile memory unit according to the row strobe signal, so that the enabled nonvolatile memory unit operates in one of a programming mode, an erasing mode and a reading mode.

Description

Technical Field

[0001] The present invention relates to a non-volatile semiconductor memory device, a system on chip (SoC) using the memory device and related methods, and in particular to a non-volatile semiconductor memory device having a memory array composed of novel non-volatile memory cells, a system on chip using the memory device and related methods. Background Art

[0002] According to the prior art, memory types are divided into random access memory (RAM) and non-volatile memory (NVM). RAM memory contents will disappear after power failure, while NVM memory contents will not disappear after power failure.

[0003] RAM is divided into static random access memory (SRAM) and dynamic random access memory (DRAM). SRAM is fast, does not require refresh action, has a large area and high cost, and is suitable for CPU internal cache. DRAM requires refresh action, has a small area, low cost, and large capacity, and is suitable for CPU external memory. NVM is divided into read-only memory (ROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) and flash memory.

[0004] The characteristic of ROM is that it cannot be programmed, and the memory content is determined when the IC is manufactured; the characteristic of PROM is that it can be programmed once, and the memory content cannot be modified; the characteristic of EPROM is that it is often used to store system program code, the data is erased by ultraviolet light, the erasable number of times is 10,000 to 100,000, the minimum amount of data to be cleared is the entire memory, data programming uses hot electron injection, the minimum amount of data to be written is the entire memory, and the minimum amount of data to be read is one byte.

[0005] The characteristic of EEPROM is that it is often used to store small amounts of parameter data. Data erasure uses FN tunneling, the erasable number of times is 1,000,000, and the minimum amount of data to be cleared is one byte. Data programming uses FN tunneling, and the minimum amount of data to be read and written is one byte. In addition, flash memory is a type of EEPROM. Data erasure uses FN tunneling, and the minimum amount of data to be cleared is one block. NOR Flash can be erased 10,000 to 100,000 times, and NAND Flash can be erased 100,000 to 1,000,000 times. Data programming uses hot electron injection, and the minimum amount of data to be read in NOR Flash is one byte, and the minimum amount of data to be written is one page. The minimum amount of data to be read and written in NAND Flash is one page.

[0006] Please refer to Figure 1 , showing a circuit structure diagram of a conventional non-volatile memory (NVM) device. The non-volatile memory (NVM) device includes a row decoder 10, a column decoder 20, and a memory array 30 composed of a plurality of non-volatile memory cells 31 (NVM cells). Figure 2 A schematic diagram showing a non-volatile memory cell 31 in the memory array electrically connected to the intersection of a row line and a column line.

[0007] The memory array 30 may include one or more memory banks. In each memory bank, a plurality of non-volatile memory cells 31 are closely arranged in rows and columns at the intersection of a plurality of row lines 11 and a plurality of column lines 21. From the perspective of IC layout, the memory array 30 is a flat and compact square block. Figure 4 , showing Figure 1 A circuit layout diagram of a conventional non-volatile memory (NVM) device is shown. Figure 4 In the example, the square block is only composed of memory cells 31 without any other circuit elements. Around the square block, a row decoder 10 is usually arranged above (or below) the square block to electrically connect multiple row lines of the square block, and a column decoder 20 is arranged on the left (or right) of the square block to electrically connect multiple column lines of the square block. The row decoder 10 and the column decoder 20 are usually composed of switches and multiplexers.

[0008] Continue to refer Figure 1The row decoder 10 generates a row strobe signal according to a row address signal to activate one of the row lines 11 among the plurality of row lines. The column decoder 20 generates a column strobe signal according to a column address signal to activate one of the column lines 21 among the plurality of column lines. When the row decoder 10 and the column decoder 20 respectively activate a row line 11 and a column line 21 according to the row address signal and the column address signal, the non-volatile memory (NVM) device can address a non-volatile memory cell 31, and drive the row line 11 activated by the row decoder 10 and the column line 21 activated by the column decoder 20 through a voltage source or a current source 1 electrically connected to the row decoder 10 and electrically connected to the column decoder 20, respectively, so as to enable the addressed non-volatile memory cell 31 to operate in one of a programming mode, an erasing mode and a reading mode.

[0009] Taking the voltage source 1 as an example, when the addressed non-volatile memory cell 31 is enabled to operate in different modes, the voltage sources 1 of the row decoder 10 and the column decoder 20 will respectively provide the operating voltages required for different modes to the activated row line 11 and the activated column line 21, so that the addressed non-volatile memory cell 31 can operate in one of the programming mode, the erasing mode and the reading mode.

[0010] A non-volatile memory cell is usually represented by a capacitor combined with a metal oxide semiconductor field effect transistor (MOSFET). Figure 3A and Figure 3B , respectively showing the symbolic representation of two types of non-volatile memory cells 31. Figure 3A and Figure 3B The non-volatile memory cell 31 shown has a drain (D) electrically connected to a row line, and a gate (G) and a source (S) electrically connected to two column lines. With the activated row line and the activated column line providing different operating voltages, the addressed non-volatile memory cell 31 can operate in one of the programming mode, the erasing mode and the reading mode.

[0011] Next reference Figure 5, showing a circuit architecture diagram of a local memory array 30 addressing a non-volatile memory cell 31. According to the circuit architecture of the prior art, taking voltage source driven addressing as an example, when a row address signal addresses a row of non-volatile memory cells 31 in the memory array 30, the row decoder generates a row selection signal according to the row address signal to activate one of the plurality of row lines 11. The voltage source provides an operating voltage VDa to the activated row line 11, so that the drains of the non-volatile memory cells 31 addressing the row array all receive the operating voltage VDa, and the voltage source provides a voltage VDb to the remaining unactivated row lines, so that the drains of the non-volatile memory cells 31 in the remaining unaddressed row arrays all receive the voltage VDb.

[0012] When a column address signal addresses a non-volatile memory cell 31 of one column array of the memory array 30, the column decoder generates a column selection signal according to the column address signal to activate two column lines 21 among the plurality of column lines 21. The voltage source provides operating voltages VGa and VSa to the two activated column lines 21, and provides voltages VGb and VSb to the remaining unactivated column lines. In this way, the gate and source of the non-volatile memory cell 31 of the addressed column array receive the operating voltages VGa and VSa, respectively, while the gate and source of the non-volatile memory cells of the remaining unaddressed column arrays receive the voltages VGb and VSb provided by the remaining unactivated column lines.

[0013] therefore, Figure 4 The local memory array 30 shown includes a plurality of nonvolatile memory cells 31 having four states (state1, state2, state3, state4). The nonvolatile memory cell 31 addressed by the activated row line 11 and the activated column line 21 has state 1 (state1), and the nonvolatile memory cell in state 1 receives operating voltages VDa, VGa, and VSa, wherein the voltage source provides the required operating voltages VDa, VGa, and VSa according to the operating mode of the operating nonvolatile memory cell. The nonvolatile memory cell 31 addressed by the activated row line 11 and the inactivated column line 21 has state 2 (state2), and the nonvolatile memory cell 31 in state 2 receives operating voltage VDa and voltages VGb and VSb. The nonvolatile memory cell 31 addressed by the activated column line 21 and the inactivated row line 11 has state 3 (state3), and the nonvolatile memory cell 31 in state 3 receives operating voltages VGa, VSa, and voltage VDb. The nonvolatile memory cells 31 addressed by the remaining inactivated row lines 11 and the inactivated column lines 21 have state 4 , and the nonvolatile memory cells 31 in state 4 receive voltages VGb, VSb, and VDb.

[0014] Since the existing memory array 30 adopts Figure 1 In the circuit structure shown, the conventional non-volatile memory (NVM) device selects the non-volatile memory cell 31 to be operated through the row line 11 activated by the row decoder 10 and the column line 21 activated by the column decoder 20. According to the prior art, the voltage or current controlled to read, write or clear the operating non-volatile memory cell 31 is introduced from the voltage source or current source 1 to the entire activated row line 11 through the row decoder 10, so that the non-operating non-volatile memory cells 31 (state 2) of the entire row array will be affected. The voltage source or current source is introduced to the entire activated column line 21 through the column decoder 20, so that the non-operating non-volatile memory cells 31 (state 3) of the entire column array will be affected. Therefore, the addressing method of the conventional non-volatile memory (NVM) device will generate read interference or write interference to the adjacent non-operating non-volatile memory cells 31 (states 2 and 3), which may destroy the content data of the adjacent non-operating non-volatile memory cells 31, thereby reducing the reliability of the operation of the memory array 30.

[0015] The following examples illustrate possible interference. Fig. 6A , showing that a working non-volatile memory cell 31 is programmed by hot electron injection in a memory array 30 of a conventional circuit architecture. When the working non-volatile memory cell 31 operates in a programming mode, the drain of the working non-volatile memory cell 31 receives a programming operating voltage VPb, and the gate and source thereof receive a programming operating voltage VPa and 0V, respectively. At this time, the unactivated row line and column line provide 0V. Among them, the programming operating voltage VPb may cause erase interference to the adjacent non-volatile memory cell 31 in state 2, and the programming operating voltage VPa may cause program interference to the adjacent non-volatile memory cell 31 in state 3.

[0016] Please refer to Figure 6B, showing an active non-volatile memory cell 31 being erased by FN tunneling in a memory array 30 of a conventional circuit architecture. When the active non-volatile memory cell 31 operates in an erasing mode, the drain of the active non-volatile memory cell 31 receives an erasing operating voltage VEb, and the gate and source thereof receive 0V and an erasing operating voltage VEa, respectively. At this time, the unactivated row line is in a floating state, and the unactivated column line provides an erasing operating voltage VEc. The erasing operating voltage VEb may cause an erase disturbance to the adjacent non-volatile memory cell 31 in state 2, while the erase operating voltage VEc may cause a program disturbance to the adjacent non-volatile memory cells 31 in states 2 and 4, and the floating potential of the unactivated row line and the erase operating voltage VEa may cause an erase disturbance to the adjacent non-volatile memory cell 31 in state 3.

[0017] Please refer to Figure 6C , showing a working non-volatile memory cell 31 being read in a memory array 30 of a conventional circuit architecture. When the working non-volatile memory cell 31 operates in a reading mode, the drain of the working non-volatile memory cell 31 receives a reading operating voltage VRb, and the gate and source thereof receive a reading operating voltage VRa and 0V, respectively. At this time, the unactivated row line and column line provide 0V. Among them, the reading operating voltages VRb and VRa may generate programming interference to the working non-volatile memory cell 31, the reading operating voltage VRb may generate erase interference to the adjacent non-volatile memory cell 31 in state 2, and the reading operating voltage VRa may generate programming interference to the adjacent non-volatile memory cell 31 in state 3.

[0018] As described above, according to the circuit architecture of the prior art, when a working non-volatile memory cell operates in a certain mode, it may cause erase disturbance or program disturbance to the adjacent non-volatile memory cell 31 for a long time, which will reduce the reliability of the operation of the memory array 30.

[0019] Please refer to Figure 7 ,show Figure 5The schematic diagram of the local memory array 30 addressing the cell group 32 is shown, wherein the plurality of non-volatile memory cells 31 of each cell group 32 are closely arranged in a row / column manner at the intersection of a plurality of row lines and a plurality of column lines, and the plurality of non-volatile memory cells 31 of the cell group 32 are addressed by an activated row line and an activated column line. According to the prior art, taking the voltage source driven addressing as an example, when a row address signal and a column address signal address one of the cell groups Group1 of the memory array 30, the row decoder activates a row line to provide an operating voltage VDa, and the unactivated row line provides a voltage VDb; and the column decoder activates two column lines to provide operating voltages VGa and VSa, and the unactivated column lines provide voltages VGb and VSb. Thus, each nonvolatile memory cell of cell group Group1 has state 1 (state1), each nonvolatile memory cell of cell group Group2 has state 2 (state2), each nonvolatile memory cell of cell group Group3 has state 3 (state3), and each nonvolatile memory cell of cell group Group4 has state 4 (state4).

[0020] use Figure 7 In the circuit architecture shown, the conventional non-volatile memory (NVM) device selects the memory cell group Group1 to be operated through the row line activated by the row decoder and the column line activated by the column decoder. According to the prior art, the voltage or current controlled to read, write or clear the operating memory cell group Group1 is introduced from the voltage source or current source to the entire activated row line through the row decoder, so that the memory cell group Group2 will be affected. The voltage source or current source is introduced to the entire activated column line through the column decoder, so that the memory cell group Group3 will be affected. Therefore, the addressing method of the conventional non-volatile memory (NVM) device will generate programming interference or erasing interference to the adjacent non-volatile memory cell groups (Group2, 3), which may destroy the content data of the adjacent non-volatile memory cells and reduce the reliability of the operation of the memory array 30. Summary of the invention

[0021] In view of the fact that the circuit architecture adopted by the existing non-volatile memory (NVM) device may destroy the content data of the adjacent non-volatile memory cells, which will reduce the reliability of the operation of the memory array 30, one of the purposes of the present invention is to provide a novel non-volatile memory cell and a circuit architecture of a memory array composed of these novel non-volatile memory cells, so that the non-volatile memory cells or cell groups that are not addressed and not working in the memory array are not disturbed by the non-volatile memory cells or cell groups that are addressed and working, thereby obtaining the reliability of stable operation of the memory array.

[0022] One of the purposes of the present invention is to provide a novel non-volatile memory device and a system on chip including the novel non-volatile memory device, so that the non-volatile memory cells or cell groups that are not addressed and not working in the memory array of the non-volatile memory device are not disturbed by the non-volatile memory cells or cell groups that are addressed and working, thereby obtaining the reliability of stable operation of the non-volatile memory device.

[0023] One of the purposes of the present invention is to provide a novel addressing method and a memory control method using the novel addressing method, so that in a non-volatile memory (NVM) device using the novel non-volatile memory cells, non-volatile memory cells or cell groups that are not addressed and not working are not disturbed by non-volatile memory cells or cell groups that are addressed and working, thereby obtaining the reliability of stable operation of the memory array.

[0024] One of the purposes of the present invention is to provide a method for operating a novel addressing method and a method for operating a non-volatile memory device using the novel addressing method, so that the non-volatile memory device uses the novel addressing method to operate the non-volatile memory cells or cell groups that are addressed and in operation in one of the programming mode, erasing mode and reading mode, and does not interfere with the non-volatile memory cells or cell groups that are not addressed and not in operation, thereby obtaining the reliability of stable operation of the non-volatile memory device.

[0025] One of the purposes of the present invention is to provide a memory array layout method, which uses row segment lines and column segment lines to plan each memory block contained in a memory array, so that the unaddressed and non-operating memory blocks in the memory array are not disturbed by the addressed and operating memory blocks, thereby obtaining the reliability of stable operation of the memory array.

[0026] In order to achieve one of the above-mentioned objects, the present invention provides a non-volatile semiconductor memory device, comprising: a plurality of row lines; a plurality of column lines; a row decoder, generating a row selection signal according to a row address signal to activate a row line; a column decoder, generating a column selection signal according to a column address signal to activate a column line; and a memory array, comprising: a plurality of non-volatile memory cells (NVM cells), each of which is constructed at the intersection of the row lines and the column lines; each non-volatile memory cell is coupled to one of the plurality of row lines via a row-enabling switch, and is activated via at least one row-enabling switch. A switch is coupled to one of the plurality of column lines, the row enable switch enables the activated row line to enable the nonvolatile memory cell according to the column enable signal, and the column enable switch enables the activated column line to enable the nonvolatile memory cell according to the row enable signal, so that the enabled nonvolatile memory cell operates in one of a programming mode, an erasing mode and a reading mode.

[0027] In order to achieve one of the above-mentioned objects, the present invention provides a system on chip (System on Chip) comprising: the above-mentioned non-volatile semiconductor memory device; and a power circuit electrically connected to the column decoder and the row decoder to provide the voltage required for the enabled non-volatile memory unit to operate in each mode.

[0028] In order to achieve one of the above-mentioned objects, the present invention provides an addressing method for addressing at least one non-volatile memory cell of a plurality of non-volatile memory cells (NVM cells), and each non-volatile memory cell corresponds to at least one row line and at least one column line. The addressing method comprises: generating a row selection signal according to a row address signal to activate a row line; generating a column selection signal according to a column address signal to activate a column line; enabling the row line to enable the at least one non-volatile memory cell according to the column selection signal; and enabling the column line to enable the at least one non-volatile memory cell according to the row selection signal, so that the at least one non-volatile memory cell operates in one of a programming mode, an erasing mode and a reading mode.

[0029] In order to achieve one of the above-mentioned objects of the invention, the present invention provides a method for operating a non-volatile semiconductor memory device, wherein the non-volatile semiconductor memory device includes a plurality of non-volatile memory cells. The method includes: addressing at least one non-volatile memory cell using the above-mentioned addressing method; and operating the at least one non-volatile memory cell to program digital data, or to erase the stored digital data, or to read the stored digital data.

[0030] In order to achieve one of the above-mentioned objects, the present invention provides a non-volatile semiconductor memory device, comprising: a row decoder, generating a row selection signal according to a row address signal to activate one of a plurality of row lines; a column decoder, generating a column selection signal according to a column address signal to activate one of a plurality of column lines; and a memory array, comprising: a plurality of non-volatile memory cells (NVM cells), and the plurality of non-volatile memory cells are divided into a plurality of memory blocks; each non-volatile memory cell in each memory block is electrically connected to a column-segment line and a row-segment line respectively; wherein each memory block comprises a column-enabling switch array and a row-enabling switch array. The invention relates to a memory block of the present invention. The memory block of the present invention is ...

[0031] In order to achieve one of the above-mentioned objects, the present invention provides a layout method of a memory array, comprising: configuring a plurality of row lines and a plurality of column lines at a metal layer; configuring a plurality of non-volatile memory cells (NVM cells) in a memory block at a device layer, and each non-volatile memory cell (NVM cell) corresponds to a row line and a column line respectively; configuring a plurality of row segment lines and a plurality of column segment lines at a metal layer corresponding to the memory block, and each non-volatile memory cell (NVM cell) of the memory block corresponds to a row segment line and a column segment line respectively; configuring at least one column-enabling switch array and / or at least one row-enabling switch array between adjacent memory blocks at a device layer, wherein the row-enabling switch array controls a portion of row lines to be electrically connected to the row segment lines of a memory block, and the column-enabling switch array controls a portion of column lines to be electrically connected to the column segment lines of a memory block.

[0032] In order to achieve one of the above-mentioned objects of the invention, the present invention provides a memory control method for controlling the layout of a memory array using the above-mentioned layout method, comprising: according to the column selection signal, controlling the row enable switch array to electrically connect part of the row lines to the row segment lines of the memory block; and according to the row selection signal, controlling the column enable switch array to electrically connect part of the column lines to the column segment lines of the memory block.

[0033] According to the novel nonvolatile memory cell, the implemented nonvolatile memory device, the system on chip and the novel addressing method, the layout method of the memory array and the memory control method of the present invention, the nonvolatile memory cells or cell groups that are not addressed and not working in the memory array composed of the novel nonvolatile memory cells are not disturbed by the nonvolatile memory cells or cell groups that are addressed and working, thereby obtaining the reliability of stable operation of the memory array. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 FIG. 1 is a circuit diagram of a conventional non-volatile memory (NVM) device.

[0035] Figure 2 A schematic diagram of a nonvolatile memory cell electrically connecting a row line and a column line.

[0036] Figure 3A A circuit diagram of a symbolic representation of a nonvolatile memory cell.

[0037] Figure 3B A circuit diagram showing another symbolic representation of a nonvolatile memory cell.

[0038] Figure 4 for Figure 1 A circuit layout diagram of a conventional non-volatile memory device is shown.

[0039] Figure 5 A circuit diagram for addressing a nonvolatile memory cell in a local memory array.

[0040] Fig. 6A Schematic diagram of the state of a local memory array operating with hot electron injection programming.

[0041] Figure 6B FIG. 1 is a schematic diagram of the state of a local memory array operating with FN tunneling erasure.

[0042] Figure 6C A state diagram of the read operation of the local memory array.

[0043] Figure 7 Schematic diagram of addressing cell groups in a local memory array.

[0044] Fig. 8A is a schematic diagram of a non-volatile memory unit of the present invention.

[0045] Figure 8B is a circuit diagram of a non-volatile memory unit of the present invention.

[0046] Fig. 9 A circuit architecture diagram of an addressing mode of the memory array of the present invention.

[0047] Fig. 10A FIG. 4 is a schematic diagram of the non-volatile memory unit / group of the present invention in a working state.

[0048] Fig. 10B FIG. 4 is a schematic diagram of a non-volatile memory cell / group of the present invention in a non-working state.

[0049] Fig.11 FIG. 4 is a circuit architecture diagram of another addressing mode of the memory array of the present invention.

[0050] Fig.12 FIG. 4 is a circuit layout diagram of the nonvolatile memory device of the present invention.

[0051] Description of reference numerals:

[0052] 1 Voltage source, current source

[0053] 10-line decoder

[0054] 11 lines

[0055] 20 column decoder

[0056] 21 lines

[0057] 30 memory array

[0058] 31 Non-volatile memory cells, FGMOS

[0059] 32 unit group

[0060] 40 memory array

[0061] 41 non-volatile memory cells

[0062] 411 row energy switch

[0063] 412 Column enable switch

[0064] 42 non-volatile memory cell groups

[0065] 421 rows of energy switch array

[0066] 422 column enable switch array

[0067] 50 memory blocks

[0068] 51 line segment lines

[0069] 52 column segment lines DETAILED DESCRIPTION

[0070] All technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art of the present invention. The technical terms explained below are used in the specification of the present invention only for the purpose of describing basic definitions and are not intended to limit the scope of the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0071] Coupled to: A physical connection through at least one device, or a physical connection without passing through any device. For example, device A is physically connected to device B through device C, or device A is physically connected to device B. Both are considered device A coupled to device B.

[0072] Electrically connected to: An electrical connection that can transmit electrical energy, or an electrical connection that transmits electrical energy through at least one device. For example, a power supply electrically connected to device A via a conductor, or a power supply electrically connected to device A via a conductor through an electronic switch, are both considered to be the power supply electrically connected to device A.

[0073] Enable a device: Enable a device to operate in a certain function. For example, a row line is activated by a row select signal and a column line is activated by a column select signal, so that the non-volatile memory cell electrically connected to the row line and the column line can operate in programming mode, erasing mode and reading mode, which is regarded as the row select signal or the column select signal enabling the non-volatile memory cell, or the activated row line or the activated column line enabling the non-volatile memory cell.

[0074] The invention will be described more fully below with reference to the drawings, and specific exemplary embodiments are shown by way of illustration. However, the invention may be embodied in many different forms, and thus the construction covered or claimed is not limited to any exemplary embodiment disclosed in this specification, which is merely illustrative. In addition, the invention may be embodied as a method, circuit or device or system, computer program product. Thus, the embodiments may take the form of, for example, hardware, software, firmware, or any combination of these.

[0075] First reference Fig. 8A and Figure 8B , respectively showing a schematic diagram and a circuit diagram of a novel non-volatile memory cell of the present invention. The novel non-volatile memory cell 41 of the present invention is composed of a non-volatile memory cell 31, at least one row enable switch 411 and at least one column enable switch 412, and is suitable for being constructed at the intersection of a row line and a column line of a memory array. The row line is physically connected to the non-volatile memory cell 31 through the row enable switch 411, and the column line is physically connected to the non-volatile memory cell 31 through the column enable switch 412, so that the activation of the row line and the column line can enable the non-volatile memory cell 31 to operate in one of a programming mode, an erasing mode and a reading mode.

[0076] Continue to refer Figure 8B In one embodiment of the present invention, a novel non-volatile memory cell 41 is suitable for being arranged at the intersection of a row line and two column lines in a memory array, and comprises: a row enable switch 411, two column enable switches 412, and a floating gate MOSFET or FGMOS 31, wherein the drain of the FGMOS 31 is coupled to the row line via the row enable switch 411, and the gate and source of the FGMOS 31 are respectively coupled to the two column lines via the two column enable switches 412. When the row line and the two column lines are activated, the row enable switch 411 and the two column enable switches 412 will be turned on at the same time, such as Fig. 10AAs shown, the row line and the two column lines are electrically connected to the FGMOS 31, and the FGMOS 31 is provided with the required electrical energy, so as to enable the FGMOS 31 to enter the working state and operate in one of the programming mode, erasing mode and reading mode.

[0077] After the FGMOS 31 completes a certain operation mode, the potential of the activated row line and the activated two column lines first drops to 0V, and then the row enable switch 411 and the two column enable switches 412 are turned OFF. Fig. 10B As shown, the gate, source and drain of the FGMOS 31 are kept at 0V and enter the non-operating state. Therefore, in the non-operating state of the novel non-volatile memory cell of the present invention, the potentials of the gate, source and drain of the FGMOS 31 are not affected by whether the row line and the two column lines are activated, thereby obtaining the reliability of the stable operation of the memory array.

[0078] Please refer to Fig. 9 , a circuit architecture diagram showing an addressing mode of a memory array of the present invention. In another embodiment of the present invention, a memory array 40 includes: a plurality of row lines 11 arranged in parallel with each other; a plurality of column lines 21 arranged in parallel with each other; and a plurality of novel non-volatile memory cells 41, each novel non-volatile memory cell 41 being arranged at the intersection of one of the row lines 11 and at least one of the column lines 21, each novel non-volatile memory cell 41 including: a row enable switch 411, at least one column enable switch 412, and a non-volatile memory cell, the non-volatile memory cell being coupled to the one of the row lines 11 via the row enable switch 411, and coupled to the at least one of the column lines 21 via the column enable switch 412.

[0079] The nonvolatile memory cell is implemented by taking FGMOS as an example. The FGMOS is disposed at the intersection of a row line 11 and two column lines 21 in the memory array 40. The drain of the FGMOS is coupled to the row line 11 via the row enable switch 411, and the gate and source of the FGMOS are respectively coupled to the two column lines 21 via two column enable switches 412. By controlling the row enable switch 411 and the two column enable switches 412 to be turned on or off, it is determined that the activated row line 11 and the activated column line 21 are electrically connected to the FGMOS, so that the FGMOS enters a working state and operates in one of a programming mode, an erasing mode, and a reading mode.

[0080] When the row line 11 and the at least one column line 21 are activated to address the non-volatile memory cell, the row enable switch 411 and the at least one column enable switch 412 will be turned on at the same time, so that the activated row line 11 and the activated column line 21 are electrically connected to the addressed non-volatile memory cell and provide the electrical energy required by the non-volatile memory cell, so as to enable the non-volatile memory cell to enter a working state and operate in one of a programming mode, an erasing mode and a reading mode.

[0081] After the non-volatile memory cell has completed operating a certain mode, the potential of the activated row line 11 and the activated column line 21 is first reduced to 0V, and then the row enable switch 411 and the column enable switch 412 are turned on (OFF), so that the non-volatile memory cell is electrically isolated and enters a non-operating state. Therefore, when the non-volatile memory cell of the memory array 40 of the present invention is not addressed and in a non-operating state, because the row enable switch 411 and the column enable switch 412 are turned on (OFF), the corresponding row line 11 and the corresponding column line 21 are not electrically connected, and the non-addressed non-volatile memory cell is electrically isolated and enters an idle state. The idle non-volatile memory cell does not receive any voltage and is not disturbed by the operating mode of the operating cell, thereby obtaining the reliability of the stable operation of the memory array 40.

[0082] Continue to refer Fig. 9 In another embodiment of the present invention, a memory array 40 includes: a plurality of row lines 11 arranged in parallel; a plurality of column lines 21 arranged in parallel; and a plurality of novel non-volatile memory cells 41, wherein the plurality of novel non-volatile memory cells 41 are arranged into a plurality of non-volatile memory cell groups 42, each of the novel non-volatile memory cell groups 42 being arranged at the intersection of one of the row lines 11 and at least one of the column lines 21. The non-volatile memory cell group 42 is coupled to the one of the row lines 11 via at least one row enable switch 411, and is coupled to the at least one of the column lines 21 via the column enable switch 412. When the row line 11 and the at least one column line 21 are activated to address the non-volatile memory cell group 42, the row enable switch 411 and the at least one column enable switch 412 will be turned on at the same time, so that the activated row line 11 and the activated column line 21 are electrically connected to the addressed non-volatile memory cell group 42, and the multiple non-volatile memory cells 41 of the addressed non-volatile memory cell group 42 all enter the working state and operate in one of the programming mode, erasing mode and reading mode.

[0083] When the non-volatile memory cell group 42 is planned to form a non-volatile memory cell 41 of a byte or a word, the non-volatile memory cell group 42 that enters the working state can operate in a programming mode, an erasing mode or a reading mode of a byte or a word. The non-volatile memory cell that forms a byte or a word is implemented by FGMOS as an example. The drain of each FGMOS is connected to each other and coupled to a row line 11 through a row enable switch 411, the gate of each FGMOS is connected to each other and coupled to a column line 21 through a column enable switch 412, and the source of each FGMOS is connected to each other and coupled to another column line 21 through a column enable switch 412. In this way, each FGMOS of a byte or a word can operate in a programming mode, an erasing mode or a reading mode at the same time.

[0084] Continue to refer Fig. 9 , taking FGMOS to implement nonvolatile memory cells as an example, and taking voltage source driven addressing as an example, when a row address signal and a column address signal address one of the FGMOS in the memory array 40, a row decoder generates a row strobe signal according to the row address signal to activate a row line 11, and a column decoder generates a column strobe signal according to the column address signal to activate a column line 21. The row enable switch 411 is controlled to be turned on (ON) by the column strobe signal, and the column enable switch 412 is controlled to be turned on (ON) by the row strobe signal, so that the activated row line 11 provides the working voltage VDa to the drain of the addressed FGMOS, and the activated column line 21 provides the working voltage VGa, VSa to the gate and source of the addressed FGMOS. At this time, the unactivated row line 11 provides the voltage VDb, and the unactivated column line 21 provides the voltage VGb, VSb. Therefore, the addressed FGMOS can operate in the programming mode, the erasing mode or the reading mode. The unaddressed FGMOS is electrically isolated and enters an idle state because the row enable switch 411 and the column enable switch 412 are not turned on by the row select signal and the column select signal, and is not affected by the operating mode of other working non-volatile memory cells 41 or non-volatile memory cell groups 42.

[0085] In other words, the non-volatile memory cells 41 or the non-volatile memory cell groups 42 that are not addressed in the memory array 40 do not enter the working state. At this time, the inactivated row line 11 provides the voltage VDb, and the inactivated column line 21 provides VGb, VSb, but the remaining row enable switches 411 and the column enable switches 412 are not turned on, so that the non-volatile memory cells 41 or the non-volatile memory cell groups 42 that do not enter the working state are prevented from being disturbed by the voltages provided on the activated or inactivated row lines 11 and column lines 21.

[0086] In one embodiment of the present invention, a non-volatile memory (NVM) device includes: a memory array 40, the memory array 40 includes: a plurality of row lines 21 (row lines), a plurality of column lines 11 (column lines) and a plurality of non-volatile memory cells (NVM cells), each non-volatile memory cell is constructed at the intersection of the row lines 11 and the column lines 21. The non-volatile memory (NVM) device further includes: a row decoder and a column decoder, the row decoder generates a row selection signal according to a row address signal to activate a row line. The column decoder generates a column selection signal according to a column address signal to activate a column line. The activated row line and the activated column line provide the operating voltage required for the addressed non-volatile memory cell to operate in each mode.

[0087] In the memory array 40 of the present invention, each nonvolatile memory cell is coupled to the corresponding row line 11 via a row-enabling switch 411 (column-enabling switch), and is coupled to the corresponding column line 21 via at least one row-enabling switch 412 (row-enabling switch). Fig. 9 As shown, the non-volatile memory cell is described by taking FGMOS as an example, the drain of the FGMOS is coupled to the corresponding row line 11 via a row enable switch 411, and the gate and source of the FGMOS are respectively coupled to the corresponding column line 21 via two column enable switches 412. Moreover, the row enable switch 411 is controlled to be turned on (ON) by the column selection signal, so that the activated row line 11 is electrically connected to the drain of the FGMOS, so that the activated row line 11 is only electrically connected to the working non-volatile memory cell. The column selection signal does not control the other row enable switches 411 to be turned on (ON), so that the activated row line 11 and other non-activated row lines 11 are not electrically connected to other non-operating non-volatile memory cells. The two column enable switches 412 are controlled to be turned on (ON) by the row selection signal, so that the activated two column lines 21 are respectively electrically connected to the gate and source of the FGMOS, so that the activated two column lines 21 are only electrically connected to the working non-volatile memory cell. The row selection signal does not control the other column enable switches 412 to be turned on, so that the two activated column lines 21 and the other inactivated column lines 21 are not electrically connected to other inactive non-volatile memory cells. Therefore, when a row address signal and a column address signal address one non-volatile memory cell 41 or a non-volatile memory cell group 42 of the memory array 40 of the present invention, the activated row line 11 and the activated column line 21 provide the operating voltage required for each mode, so that the active non-volatile memory cell 41 or the non-volatile memory cell group 42 can operate in one of the programming mode, the erasing mode and the reading mode.

[0088] When the working memory cell has completed its operation and the potential of the activated row line 11 and column line 21 drops from the working voltage to 0 V, the row enable switch 411 and the column enable switch 412 are controlled to be turned OFF, so that the drain, gate and source of the memory cell are kept at 0 V. Therefore, the non-working non-volatile memory cell 41 or non-volatile memory cell group 42 of the memory array 40 of the present invention isolates the row line 11 and the column line 21 and enters an idle state.

[0089] According to this embodiment of the present invention, the present invention provides a method for manufacturing a non-volatile memory (NVM) device, comprising: in the layout of the memory array, a row enable switch is arranged between each non-volatile memory cell and one of the row lines; and at least one column enable switch is arranged between each non-volatile memory cell and at least one of the column lines. The non-volatile memory cell is described by taking FGMOS as an example. In the layout of the memory array, the present invention arranges a row enable switch between the drain of each FGMOS and one of the row lines, and arranges two column enable switches between the gate and source of each FGMOS and the corresponding two column lines.

[0090] According to this embodiment of the present invention, a non-volatile memory (NVM) device of the present invention implements an addressing method, the addressing method is used to address at least one non-volatile memory cell of a plurality of non-volatile memory cells in a memory array, and each non-volatile memory cell of the memory array corresponds to at least one row line and at least one column line. The addressing method of the present invention includes: a row decoder generates a row selection signal according to a row address signal to activate a row line; a column decoder generates a column selection signal according to a column address signal to activate a column line; a row enable switch is controlled according to the column selection signal so that the activated row line enables the at least one non-volatile memory cell; and at least one column enable switch is controlled according to the row selection signal so that the activated column line enables the at least one non-volatile memory cell, so that the at least one non-volatile memory cell operates in one of a programming mode, an erase mode and a read mode.

[0091] According to an embodiment of the present invention, a programming method for operating a non-volatile memory (NVM) device of the present invention is to address at least one non-volatile memory cell in a memory array according to the addressing method of the present invention, so that the addressed non-volatile memory cell obtains the working voltage required for operating in a programming mode, and the corresponding row line and column line of the non-addressed non-volatile memory cell are electrically isolated, thereby programming the addressed non-volatile memory cell to write digital data. An erasing method for operating a non-volatile memory (NVM) device of the present invention is to address at least one non-volatile memory cell in a memory array according to the addressing method of the present invention, so that the addressed non-volatile memory cell obtains the working voltage required for operating in an erase mode, and the corresponding row line and column line of the non-addressed non-volatile memory cell are electrically isolated, thereby erasing the digital data stored in the addressed non-volatile memory cell. The reading method of the non-volatile memory (NVM) device of the present invention is to address at least one non-volatile memory cell in a memory array according to the addressing method of the present invention, so that the addressed non-volatile memory cell obtains the working voltage required to operate in the read mode, and the corresponding row line and column line of the non-addressed non-volatile memory cell are electrically isolated, thereby reading the digital data stored in the addressed non-volatile memory cell.

[0092] According to the above-mentioned embodiment of the present invention, a system on chip includes a non-volatile memory (NVM) device of the present invention; and a power circuit, which is electrically connected to the row decoder and the column decoder of the non-volatile memory (NVM) device of the present invention to provide the voltage required for the enabled non-volatile memory unit or group to operate in each mode.

[0093] According to this embodiment of the present invention, the non-volatile memory (NVM) device of the present invention implements a memory control method, which is applicable to a memory controller, including: controlling at least one column enable switch to be turned on according to a row select signal generated by a row address signal, so that the addressed non-volatile memory cell is electrically connected to the activated column line; and controlling a row enable switch to be turned on according to a column select signal generated by a column address signal, so that the addressed non-volatile memory cell is electrically connected to the activated row line, so that the row line activated by the row select signal and the column line activated by the column select signal can enable at least one non-volatile memory cell to operate in one of a programming mode, an erase mode and a read mode.

[0094] Please refer to Fig.11, is another circuit structure diagram showing another addressing of the memory array 40 of the present invention. In this embodiment of the present invention, the non-volatile memory cell is taken as FGMOS, and considering that each FGMOS is configured with one row of enable switches 411 and two columns of enable switches 412, the layout area of ​​the memory array will increase due to the number of enable switches 411 and 412. Therefore, reducing the number of enable switches can reduce the layout area of ​​the memory array, or increase the number of non-volatile memory cells to obtain better economic cost.

[0095] In this embodiment of the present invention, the memory array 40 of the present invention includes: a plurality of row lines 11 arranged in parallel with each other; a plurality of column lines 21 arranged in parallel with each other; and a plurality of non-volatile memory cells, and the plurality of non-volatile memory cells are divided into a plurality of non-volatile memory cell groups 42. Each non-volatile memory cell group 42 includes a memory block 50, a column-enabling switch array 421, and a row-enabling switch array 422. Each memory block 50 includes: a plurality of column-segment lines 51, a plurality of row-segment lines 52, and a plurality of non-volatile memory cells, wherein the plurality of non-volatile memory cells of the memory block 50 are closely arranged in a row / column manner at the intersection of the plurality of row-segment lines 51 and the plurality of column-segment lines 52.

[0096] Each memory block 50 is configured with a row of enable switch arrays 421 and a column of enable switch arrays 422. In the IC layout, it looks like Fig.12As shown, the memory array 40 is a plurality of closely arranged square blocks, one square block corresponds to a memory block 50 of a non-volatile memory cell group 42, the row enable switch array 421 can be arranged above or below the square block, and the column enable switch array 422 can be arranged on the left or right of the square block. The row enable switch array 421 includes a plurality of row enable switches, each row segment line 51 is coupled to the corresponding row line 11 via a row enable switch, and the column enable switch array 422 includes a plurality of column enable switches, each column segment line 52 is coupled to the corresponding column line 21 via a column enable switch. When a row address signal and a column address signal address one of the memory blocks 50 of the memory array 40 to work, the row enable switch array 421 and the column enable switch array 422 of the working memory block 50 are all turned on, so that all the row segment lines 51 and all the column segment lines 52 of the working memory block 50 are electrically connected to the corresponding row line 11 and the corresponding column line 21 respectively, so that the addressed non-volatile memory cells in the working memory block 50 can operate in one of the programming mode, erasing mode and reading mode.

[0097] To further illustrate, and taking FGMOS as a non-volatile memory cell as an example, not all non-volatile memory cells in the working memory block 50 enter the working state, because the activated row line 11 is only electrically connected to one row segment line 51 of the working memory block 50 to provide the working voltage VDa, and the inactivated row line 11 is electrically connected to the other row segment lines 51 of the working memory block 50 to provide the voltage VDb; the activated column line 21 is only electrically connected to two column segment lines 52 of the working memory block 50 to provide the working voltages VGa and VSa, and the inactivated column line 21 is electrically connected to the other column segment lines 52 of the working memory block 50 to provide the voltages VGb and VSb. Therefore, only the non-volatile memory cells addressed by the activated row line 11 and the activated column line 21 in the memory block 50 can operate in one of the programming mode, the erasing mode and the reading mode.

[0098] In the memory array 40 of the present invention, the row enable switch arrays 421 and the column enable switch arrays 422 of the remaining inoperative memory blocks 50 are all turned OFF, so that all the row segment lines 51 and the column segment lines 52 of the remaining inoperative memory blocks 50 are not electrically connected to the corresponding row lines 11 and the corresponding column lines 21. In this way, all the non-volatile memory cells of the remaining inoperative memory blocks 50 enter an idle state. The idle non-volatile memory cells do not receive any voltage and are not affected by the operating mode of the operating memory blocks 50.

[0099] Continue to refer Fig.11 In this embodiment of the present invention, a non-volatile memory (NVM) device includes a row decoder and a column decoder, which are the same as other embodiments of the present invention. Taking voltage source driven addressing as an example, when a row address signal and a column address signal address a non-volatile memory cell in a memory block 50 of a memory array 40, the row decoder generates a row selection signal according to the row address signal to activate a row line to provide an operating voltage VDa, while the unactivated row line provides a voltage VDb, and the column decoder generates a column selection signal according to the column address signal to activate a column line to provide an operating voltage VGa, VSa, while the unactivated column line provides voltages VGb, VSb. At this time, the row selection signal and the column selection signal are used to control the row enable switch array 421 and the column enable switch array 422 connected to the working memory block 50 to be turned on, so that all the row segment lines 51 and all the column segment lines 52 of the working memory block 50 are electrically connected to the corresponding row line 11 and the column line 21, so that the activated row line 11 activates the corresponding row segment line 51, and the activated column line 21 activates the corresponding column segment line 52. Therefore, the activated row segment line 51 and the activated column segment line 52 will enable one of the non-volatile memory cells of the working memory block 50 to operate in one of the programming mode, the erasing mode and the reading mode. The cells of other non-working memory blocks 50 enter an idle state because their row enable switch arrays 421 and the column enable switch arrays 422 are turned off, and are not affected by the operating mode of the working memory block 50.

[0100] According to this embodiment of the present invention, a non-volatile memory (NVM) device of the present invention implements an addressing method for addressing at least one non-volatile memory cell of a plurality of non-volatile memory cells (NVM cells), and the plurality of non-volatile memory cells are divided into a plurality of memory blocks 50, and each non-volatile memory cell in each memory block 50 is electrically connected to a column-segment line 51 and at least one row-segment line 52. The addressing method comprises: a row decoder generates a row selection signal according to a row address signal to activate a row line 11; a column decoder generates a column selection signal according to a column address signal to activate a column line 21; a row enable switch array 421 and a column enable switch array 422 are respectively controlled according to the column selection signal and the row selection signal, so that the activated row line 11 and the activated column line 21 enable one of the memory blocks 50; the row enable switch array 421 enables the memory block 50 according to the column selection signal. The row segment lines 51 of the enabled memory block 50 are electrically connected to the corresponding row lines 11; the column enable switch array 422 enables the column segment lines 52 of the enabled memory block 50 to be electrically connected to the corresponding column lines 21 according to the row selection signal; and, according to the activated row line 11 and the activated column line 21, at least one non-volatile memory cell of the enabled memory block 50 is addressed so that the at least one non-volatile memory cell operates in one of the programming mode, the erasing mode and the reading mode.

[0101] According to this embodiment of the present invention, a non-volatile memory (NVM) device of the present invention implements a layout method of a memory array, comprising: configuring a plurality of row lines and a plurality of column lines on a metal layer of a substrate, wherein the plurality of row lines are configured in parallel with each other, and the plurality of column lines are configured in parallel with each other; and planning a plurality of memory blocks on a device layer of the substrate, wherein each memory block is configured with a plurality of non-volatile memory cells, and each non-volatile memory cell is configured at the intersection of a row line and a column line; wherein, in the metal layer, corresponding to the memory block, a plurality of row segment lines are configured to correspond to the row lines respectively, and a plurality of column segment lines are configured to correspond to the column lines respectively, and each non-volatile memory cell is electrically connected to the corresponding row segment line and the corresponding column segment line; and, in the device layer, at least one row enable switch array and / or at least one column enable switch array are configured between adjacent memory blocks, wherein the row enable switch array controls the plurality of row segment lines of the memory block to be electrically connected to the corresponding row lines respectively, and the column enable switch array controls the plurality of column segment lines of the memory block to be electrically connected to the corresponding column lines respectively.

[0102] According to this embodiment of the present invention, the non-volatile memory (NVM) device of the present invention implements a memory control method, which is applicable to a memory controller, including: controlling a column enable switch array of a memory block to be turned on according to a row selection signal generated by a row address signal, so that multiple column segment lines of the memory block are respectively electrically connected to corresponding column lines; and controlling a row enable switch array of the memory block to be turned on according to a column selection signal generated by a column address signal, so that multiple row segment lines of the memory block are respectively electrically connected to corresponding row lines, so that the row line activated by the row selection signal and the column line activated by the column selection signal can address at least one non-volatile memory cell of the memory block and operate in one of a programming mode, an erase mode and a read mode.

[0103] In summary, the novel nonvolatile memory cell, novel nonvolatile memory device, system on chip including the novel nonvolatile memory device and novel addressing method and memory control method implemented according to the present invention can prevent the nonvolatile memory cells or cell groups that are not addressed and not working from being disturbed by the nonvolatile memory cells or cell groups that are addressed and working, thereby obtaining the reliability of stable operation of the memory array.

Claims

1. A nonvolatile semiconductor memory device, comprising: Multiple lines; Multiple column lines; A row decoder generates a row selection signal according to a row address signal to activate a row line; a column decoder, generating a column selection signal according to a column address signal to activate a column line; and A memory array comprises: a plurality of non-volatile memory cells, each non-volatile memory cell being constructed at the intersection of the plurality of row lines and the plurality of column lines; Features: Each nonvolatile memory cell is coupled to one of a plurality of row lines via a row enable switch and is coupled to one of a plurality of column lines via at least one column enable switch, the row enable switch enables the activated row line to enable the nonvolatile memory cell according to the column enable signal, and the column enable switch enables the activated column line to enable the nonvolatile memory cell according to the row enable signal, so that the enabled nonvolatile memory cell operates in one of a programming mode, an erasing mode and a reading mode.

2. The nonvolatile semiconductor memory device according to claim 1, wherein: Except for the enabled nonvolatile memory cell, other disabled nonvolatile memory cells in the memory array are not electrically connected to the plurality of disabled and enabled row lines and column lines.

3. A system on chip, characterized in that: comprising: the nonvolatile semiconductor memory device as claimed in claim 1; and a power circuit electrically connected to the column decoder and the row decoder to provide the voltage or current required for the enabled non-volatile memory unit to operate in each mode.

4. An addressing method, characterized in that: The method is used to address at least one nonvolatile memory unit of a plurality of nonvolatile memory units, and each nonvolatile memory unit corresponds to at least one row line and at least one column line, and the addressing method includes: Generate a row selection signal according to a row address signal to start a row line; generating a column selection signal according to a column address signal to activate a column line; According to the column selection signal, the row line enables the at least one non-volatile memory unit; as well as According to the row selection signal, the column line enables the at least one nonvolatile memory cell, so that the at least one nonvolatile memory cell operates in one of a programming mode, an erasing mode and a reading mode.

5. A nonvolatile semiconductor memory device comprising: A row decoder generates a row selection signal according to a row address signal to activate one of the plurality of row lines; a column decoder, generating a column selection signal according to a column address signal to activate one of the plurality of column lines; and A memory array includes: a plurality of non-volatile memory cells, wherein the plurality of non-volatile memory cells are divided into a plurality of memory blocks; Features: Each nonvolatile memory cell in each memory block is electrically connected to a row segment line and at least one column segment line respectively; wherein each memory block comprises a row enable switch array and a column enable switch array, wherein the row enable switch array enables part of the row lines to be electrically connected to the row segment lines of the memory block according to the column enable signal, and the column enable switch array enables part of the column lines to be electrically connected to the column segment lines of the memory block according to the row enable signal.

6. The nonvolatile semiconductor memory device according to claim 5, wherein: According to the row selection signal and the column selection signal, one of the memory blocks is enabled, and according to the row line and the column line activated by the row selection signal and the column selection signal, at least one non-volatile memory cell of the enabled memory block is addressed to operate in one of a programming mode, an erasing mode and a reading mode.

7. The nonvolatile semiconductor memory device according to claim 6, wherein: The other disabled memory blocks are not electrically connected to the other disabled and enabled row lines and column lines.

8. A system on chip, characterized in that: comprising: a nonvolatile semiconductor memory device as claimed in claim 5; and a power circuit electrically connected to the column decoder and the row decoder to provide the voltage or current required for the enabled memory block to operate in each mode.

9. The system on chip according to claim 8, characterized in that It also includes a memory controller, which controls the row enable switch array according to the column selection signal to electrically connect part of the row lines to the row segment lines of the memory block; and controls the column enable switch array according to the row selection signal to electrically connect part of the column lines to the column segment lines of the memory block.

10. An addressing method, characterized in that: At least one nonvolatile memory unit of a plurality of nonvolatile memory units is addressed, and the plurality of nonvolatile memory units are divided into a plurality of memory blocks, each nonvolatile memory unit in each memory block is electrically connected to a row segment line and a column segment line, respectively, and the addressing method comprises: Generate a row selection signal according to a row address signal to start a row line; generating a column selection signal according to a column address signal to activate a column line; enabling one of the memory blocks according to the row selection signal and the column selection signal; electrically connecting part of the row lines to the row segment lines of the memory block according to the column strobe signal, and electrically connecting part of the column lines to the column segment lines of the memory block according to the row strobe signal; as well as According to the activated row line and the column line, at least one nonvolatile memory cell of the addressing memory block operates in one of a programming mode, an erasing mode and a reading mode.

11. The addressing method according to claim 10, characterized in that: The invention also includes: configuring a row enable switch array and a column enable switch array for each memory block, wherein the row enable switch array controls part of the row lines to be electrically connected to the row segment lines of the memory block, and the column enable switch array controls part of the column lines to be electrically connected to the column segment lines of the memory block.

12. The addressing method according to claim 10, characterized in that: Also includes: According to the column selection signal, the row enable switch array of the memory block is controlled to electrically connect some row lines to the row segment lines of the memory block, wherein some row lines include the activated row lines; and according to the row selection signal, the column enable switch array of the memory block is controlled to electrically connect some column lines to the column segment lines of the memory block, wherein some column lines include the activated column lines.

13. A method for laying out a memory array, comprising: Disposing a plurality of row lines and a plurality of column lines on a metal layer of a substrate; and A plurality of memory blocks are planned on the component layer of the substrate, each memory block is configured with a plurality of non-volatile memory units, and each non-volatile memory unit is configured at the intersection of a row line and a column line; the characteristics are: A plurality of row segment lines and a plurality of column segment lines are arranged on the metal layer corresponding to the memory block, and each non-volatile memory cell of the memory block is electrically connected to a corresponding row segment line and a corresponding column segment line; At the element layer, at least one row enable switch array and / or at least one column enable switch array is configured between adjacent memory blocks, wherein the row enable switch array controls a portion of row lines to be electrically connected to the plurality of row segment lines of the memory block, and the column enable switch array controls a portion of column lines to be electrically connected to the plurality of column segment lines of the memory block.

14. A memory control method, characterized in that: For controlling the non-volatile semiconductor memory device as claimed in claim 5, comprising: According to the column selection signal, controlling the row enable switch array to electrically connect part of the row lines to the row segment lines of the memory block; and According to the row selection signal, the column enable switch array is controlled to electrically connect part of the column lines to the column segment lines of the memory block.

15. The memory control method according to claim 14, wherein: The invention also includes: when at least one non-volatile memory cell of the memory block is completed in one of the programming mode, the erasing mode and the reading mode, the potential of the activated row line and the column line is first controlled to drop to 0V, and then the row enable switch and the column enable switch are controlled to be closed, so that the non-volatile memory cell that has completed the operation is electrically isolated from the row line and the column line and enters an idle state.

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