Wafer cutting method

Abstract

According to the wafer cutting method provided by the invention, the metal protection layer is formed before the photoetching process, and the basic requirement of the thickness of the metal protection layer is that a photoetching machine can accurately identify and align the Mark in the photoetching process so as to realize accurate alignment. After the photoetching process is completed and the first etching groove is formed, the metal hard mask layer is formed, at the moment, the metal hard mask layer and the metal protection layer serve as a hard mask for follow-up etching, especially a hard mask for etching a silicon substrate together, and due to the fact that the process is only the etching process but not the photoetching process, the etching process is simplified. The thickness of the metal hard mask layer is not limited when a photoetching machine recognizes and aligns the Mark, so that the metal hard mask layer can provide sufficient thickness to meet the requirement for the thickness of the hard mask during etching, in addition, parameters such as the thickness and the material of the metal hard mask layer can be designed according to different product specification requirements, and the manufacturing cost is reduced. A more flexible hard mask structure is provided for the wafer cutting process, and the application range is wide.

Description

Technical Field

[0001] The present invention relates to the technical field of wafer cutting technology, and in particular to a wafer cutting method. Background Art

[0002] In hybrid bonding technology (HB), wafer to wafer (W2W) bonding and chip to wafer (C2W) bonding are the two main bonding methods. Among them, W2W bonding directly bonds two wafers to achieve electrical connection and physical stacking between wafers, which is particularly suitable for homogeneous or heterogeneous wafer stacking in large-scale production. C2W bonding has higher flexibility by directly packaging the chip onto the wafer, and can adapt to chips of different types and sizes, making the 3D stacking configuration more diverse.

[0003] Currently, in C2W bonding technology, wafers need to be cut into individual chips through a dicing process before hybrid bonding. Figure 1 and Figure 2 As shown, the metal layer 202 needs to be introduced in the process of cutting the wafer 20 into individual chips, which is used to protect the bonding interface during the photolithography process and as a hard mask layer when etching the silicon substrate 200. Figure 2 As shown, when the metal layer 202 acts as a hard mask layer, the thickness of the metal layer 202 needs to be as thick as possible to ensure that the bonding interface is not exposed during the etching process. However, an overly thick metal layer 202 may be exposed during photolithography (such as Figure 1 As shown in the figure, the lithography machine cannot recognize the alignment mark. When the metal layer 202 is too thin, it cannot provide sufficient blocking effect during the silicon etching process. This problem has become the main blocking point of the current wafer LG cutting route. Summary of the invention

[0004] In view of the shortcomings of the prior art mentioned above, the purpose of the present invention is to provide a wafer cutting method for solving the problem that in the prior art, the metal layer introduced in the wafer LG cutting route needs to be relatively thin during the photolithography process to protect the Bonding interface, but needs to be relatively thick when etching the silicon substrate as a hard mask layer, resulting in the thickness of the metal layer becoming the main blocking point for improving the yield of the current wafer LG cutting route.

[0005] To achieve the above object and other related objects, the present invention provides a wafer cutting method, which comprises the following steps:

[0006] S1. Provide a wafer to be cut with a plurality of cutting paths, wherein the wafer to be cut comprises a silicon substrate, a rewiring layer and a bonding layer in sequence along a thickness direction; wherein the rewiring layer comprises a wiring dielectric layer and a metal wiring layer, and the bonding layer comprises a bonding dielectric layer and a bonding metal layer;

[0007] S2, forming a metal protective layer on the surface of the bonding layer;

[0008] S3, using a photolithography process to sequentially etch the metal protection layer, the bonding layer and a portion of the wiring dielectric layer along the cutting path to form a first etching groove;

[0009] S4, forming a metal hard mask layer on the surface of the first etching groove and the surface of the metal protection layer;

[0010] S5, using the metal hard mask layer and the metal protection layer as masks and adopting a laser etching process based on the first etching groove to sequentially etch the remaining thickness of the rewiring layer and a part of the thickness of the silicon substrate to form a second etching groove;

[0011] S6, continuing to etch the silicon substrate downward along the cutting path and according to the width of the first etching groove until stopping at a preset depth in the silicon substrate;

[0012] S7, thinning the back side of the silicon substrate to at least completely separate all the cutting paths;

[0013] S8. removing the metal hard mask layer and the metal protection layer to form an independent chip.

[0014] Optionally, in step S3, when etching the wiring dielectric layer, the position of the uppermost metal wiring layer in the rewiring layer corresponding to the cutting path is used as the etching stop point.

[0015] Optionally, the overall width of the metal wiring layer of the rewiring layer corresponding to the cutting road is W1, the width of the first etching groove is W2, the width of the second etching groove is W3, and W2>W3≥W1.

[0016] Further, step S6 includes:

[0017] S61, using a first plasma cutting technology to etch the remaining wiring dielectric layer downward along the cutting path direction and according to the width of the first etching groove until the surface of the silicon substrate is exposed;

[0018] S62, using a second plasma cutting technology to etch the silicon substrate downward along the cutting path direction and according to the width of the first etching groove until stopping at a preset depth in the silicon substrate.

[0019] Optionally, the metal protective layer is a single layer structure of a titanium layer or a titanium nitride layer, or a stacked structure of a titanium layer and a titanium nitride layer; the metal hard mask layer is a single layer structure of a titanium layer or a titanium nitride layer, or a stacked structure of a titanium layer and a titanium nitride layer.

[0020] Furthermore, the thickness of the metal protective layer is

[0021] Optionally, the thickness of the metal protection layer is smaller than the thickness of the metal hard mask layer.

[0022] Furthermore, the thickness of the metal hard mask layer is set according to the etching depth of the silicon substrate in step S6, and the setting principle is that the deeper the etching depth of the silicon substrate in step S6, the thicker the thickness of the metal hard mask layer.

[0023] Optionally, the metal protection layer and the metal hard mask layer are formed by deposition using a PVD process.

[0024] Optionally, a cleaning step is further included after step S5 and before step S6.

[0025] As described above, the wafer cutting method of the present invention forms a metal protective layer before the photolithography process. Since the subsequent first etching groove only etches to a part of the thickness in the wiring dielectric layer, the etching depth is shallow, and the thickness requirement of the metal protective layer is low, so the basic requirement of the thickness of the metal protective layer is to enable the photolithography machine to accurately identify the alignment mark in the photolithography process to achieve precise alignment. In addition, the thickness of the metal protective layer can also be adjusted according to actual requirements on this basis. After the photolithography process is completed to form the first etching groove, a metal hard mask layer is formed. At this time, the metal hard mask layer and the metal protective layer are used together as a hard mask for subsequent etching, especially for etching the silicon substrate. Since the process only has an etching process but no photolithography process, there is no thickness restriction of the metal hard mask layer by the photolithography machine to identify the alignment mark, so the metal hard mask layer can provide sufficient thickness to meet the requirements of the hard mask thickness during etching. In addition, the thickness, material and other parameters of the metal hard mask layer can be designed according to different product specification requirements, providing a more flexible hard mask structure for the wafer cutting process, with a wide range of applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a schematic diagram of a partial cross-sectional structure of a photoresist layer formed on a wafer to be cut in the prior art.

[0027] Figure 2 It is a schematic diagram of a partial cross-sectional structure of an etched groove formed on a wafer to be cut by a laser etching process in the prior art.

[0028] Figures 3 to 16It is a schematic diagram of the partial cross-sectional structure of each step in the wafer cutting method of the present invention.

[0029] Component number description

[0030] 10 Wafers to be cut

[0031] 101 Cutting Road

[0032] 102 Chip Area

[0033] 103 Silicon substrate

[0034] 104 Rewiring Layer

[0035] 105 Wiring dielectric layer

[0036] 106 Metal Wiring Layer

[0037] 107 Bonding layer

[0038] 108 bonding dielectric layer

[0039] 109 Bonding metal layer

[0040] 11 Metal protective layer

[0041] 110 Photoresist layer

[0042] 111 Patterned photoresist layer

[0043] 12 First etching groove

[0044] 13 Metal Hard Mask Layer

[0045] 14 Second etching groove

[0046] 15 First protective adhesive layer

[0047] 16 Second protective adhesive layer

[0048] 17 Chip

[0049] 20 Wafer

[0050] 200 Silicon substrate

[0051] 201 Photoresist layer

[0052] 202 Metal Layer DETAILED DESCRIPTION

[0053] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0054] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0055] For ease of description, spatial relational terms such as “under”, “below”, “below”, “below”, “over”, etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatial relational terms are intended to include other orientations of the device in use or operation in addition to the orientation depicted in the drawings, and may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, so that the first and second features may not be in direct contact. In addition, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or one or more intervening layers may also be present.

[0056] See also Figures 3 to 16 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0057] This embodiment provides a wafer cutting method, and the wafer cutting method comprises the following steps:

[0058] S1. Provide a wafer to be cut with a plurality of cutting paths, wherein the wafer to be cut comprises a silicon substrate, a rewiring layer and a bonding layer in sequence along a thickness direction; wherein the rewiring layer comprises a wiring dielectric layer and a metal wiring layer, and the bonding layer comprises a bonding dielectric layer and a bonding metal layer;

[0059] S2, forming a metal protective layer on the surface of the bonding layer;

[0060] S3, using a photolithography process to sequentially etch the metal protection layer, the bonding layer and a portion of the wiring dielectric layer along the cutting path to form a first etching groove;

[0061] S4, forming a metal hard mask layer on the surface of the first etching groove and the surface of the metal protection layer;

[0062] S5, using the metal hard mask layer and the metal protection layer as masks and adopting a laser etching process based on the first etching groove to sequentially etch the remaining thickness of the rewiring layer and a part of the thickness of the silicon substrate to form a second etching groove;

[0063] S6, continuing to etch the silicon substrate downward along the cutting path and according to the width of the first etching groove until stopping at a preset depth in the silicon substrate;

[0064] S7, thinning the back side of the silicon substrate to at least completely separate all the cutting paths;

[0065] S8. removing the metal hard mask layer and the metal protection layer to form an independent chip.

[0066] The wafer cutting method of this embodiment forms a metal protective layer before the photolithography process. Since the subsequent first etching groove only etches to a part of the thickness of the wiring dielectric layer, the etching depth is shallow, and the thickness requirement of the metal protective layer is low, the basic requirement of the thickness of the metal protective layer is to enable the photolithography machine to accurately identify the alignment mark in the photolithography process to achieve precise alignment. In addition, the thickness of the metal protective layer can be adjusted according to actual requirements on this basis. After the photolithography process is completed to form the first etching groove, a metal hard mask layer is formed. At this time, the metal hard mask layer and the metal protective layer are used together as a hard mask for subsequent etching, especially for etching the silicon substrate. Since the process only has an etching process but no photolithography process, there is no thickness restriction of the metal hard mask layer by the photolithography machine to identify the alignment mark. Therefore, the metal hard mask layer can provide sufficient thickness to meet the requirements of the hard mask thickness during etching. In addition, the thickness, material and other parameters of the metal hard mask layer can be designed according to different product specification requirements, providing a more flexible hard mask structure for the wafer cutting process, which has a wide range of applications.

[0067] The wafer cutting method of this embodiment is described in detail below with reference to the specific drawings.

[0068] like Figure 3 As shown, step S1 is first performed to provide a wafer 10 to be cut having a plurality of cutting lanes 101, wherein the wafer 10 to be cut includes a silicon substrate 103, a rewiring layer 104 and a bonding layer 107 in sequence along the thickness direction; wherein the rewiring layer 104 includes a wiring dielectric layer 105 and a metal wiring layer 106, and the bonding layer 107 includes a bonding dielectric layer 108 and a bonding metal layer 109.

[0069] like Figure 3As shown, the wafer 10 to be cut is generally divided into a chip area 102 and a cutting road 101 between the chip areas 102. After the chip process preparation is completed, the wafer 10 to be cut is divided into independent chips through the cutting road 101. For ease of understanding, the drawings of this embodiment are described by taking the cutting road 101 between two chip areas 102 as an example, and those skilled in the art can easily understand the implementation process of the cutting method of this embodiment on the entire wafer 10 to be cut.

[0070] The size of the silicon substrate 103 is set as required, such as the common 6 inches, 8 inches, 12 inches, etc.; in addition, the thickness of the silicon substrate 103 is also set as required. A device structure is formed in the silicon substrate 103. Since the focus of this embodiment is on the cutting process after the wafer preparation is completed, the device structure formed in the silicon substrate 103 is not shown in the drawings. In addition, the structure of the rewiring layer 104 is designed according to the specific requirements of different device structures, and no excessive restrictions are made here, as long as the rewiring layer 104 can realize the rearrangement of the circuit of the device structure in the silicon substrate 103 in a preset manner.

[0071] In addition, after the wafer cutting method of this embodiment is completed to cut into single chips, it is necessary to implement the C2W bonding process, so it is generally necessary to lead out the metal wiring layer 106 in the rewiring layer 104 through the bonding metal layer 109 in the bonding layer 107 to facilitate the subsequent bonding process.

[0072] As an example, the material of the wiring dielectric layer 105 includes one or a combination of two or more of the group consisting of epoxy resin, silicone, PI, PBO, BCB, silicon oxide, phosphosilicate glass and fluorine-containing glass or other low-k dielectric materials; the material of the metal wiring layer 104 includes one or a combination of two or more of the group consisting of copper, aluminum, nickel, gold, silver and titanium. In this embodiment, the material of the metal wiring layer 104 mainly includes copper.

[0073] like Figure 4 As shown, step S2 is then performed to form a metal protective layer 11 on the surface of the bonding layer 107. The basic requirement for the thickness of the metal protective layer 11 is to enable the photolithography machine to accurately identify the alignment mark in the subsequent photolithography process to achieve precise alignment. On this basis, the thickness of the metal protective layer 11 is adjustable.

[0074] The material of the metal protective layer 11 is not overly restricted, as long as it can play a better hard mask effect later. For example, it can be titanium, titanium nitride or other titanium metal derivatives. The metal protective layer 11 can be a single-layer structure of these materials, or a stacked structure in which single-layer structures formed by different materials are superimposed on each other. In this embodiment, it is preferred that the material of the metal protective layer 11 is mainly a titanium layer formed by titanium. In addition, the method of forming the metal protective layer 11 is not overly restricted. For example, it can be a suitable deposition process such as CVD, ALD or PVD. In this embodiment, the PVD process is preferably used to deposit the metal protective layer 11. Since the temperature of the PVD process is relatively low, the impact on the device structure in the wafer 10 to be cut is relatively small.

[0075] When the metal protective layer 11 is a titanium layer, the thickness of the metal protective layer 11 is selected to be Preferably choose

[0076] like Figure 8 As shown, step S3 is then performed to sequentially etch the metal protection layer 11 , the bonding layer 107 and a portion of the wiring dielectric layer 105 along the cutting path 101 using a photolithography process to form a first etched groove 12 .

[0077] Generally, a metal wiring layer 106 will also be formed in the rewiring layer 104 in the corresponding area of ​​the cutting path 101. At this time, when etching to form the first etching groove 12, the etching thickness of the wiring dielectric layer 105 takes the metal wiring layer 106 located at the top as a reference point, that is, etching until the metal wiring layer 106 at the top is exposed (equivalent to using the metal wiring layer 106 located at the top of the rewiring layer 104 as the etching stop point when forming the first etching groove 12). At this time, the overall width of the metal wiring layer 106 of the rewiring layer 104 corresponding to the cutting path 101 is defined as W1, and the width of the first etching groove 12 is W2, then W2≥W1, that is, the width W2 of the first etching groove must not be less than the overall width W1 of the metal wiring layer, so as to ensure that the metal wiring layer 106 corresponding to the cutting path 101 is completely removed later.

[0078] like Figures 5 to 8 As shown, as a specific example, the method of forming the first etching groove 12 by using the photolithography process includes:

[0079] S31, such as Figure 5 As shown, a photoresist layer 110 is coated on the surface of the metal protection layer 11;

[0080] S32, such as Figure 6As shown, after using an alignment device to ensure that the wafer 10 to be cut is accurately aligned with the design pattern, a photolithography machine is used for exposure, and after exposure, development is performed to obtain a patterned photoresist layer 111;

[0081] S33, such as Figure 7 As shown, the metal protection layer 11, the bonding layer 107 and a part of the wiring dielectric layer 105 are sequentially etched based on the patterned photoresist layer 111, preferably, dry etching is adopted;

[0082] S34, such as Figure 8 As shown, the patterned photoresist layer 111 is removed to obtain the first etching groove 12. For example, the patterned photoresist layer 111 can be removed by using conventional wet process, dry process or ashing process, which is selected according to actual conditions.

[0083] like Fig. 9 As shown, step S4 is then performed to form a metal hard mask layer 13 on the surface of the first etching groove 12 (ie, the bottom wall and side wall of the first etching groove 12 ) and the surface of the metal protection layer 11 .

[0084] The metal hard mask layer 13 and the metal protective layer 11 serve as hard masks in the subsequent etching process. Therefore, when the adjustable range of the thickness of the metal protective layer 11 is small, the material and thickness of the metal hard mask layer 13 can be flexibly adjusted to meet the hard mask thickness required for subsequent etching.

[0085] In this embodiment, the material of the metal hard mask layer 13 is not overly limited, as long as it can achieve a better hard mask effect later. For example, it can be titanium, titanium nitride or other titanium metal derivatives. The metal hard mask layer 13 can be a single-layer structure of these materials, or a stacked structure in which single-layer structures formed by different materials are superimposed on each other. In this embodiment, the metal hard mask layer 13 is selected to be a single-layer structure of a titanium layer or a titanium nitride layer, or a stacked structure composed of a titanium layer and a titanium nitride layer. In addition, the method of forming the metal hard mask layer 13 is not overly limited, for example, it can be a suitable deposition process such as CVD, ALD or PVD. In this embodiment, the PVD process is preferably used to deposit the metal hard mask layer 13. Since the PVD process temperature is relatively low, the impact on the device structure in the wafer 10 to be cut is relatively small.

[0086] As an example, the thickness of the metal protection layer 11 is less than the thickness of the metal hard mask layer 13. In principle, the deeper the etching depth of the silicon substrate 103 is, the thicker the metal hard mask layer 13 needs to be. For example, when the metal protection layer 11 is a titanium layer, the thickness of the metal protection layer 11 is selected to be At this time, when the material of the metal hard mask layer 13 is a single-layer structure of a titanium layer or a titanium nitride layer, or a stacked-layer structure consisting of a titanium layer and a titanium nitride layer, the thickness of the metal hard mask layer 13 is selected to be Preferably

[0087] like Fig.10 and Fig.11 As shown, step S5 is then performed, using the metal hard mask layer 13 and the metal protective layer 11 as masks and based on the first etching groove 12, a laser etching process is used to sequentially etch the remaining thickness of the rewiring layer 104 and a partial thickness of the silicon substrate 103 to form a second etching groove 14.

[0088] Laser etching is a technology that uses a high-energy laser beam to locally heat the surface of a material, causing it to melt, evaporate, or undergo chemical changes to form the desired pattern or text. This technology has important applications in semiconductor manufacturing, especially in etching copper layers.

[0089] Laser etching usually uses a laser etcher, which consists of a laser source (such as a fiber laser or UV laser), a focusing system, and a precision optical scanning system. The laser source generates a high-energy laser beam, which forms a high-power density laser spot through the focusing system, and the optical scanning system controls the movement of the laser beam on the surface of the material to form the desired pattern. When the laser beam contacts the material, it will generate extremely high temperatures, causing the material to melt or evaporate rapidly.

[0090] The width W3 of the second etching groove is not excessively limited, as long as W1≤W3≤W2 is satisfied. Fig.11 As shown, W3 = W2, such as Fig.10 As shown, W2>W3.

[0091] As described above, during the laser etching process, since the rewiring layer 104 contains a metal wiring layer 106 in addition to the wiring medium layer 105, the material layer in the high-temperature melting cutting path 101 will produce slag, which will contaminate the surface of the bonding layer, affect the cleanliness of the surface of the bonding layer, and reduce the quality and stability of subsequent bonding. Therefore, the width W3 of the second etched groove can be reduced during the laser etching process of this step, even if W2>W3. This makes it easier to leave the slag generated by laser etching on the side wall steps of the second etched groove 14 to avoid contaminating the surface of the bonding layer.

[0092] like Fig.12 As shown, step S6 is then performed to continue etching the silicon substrate 103 downward along the cutting path 101 and according to the width W2 of the first etching groove 12 until the etching stops at a preset depth in the silicon substrate 103 .

[0093] As a preferred example, a cleaning step is further included after step S5 and before step S6 to clean the slag generated by the laser etching.

[0094] like Fig.10 As shown, when W2>W3, that is, the width of the formed second etching groove 14 is smaller than the width of the first etching groove 12, this step S6 includes:

[0095] S61, using a first plasma cutting technology to etch the remaining wiring dielectric layer 105 downward along the cutting path 101 and according to the width W2 of the first etching groove until the surface of the silicon substrate 103 is exposed, and the first plasma cutting technology may be, for example, an inductively coupled plasma cutting technology;

[0096] S62, using a second plasma cutting technology to etch the silicon substrate 103 downward along the cutting path 101 and according to the width W2 of the first etching groove until stopping at a preset depth in the silicon substrate 103. The second plasma cutting technology may be, for example, a capacitively coupled plasma cutting technology.

[0097] like Fig.14 As shown, step S7 is then performed to thin the back side of the silicon substrate 103 so as to completely separate at least all the cutting paths 101 .

[0098] As an example, Fig.14 As shown, before the back side thinning of the silicon substrate 103 is performed, a first protective adhesive layer 15 may be applied to the surface of the metal hard mask layer 13, and then the wafer 10 to be cut may be turned over. The first protective adhesive layer 15 may protect the front side of the wafer 10 to be cut during the back side thinning process, and prevent the wafer 10 to be cut from being physically damaged during the back side thinning. At the same time, the first protective adhesive layer 15 may also prevent the wafer 10 to be cut from shifting during the thinning process.

[0099] As an example, the CMP process is used to thin the back side. The thinning thickness is set according to actual needs, and the grinding can be stopped when the cutting road 101 is separated, or it can continue to grind to a certain thickness after the cutting road 101 is separated.

[0100] like Fig.16 As shown, step S8 is finally performed to remove the metal hard mask layer 13 and the metal protection layer 11 to form an independent chip 17 .

[0101] As an example, Fig.15As shown, before removing the metal hard mask layer 13 and the metal protective layer 11, a second protective adhesive layer 16 may be first applied to the thinned surface of the silicon substrate 103, and then the wafer 10 to be cut separated by the cutting path 101 is flipped over, and then the first protective adhesive layer 15 is removed.

[0102] As an example, a high selectivity inorganic liquid wet method is selected to remove the metal hard mask layer 13 and the metal protection layer 11 .

[0103] In summary, the present invention provides a wafer cutting method, by forming a metal protective layer before the photolithography process, since the subsequent first etching groove is only etched to a part of the thickness in the wiring dielectric layer, the etching depth is shallow, and the thickness requirement of the metal protective layer is low, so the basic requirement of the thickness of the metal protective layer is to enable the photolithography machine to accurately identify the alignment mark in the photolithography process to achieve precise alignment, and the thickness of the metal protective layer can also be adjusted according to actual requirements on this basis. After the photolithography process is completed to form the first etching groove, a metal hard mask layer is formed. At this time, the metal hard mask layer and the metal protective layer are used together as a hard mask for subsequent etching, especially for etching the silicon substrate. Since the process only has an etching process but no photolithography process, there is no thickness restriction of the metal hard mask layer by the photolithography machine to identify the alignment mark, so the metal hard mask layer can provide sufficient thickness to meet the requirements of the hard mask thickness during etching. In addition, the thickness, material and other parameters of the metal hard mask layer can be designed according to different product specification requirements, providing a more flexible hard mask structure for the wafer cutting process, with a wide range of applications. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0104] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A wafer cutting method, characterized in that: The wafer cutting method comprises the following steps: S1. Provide a wafer to be cut with a plurality of cutting paths, wherein the wafer to be cut comprises a silicon substrate, a rewiring layer and a bonding layer in sequence along a thickness direction; wherein the rewiring layer comprises a wiring dielectric layer and a metal wiring layer, and the bonding layer comprises a bonding dielectric layer and a bonding metal layer; S2, forming a metal protective layer on the surface of the bonding layer; S3, using a photolithography process to sequentially etch the metal protection layer, the bonding layer and a portion of the wiring dielectric layer along the cutting path to form a first etching groove; S4, forming a metal hard mask layer on the surface of the first etching groove and the surface of the metal protection layer; S5, using the metal hard mask layer and the metal protection layer as masks and adopting a laser etching process based on the first etching groove to sequentially etch the remaining thickness of the rewiring layer and a part of the thickness of the silicon substrate to form a second etching groove; S6, continuing to etch the silicon substrate downward along the cutting path and according to the width of the first etching groove until stopping at a preset depth in the silicon substrate; S7, thinning the back side of the silicon substrate to at least completely separate all the cutting paths; S8. removing the metal hard mask layer and the metal protection layer to form an independent chip.

2. The wafer cutting method according to claim 1, characterized in that: In step S3, when etching the wiring dielectric layer, the position of the uppermost metal wiring layer in the rewiring layer corresponding to the cutting path is used as the etching stop point.

3. The wafer cutting method according to claim 1, characterized in that: The overall width of the metal wiring layer of the rewiring layer corresponding to the cutting road is W1, the width of the first etching groove is W2, the width of the second etching groove is W3, and W2>W3≥W1.

4. The wafer cutting method according to claim 3, characterized in that: Step S6 includes: S61, using a first plasma cutting technology to etch the remaining wiring dielectric layer downward along the cutting path direction and according to the width of the first etching groove until the surface of the silicon substrate is exposed; S62, using a second plasma cutting technology to etch the silicon substrate downward along the cutting path direction and according to the width of the first etching groove until stopping at a preset depth in the silicon substrate.

5. The wafer cutting method according to claim 1, characterized in that: The metal protective layer is a single layer structure of titanium layer or titanium nitride layer, or a stacked structure of titanium layer and titanium nitride layer; the metal hard mask layer is a single layer structure of titanium layer or titanium nitride layer, or a stacked structure of titanium layer and titanium nitride layer.

6. The wafer cutting method according to claim 5, characterized in that: The thickness of the metal protective layer is 7. The wafer cutting method according to claim 1, characterized in that: The thickness of the metal protection layer is smaller than the thickness of the metal hard mask layer.

8. The wafer cutting method according to claim 7, characterized in that: The thickness of the metal hard mask layer is set according to the etching depth of the silicon substrate in step S6 , and the setting principle is that the deeper the etching depth of the silicon substrate in step S6 , the thicker the thickness of the metal hard mask layer.

9. The wafer cutting method according to claim 1, characterized in that: The metal protection layer and the metal hard mask layer are formed by deposition using a PVD process.

10. The wafer cutting method according to claim 1, characterized in that: A cleaning step is further included after step S5 and before step S6.

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