Power module

Abstract

The invention discloses a power module, and belongs to the technical field of semiconductors. The power module includes: a substrate including a conductive layer; the plurality of chips are connected to the conductive layer, and the plurality of chips are arranged side by side along a first direction; the isolation structures penetrate through the conducting layer and extend in the second direction, the isolation structures are arranged between the adjacent chips in the first direction, and the second direction is perpendicular to the first direction. Under the condition that the size of the power module is not increased, the thermal coupling effect between the chips is reduced, the uniformity of temperature distribution between the chips is improved, the heat dissipation efficiency of the power module is improved, the reliability of the power module is improved, and the service life of the power module is prolonged.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular, relates to a power module. Background Art

[0002] The side-by-side arrangement of the chips in the power module will lead to a strong thermal coupling effect between the chips and uneven temperature distribution between the chips, which will affect the heat dissipation efficiency of the power module, thereby causing problems such as local overheating of the power module and material stress failure, thereby affecting the reliability and life of the power module.

[0003] Related technologies reduce the thermal coupling effect by increasing the chip spacing or adjusting the chip layout to stagger the chips. However, these methods will increase the volume of the power module, which is not conducive to the miniaturization design of the power module. Summary of the invention

[0004] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a power module that can reduce the thermal coupling effect between chips, improve the uniformity of temperature distribution between chips, improve the heat dissipation efficiency of the power module, and thus improve the reliability and life of the power module without increasing the volume of the power module.

[0005] The present application provides a power module, comprising:

[0006] a substrate including a conductive layer;

[0007] A plurality of chips are connected to the conductive layer, and the plurality of chips are arranged side by side along a first direction;

[0008] The isolation structure penetrates the conductive layer and extends along a second direction. The isolation structure is provided between the chips adjacent to each other along the first direction. The second direction is perpendicular to the first direction.

[0009] According to an embodiment of the present application, the isolation structure includes an isolation trench.

[0010] According to an embodiment of the present application, the isolation structure is located in the middle between the two adjacent chips.

[0011] According to an embodiment of the present application, the length of the isolation structure along the second direction is greater than or equal to L and less than or equal to 6 / 5*L, where L is the length of the chip along the second direction.

[0012] According to an embodiment of the present application, the width of the isolation structure along the first direction is 0.5-0.6 mm.

[0013] According to an embodiment of the present application, the length of the isolation structure along the second direction is positively correlated with the power level of the chip.

[0014] According to one embodiment of the present application, the multiple chips include a plurality of upper bridge chips arranged in parallel and a plurality of lower bridge chips arranged in parallel; the multiple upper bridge chips are arranged side by side along the first direction, and the isolation structure is provided between adjacent upper bridge chips; the multiple lower bridge chips are arranged side by side along the first direction, and the isolation structure is provided between adjacent lower bridge chips.

[0015] According to one embodiment of the present application, the chip includes a silicon carbide device, a silicon device or a gallium nitride device.

[0016] According to an embodiment of the present application, the substrate further includes a heat conducting layer and a heat dissipation layer; the heat conducting layer is located on a side of the conductive layer away from the chip, and the heat dissipation layer is located on a side of the heat conducting layer away from the conductive layer.

[0017] According to one embodiment of the present application, the substrate includes a DBC substrate or an AMB substrate.

[0018] The above one or more technical solutions in the embodiments of the present application have at least one of the following technical effects:

[0019] By arranging a plurality of chips side by side along a first direction on a conductive layer of a substrate, and arranging an isolation structure between adjacent chips along the first direction, the isolation structure penetrates the conductive layer and extends along a second direction, thereby improving the thermal resistance between adjacent chips, reducing the transfer of heat in the first direction, reducing the heat conduction and thermal coupling effects between adjacent chips, improving the uniformity of temperature distribution between adjacent chips, improving the heat dissipation efficiency of the power module, reducing the risks of local overheating and material stress failure of the power module, and thereby improving the reliability and life of the power module, without increasing the chip spacing or staggering the chips, thereby avoiding increasing the volume of the power module, and facilitating the miniaturized design of the power module.

[0020] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0022] Figure 1 is a top view of a power module provided in an embodiment of the present application;

[0023] Figure 2 is a cross-sectional schematic diagram of a power module provided in an embodiment of the present application;

[0024] Figure 3 is a schematic diagram of the structure of a power module provided in an embodiment of the present application;

[0025] Figure 4 It is a side view of the power module provided in an embodiment of the present application. DETAILED DESCRIPTION

[0026] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0027] The power module provided in the embodiments of the present application is described below with reference to the accompanying drawings.

[0028] Figure 1 A top view of a power module provided in an embodiment of the present application, Figure 2 A schematic cross-sectional view of a power module provided in an embodiment of the present application.

[0029] like Figure 1 and Figure 2 As shown, the power module provided in the embodiment of the present application includes a substrate 1, a plurality of chips 2 and an isolation structure 3.

[0030] The substrate 1 includes a conductive layer 11. The substrate 1 may be a laminated structure along a thickness direction H, and the conductive layer 11 may be located on the top layer of the substrate 1. The material of the conductive layer 11 may include metals such as copper. The conductive layer 11 has good conductivity, and the circuit division of the power module may be performed on the conductive layer 11 to achieve electrical connection between various devices in the power module.

[0031] The multiple chips 2 are connected to the conductive layer 11, and the multiple chips 2 are arranged side by side along a first direction X. The first direction X is perpendicular to the thickness direction H. The multiple chips 2 may have the same size, and the multiple chips 2 may also be of the same chip type.

[0032] The plurality of chips 2 may constitute at least one row of chips, and the at least one row of chips is spaced apart on the conductive layer 11 along the second direction Y. The number of chips 2 in different rows of chips may be the same. Each row of chips may include at least two chips 2, and all chips 2 in each row of chips are spaced apart along the first direction X. All chips 2 in each row of chips are arranged side by side, that is, all chips 2 in each row of chips are aligned along the first side of the second direction Y, and all chips 2 in each row of chips are aligned along the second side of the second direction Y.

[0033] For example Figure 1As shown, the plurality of chips 2 may form two rows of chips, and the two rows of chips are spaced apart along the second direction Y. Each row of chips includes five chips 2, and the five chips 2 in each row of chips are spaced apart along the first direction X.

[0034] It should be noted that the chip type, size and quantity of the chip 2 can be determined according to actual application requirements and are not specifically limited here.

[0035] like Figure 1 and Figure 2 As shown, the isolation structure 3 penetrates the conductive layer 11 and extends along the second direction Y. There is an isolation structure 3 between the chips 2 adjacent to each other along the first direction X. The first direction X, the second direction Y and the thickness direction H are perpendicular to each other.

[0036] The power module may include at least one isolation structure 3. There is an isolation structure 3 between any two adjacent chips 2 in each row of chips, and the isolation structure 3 is spaced apart from the two adjacent chips 2 along the first direction X. The isolation structure 3 penetrates the conductive layer 11 along the thickness direction H, that is, the thickness of the isolation structure 3 may be equal to the thickness of the conductive layer 11. The isolation structure 3 extends along the second direction Y, and the isolation structure 3 extends along the second direction Y at least to a first position and a second position, the first position is flush with the first side of the two adjacent chips 2 along the second direction Y, and the second position is flush with the second side of the two adjacent chips 2 along the second direction Y, so as to isolate the two adjacent chips 2 in each row of chips.

[0037] The number of isolation structures 3 can be determined according to the number of rows of chips 2 in the power module and the number of chips 2 in each row of chips. For example, when the power module includes two rows of chips and each row of chips includes five chips 2, eight isolation structures 3 can be provided.

[0038] In this embodiment, a plurality of chips 2 are arranged side by side along a first direction X on the conductive layer 11 of the substrate 1, an isolation structure 3 is arranged between the chips 2 adjacent to each other along the first direction X, the isolation structure 3 penetrates the conductive layer 11 and extends along the second direction Y, the thermal resistance between the chips 2 adjacent to each other along the first direction X is improved, the heat transfer between the adjacent chips 2 along the first direction X is reduced, the heat conduction and thermal coupling effects between the adjacent chips 2 are reduced, the uniformity of the temperature distribution between the adjacent chips 2 is improved, the heat dissipation efficiency and the thermal management efficiency of the power module are improved, the risks of local overheating and material stress failure of the power module are reduced, and the reliability and life of the power module are improved, while the burden of the external heat dissipation system is reduced, and there is no need to increase the chip spacing, adjust the layout to make the chips staggered, increase the volume of the power module, and limit the integration of the power module, thereby realizing a compact layout design of the power module, which is conducive to the miniaturization design of the power module.

[0039] Related technologies also optimize heat dissipation efficiency by using materials with high thermal conductivity in power modules, but materials with high thermal conductivity have poor electrical insulation performance, and this approach cannot balance the electrical insulation performance and thermal management efficiency of the power module. This embodiment reduces the thermal conduction and thermal coupling effects of the chip by providing an isolation structure 3 in the power module, without the need to introduce materials with high thermal conductivity, so that the power module improves thermal management efficiency while meeting electrical safety requirements, and achieves the goal of maintaining the structural integrity and electrical performance of the substrate 1 while minimizing the thermal coupling effect.

[0040] In some embodiments, the isolation structure 3 includes an isolation groove, which penetrates the conductive layer 11 along the thickness direction H and extends along the second direction Y. The thickness of the isolation groove is equal to the thickness of the conductive layer 11. The isolation groove extends at least to a first position and a second position along the second direction Y, the first position is flush with the first side of the two adjacent chips 2 along the second direction Y, and the second position is flush with the second side of the two adjacent chips 2 along the second direction Y, so as to isolate the two adjacent chips 2 in each row of chips 2. In this embodiment, the isolation groove is etched in the conductive layer 11, and the isolation groove increases the thermal resistance between the adjacent chips 2 along the first direction X, so as to reduce the transfer of heat in the first direction X, reduce the heat conduction and thermal coupling effect between the adjacent chips 2 along the first direction X, improve the uniformity of the temperature distribution of each chip 2, improve the heat dissipation efficiency and thermal management efficiency of the power module, so as to improve the reliability and life of the power module, and at the same time reduce the burden of the external heat dissipation system.

[0041] In some embodiments, the isolation structure 3 is located in the middle between two adjacent chips 2. The isolation structure 3 is spaced apart from the two adjacent chips 2 in the first direction X, and the isolation structure 3 is located in the middle of the two adjacent chips 2 in the first direction X (that is, the distance between the isolation structure 3 and the two adjacent chips 2 in the first direction X is equal). The isolation structure 3 extends along the second direction Y. The first side of the isolation structure 3 along the second direction may be flush with the first side of the two adjacent chips 2 along the second direction, or the first side of the isolation structure 3 along the second direction may exceed the first side of the two adjacent chips 2 along the second direction. The second side of the isolation structure 3 along the second direction may be flush with the second side of the two adjacent chips 2 along the second direction, or the second side of the isolation structure 3 along the second direction may exceed the second side of the two adjacent chips 2 along the second direction. The distance that the first side of the isolation structure 3 along the second direction exceeds the first side of the two adjacent chips 2 along the second direction may be equal to the distance that the second side of the isolation structure 3 along the second direction exceeds the second side of the two adjacent chips 2 along the second direction.

[0042] In this embodiment, the isolation structure 3 is located in the middle between two adjacent chips 2, which can further reduce the heat conduction and thermal coupling effects of the power module.

[0043] In some embodiments, the length of the isolation structure 3 along the second direction Y is greater than or equal to L and less than or equal to 6 / 5*L, where L is the length of the chip 2 along the second direction Y.

[0044] When the length of the isolation structure 3 along the second direction Y is L (i.e., the length of the isolation structure 3 along the second direction Y is equal to the length of the chip 2 along the second direction Y), the first side of the isolation structure 3 along the second direction may be flush with the first sides of the two adjacent chips 2 along the second direction, and the second side of the isolation structure 3 along the second direction may be flush with the second sides of the two adjacent chips 2 along the second direction. When the length of the isolation structure 3 along the second direction Y is greater than L and less than or equal to 6 / 5*L (i.e., the length of the isolation structure 3 along the second direction Y is greater than the length of the chip 2 along the second direction Y), the first side of the isolation structure 3 along the second direction may exceed the first side of the two adjacent chips 2 along the second direction, and / or, the second side of the isolation structure 3 along the second direction may exceed the second side of the two adjacent chips 2 along the second direction, and the sum of the distances by which the two sides of the isolation structure 3 along the second direction exceed the two sides of the two adjacent chips 2 along the second direction is less than or equal to 1 / 5L.

[0045] In some embodiments, the width of the isolation structure 3 along the first direction X is 0.5-0.6 mm. The width of the isolation structure 3 along the first direction X can be much smaller than the distance between two adjacent chips 2 along the first direction X, so that the isolation structure 3 is spaced apart from the two adjacent chips 2, avoiding that the two opposite sides of the isolation structure 3 along the first direction X contact the two opposite sides of the two adjacent chips 2 along the first direction X, so that the isolation structure 3 is electrically connected to the two adjacent chips 2, thereby avoiding affecting the electrical performance of the two adjacent chips 2.

[0046] For example, when the width of the chip 2 along the first direction X is 4 mm, the length along the second direction Y is 5 mm, and the distance between two adjacent chips 2 along the first direction X is 2 mm, the width of the isolation structure 3 along the first direction X may be 0.5 mm, and the length of the isolation structure 3 along the second direction Y may be 6 mm. The isolation structure 3 along the first direction X is located in the middle of the two adjacent chips 2 along the first direction X.

[0047] In some embodiments, the length of the isolation structure 3 along the second direction Y is positively correlated with the power level of the chip 2. The greater the power level of the chip 2 in the power module, the higher the heat generated, and the greater the length of the isolation structure 3 along the second direction Y, so as to improve the thermal resistance between two adjacent chips 2 along the first direction X, improve the isolation structure 3 for the heat transferred in the first direction X, reduce the heat conduction and thermal coupling effects between adjacent chips 2, improve the uniformity of the temperature distribution between adjacent chips 2, improve the heat dissipation efficiency of the power module, and thus improve the reliability and life of the power module.

[0048] For chips with higher power levels and higher heat generation, the related technology achieves thermal management of the power module by increasing the distance between chips or staggering the chips. This method fixes the layout of the chips, resulting in a lack of flexibility in the chip layout. In this embodiment, an isolation structure 3 is set between adjacent chips 2, and the length of the isolation structure 3 along the second direction Y is adjusted according to the power level and heat generation of the chip 2, so as to improve thermal management and optimize different application requirements. There is no need to increase the distance between multiple chips 2 or stagger the chips, so as to avoid limiting the layout of the chips 2 and improve the flexibility of the layout of the chips 2 in the power module and the thermal management effect.

[0049] In some embodiments, Figure 1 and Figure 3 As shown, the multiple chips 2 include multiple upper bridge chips 2a arranged in parallel and multiple lower bridge chips 2b arranged in parallel. The multiple upper bridge chips 2a are arranged side by side along a first direction X, and an isolation structure 3 is provided between adjacent upper bridge chips 2a. The multiple lower bridge chips 2b are arranged side by side along the first direction X, and an isolation structure 3 is provided between adjacent lower bridge chips 2b.

[0050] The substrate 1 may include an upper bridge region and a lower bridge region. A plurality of upper bridge chips 2a are arranged in parallel in the upper bridge region of the conductive layer 11, and the plurality of upper bridge chips 2a in parallel are arranged side by side along the first direction X. At least one isolation structure 3 is provided in the upper bridge region. An isolation structure 3 is provided between any two adjacent upper bridge chips 2a, and the isolation structure 3 is spaced apart from the two adjacent upper bridge chips 2a along the first direction X. The isolation structure 3 can isolate the heat conduction between the adjacent upper bridge chips 2a and reduce the thermal coupling effect. A plurality of lower bridge chips 2b are arranged in parallel in the lower bridge region of the conductive layer 11, and the plurality of lower bridge chips 2b in parallel are arranged side by side along the first direction X. At least one isolation structure 3 is provided in the lower bridge region. An isolation structure 3 is provided between any two adjacent lower bridge chips 2b, and the isolation structure 3 is spaced apart from the two adjacent lower bridge chips 2b along the first direction X. The isolation structure 3 can isolate the heat conduction between the adjacent lower bridge chips 2b in the first direction X and reduce the thermal coupling effect.

[0051] The number of upper bridge chips 2a is equal to the number of lower bridge chips 2b, and the plurality of upper bridge chips 2a and the plurality of lower bridge chips 2b are symmetrically arranged on the conductive layer 11 to achieve uniformity of current and voltage in the upper bridge region and the lower bridge region of the power module. For example, the upper bridge region of the power module is provided with 5 upper bridge chips 2a and 4 isolation structures 3, and the lower bridge region is provided with 5 lower bridge chips 2b and 4 isolation structures 3, and the 5 upper bridge chips 2a and the 5 lower bridge chips 2b are symmetrically arranged.

[0052] In this embodiment, the power module is a half-bridge power module. A half-bridge power module is a power electronic component consisting of two switching elements and a drive and protection circuit, and is mainly used to regulate current and voltage to control applications such as motor drive and power conversion. The topological structure of the power module is a half-bridge structure, which can simplify the design of the power module and enhance the stability of the power module.

[0053] In some embodiments, Figure 1 , Figure 3 and Figure 4 As shown, the power module may further include a signal pin 4 , a plurality of bonding wires 5 , an AC terminal 6 , a plurality of gate resistors 7 , a DC positive terminal 8 , a DC negative terminal 9 and a groove 10 .

[0054] The substrate 1 may further include a positive electrode region, a negative electrode region, an alternating current region, a first resistance region, and a second resistance region. The upper bridge region, the lower bridge region, the positive electrode region, the negative electrode region, the alternating current region, the first resistance region, and the second resistance region constitute different electrode regions, and the different electrode regions are isolated by the grooves 10, and the grooves 10 penetrate the conductive layer 11 along the thickness direction H.

[0055] The DC positive terminal 8 is connected to the positive region of the conductive layer 11. The positive region of the conductive layer 11 is connected to each upper bridge chip 2a through a bonding wire 5. The DC negative terminal 9 is connected to the negative region of the conductive layer 11. The negative region is connected to each lower bridge chip 2b through a bonding wire 5. Thus, a complete half-bridge structure is formed to achieve stable transmission of current and signals. The DC positive terminal 8 and the DC negative terminal 9 are used to realize the input and output of current in the power module. The bonding wire 5 is used to realize the electrical connection between different structures (such as the substrate 1 and the chip 2, etc.) in the power module, and also plays a role of mechanical fixation. The bonding wire 5 is a thin metal wire, and the material of the bonding wire 5 may include metals such as aluminum or copper. The number of bonding wires 5 can be determined according to the current level of the chip 2 in the power module in actual applications. For example, the higher the current level of the chip 2, the more bonding wires 5 can be. The length of the bonding wire 5 can be determined according to the layout mode and size of the chip 2 in the power module in actual applications.

[0056] The first resistance region of the conductive layer 11 is provided with a plurality of gate resistors 7, and the plurality of gate resistors 7 in the first resistance region are arranged at intervals along the first direction X, and are arranged in series with the plurality of upper bridge chips 2a in the upper bridge region in a one-to-one correspondence. The second resistance region of the conductive layer 11 is provided with a plurality of gate resistors 7, and the plurality of gate resistors 7 in the second resistance region are arranged at intervals along the first direction X, and are arranged in series with the plurality of lower bridge chips 2b in the lower bridge region in a one-to-one correspondence. For example, the upper bridge region is provided with 5 upper bridge chips 2a, the first resistance region is provided with 5 gate resistors 7 in series with the 5 upper bridge chips 2a in a one-to-one correspondence, the lower bridge region is provided with 5 lower bridge chips 2b, and the second resistance region is provided with 5 gate resistors 7 in series with the 5 lower bridge chips 2b in a one-to-one correspondence. The gate resistor 7 can limit the gate current and improve the reliability of the power module circuit. The AC terminal 6 is connected to the AC region of the conductive layer 11. The AC region is connected to each upper bridge chip 2a through a bonding wire 5. The AC terminal 6 is used to connect an AC power source. The AC region, the first resistance region, the second resistance region and the cathode region of the conductive layer 11 are respectively provided with signal pins 4. The gate and source signals of each chip 2 are collected at the signal pins 4, and the power module is connected to the external driving device through the signal pins 4 to realize the interconnection between the signal in the power module and the external driving signal.

[0057] In this embodiment, the current is input into the positive region of the power module from the DC positive terminal 8, flows into the upper bridge chip 2a in the upper bridge region through the bonding wire 5, then flows into the lower bridge chip 2b in the lower bridge region through the bonding wire 5, then flows into the negative region of the power module through the bonding wire 5, and then flows out of the power module to the external device through the AC terminal 6 or the DC negative terminal 9.

[0058] In some embodiments, chip 2 includes a silicon carbide device, a silicon device, or a gallium nitride device. Among them, the silicon carbide device may include a silicon carbide MOS tube (silicon carbide metal oxide semiconductor field effect tube) and the like. The silicon device may include an IGBT (Insulated Gate Bipolar Transistor, insulated gate bipolar transistor) and the like. Among them, the sizes of the silicon carbide device, the silicon device, and the gallium nitride device may be different. Chip 2 may select devices of different sizes or types according to actual application requirements.

[0059] Compared with IGBT, silicon carbide MOS tubes are smaller in size and have higher power density. When the substrate 1 has the same size, more chips 2 can be laid out in the power module by using silicon carbide MOS tubes. Silicon carbide materials have a wider bandgap, higher thermal conductivity, and higher breakdown electric field, so silicon carbide MOS tubes have stronger voltage resistance, and silicon carbide MOS tubes can work stably at higher temperatures. The use of silicon carbide MOS tubes can reduce the cooling requirements of the power module and the complexity of system design. Moreover, the on-resistance of silicon carbide MOS tubes is low, and silicon carbide MOS tubes can maintain a low loss state under high current conditions. Using silicon carbide MOS tubes under the same other conditions can make the power module have higher energy efficiency.

[0060] In some embodiments, Figure 2 As shown, the substrate 1 further includes a heat conducting layer 12 and a heat dissipation layer 13. The heat conducting layer 12 is located on the side of the conductive layer 11 away from the chip 2, and the heat dissipation layer 13 is located on the side of the heat conducting layer 12 away from the conductive layer 11, that is, the heat dissipation layer 13, the heat conducting layer 12 and the conductive layer 11 are stacked in sequence along the thickness direction H.

[0061] The material of the heat conducting layer 12 may be a ceramic material such as alumina. The heat conducting layer 12 has good thermal conductivity, can reduce the thermal stress generated between the chip 2 and the substrate 1, and improve the reliability of the power module. The material of the heat dissipation layer 13 may include metals such as copper. The heat dissipation layer 13 can be used as a heat dissipation channel to achieve heat conduction and heat dissipation in the substrate 1.

[0062] In some embodiments, the substrate 1 includes a DBC (Direct Bond Copper) substrate or an AMB (Active Metal Brazing) substrate.

[0063] In the case where the substrate 1 includes a DBC substrate, the conductive layer 11 and the heat dissipation layer 13 in the substrate 1 may be a copper layer, and the heat conductive layer 12 may be an alumina ceramic layer or an aluminum nitride ceramic layer. The process using the alumina ceramic layer is highly feasible and low in cost. Compared with the alumina ceramic layer, the aluminum nitride ceramic layer has higher thermal conductivity and heat dissipation performance. The DBC substrate is made by directly bonding the copper foil to the surface of the alumina or aluminum nitride ceramic substrate by hot melt bonding at high temperature, and the copper and ceramic layers can be directly bonded without additional materials. The DBC substrate has the advantages of good insulation performance, heat dissipation performance, mechanical properties, low thermal resistance coefficient and expansion coefficient matching. The DBC substrate can be widely used in the field of silicon device packaging such as IGBT.

[0064] In the case where the substrate 1 includes an AMB substrate, the conductive layer 11 and the heat dissipation layer 13 in the substrate 1 can be a copper layer, and the heat conductive layer 12 can be an aluminum oxide ceramic layer, an aluminum nitride ceramic layer or a silicon nitride ceramic layer. The thermal conductivity of the silicon nitride ceramic layer is high, and the thermal expansion coefficient is close to that of silicon, so that the AMB substrate is suitable for high-voltage, high-current semiconductor power modules. The AMB substrate is achieved by evenly coating the ceramic layer with active metal solder and performing vacuum brazing at high temperature to achieve the combination of the ceramic layer and copper. The active metal elements in the solder can include titanium, silver, zirconium or copper. Compared with the DBC substrate, the AMB substrate has higher bonding strength, high temperature resistance and reliability. Due to the use of active metal solder, the AMB substrate can achieve higher bonding strength and better heat dissipation performance.

[0065] In some embodiments, the power module further includes a heat sink, which is located on the side of the substrate 1 away from the chip 2. The material of the heat sink may include metals such as copper or aluminum. The heat sink has good thermal conductivity, which can further improve the heat dissipation performance of the power module and reduce the temperature of the chip 2. At the same time, it can provide physical support for other structures of the power module and enhance the structural stability of the power module.

[0066] In summary, according to the power module provided by the embodiment of the present application, a plurality of chips 2 are arranged side by side along the first direction X on the conductive layer 11 of the substrate 1, and an isolation structure 3 is arranged between the adjacent chips 2 along the first direction X, and the isolation structure 3 penetrates the conductive layer 11 and extends along the second direction Y, without increasing the spacing between the chips 2, and without dislocating the chips 2, so as to improve the thermal resistance between adjacent chips 2 without increasing the volume of the power module, reduce the transfer of heat in the first direction X, reduce the heat conduction and thermal coupling effects between adjacent chips 2, improve the uniformity of the temperature distribution between adjacent chips 2, improve the heat dissipation efficiency of the power module, reduce the risk of local overheating and material stress failure of the power module, thereby improving the reliability and life of the power module, and reducing the burden on the external heat dissipation system. At the same time, an isolation structure 3 is arranged in the power module to balance the electrical insulation performance and thermal management efficiency of the power module to maintain the structural integrity and electrical performance of the substrate 1. The power module can be a half-bridge power module, which simplifies the design of the power module and enhances the stability of the power module.

[0067] The terms "first", "second", etc. in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more.

[0068] In the description of the present application, “plurality” means two or more.

[0069] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0070] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A power module, characterized in that: include: a substrate including a conductive layer; A plurality of chips are connected to the conductive layer, and the plurality of chips are arranged side by side along a first direction; The isolation structure penetrates the conductive layer and extends along a second direction. The isolation structure is provided between the chips adjacent to each other along the first direction. The second direction is perpendicular to the first direction.

2. The power module according to claim 1, characterized in that: The isolation structure includes an isolation trench.

3. The power module according to claim 1, characterized in that: The isolation structure is located in the middle between the two adjacent chips.

4. The power module according to claim 1, characterized in that: The length of the isolation structure along the second direction is greater than or equal to L and less than or equal to 6 / 5*L, where L is the length of the chip along the second direction.

5. The power module according to claim 1, characterized in that: The width of the isolation structure along the first direction is 0.5-0.6 mm.

6. The power module according to claim 1, characterized in that: The length of the isolation structure along the second direction is positively correlated with the power level of the chip.

7. The power module according to claim 1, characterized in that: The plurality of chips include a plurality of upper bridge chips arranged in parallel and a plurality of lower bridge chips arranged in parallel; The plurality of upper bridge chips are arranged side by side along the first direction, and the isolation structure is provided between adjacent upper bridge chips; The plurality of lower bridge chips are arranged side by side along the first direction, and the isolation structure is provided between adjacent lower bridge chips.

8. The power module according to claim 1, characterized in that: The chip includes a silicon carbide device, a silicon device or a gallium nitride device.

9. The power module according to claim 1, characterized in that: The substrate also includes a heat-conducting layer and a heat-dissipating layer; The heat-conducting layer is located on a side of the conductive layer away from the chip, and the heat-dissipating layer is located on a side of the heat-conducting layer away from the conductive layer.

10. The power module according to any one of claims 1 to 9, characterized in that: The substrate includes a DBC substrate or an AMB substrate.

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