Chip and manufacturing method thereof, multi-chip stacked packaging structure and electronic equipment

Abstract

The invention provides a chip and a manufacturing method thereof, a multi-chip stacked packaging structure and electronic equipment, relates to the technical field of semiconductors, and can reduce damage to a low-k dielectric layer when a TSV penetrating through the low-k dielectric layer is manufactured. The chip can comprise a semiconductor substrate, a low-k dielectric layer, a through silicon via (TSV) and a first side wall protection structure. The low-k dielectric layer is arranged on the semiconductor substrate. The TSV penetrates through the semiconductor substrate and the low-k dielectric layer. The first side wall protection structure is arranged between the TSV and the low-k dielectric layer; wherein the first side wall protection layer comprises a first dielectric layer and a first metal layer, and the first dielectric layer is close to the low-k dielectric layer relative to the first metal layer. Through the first side wall protection structure, the low-k dielectric layer can be protected, and a low-k material of a hole wall is prevented from being damaged by oxidizing gas and hydrofluoric acid (HF) adopted in an etching process.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a chip and a manufacturing method thereof, a multi-chip stacking packaging structure, and an electronic device. Background Art

[0002] Through silicon via (TSV) technology refers to the technology of drilling holes on wafers and filling the holes with conductive materials to achieve interconnection between chips and between chips and external devices. It is considered to be one of the most advanced technologies in the semiconductor industry. Through silicon via technology has the advantages of short interconnection distance and high integration. It can increase the stacking density of chips in three-dimensional space, improve chip performance, reduce power consumption and reduce size.

[0003] In multi-layer stacked chip packaging, advanced process chips usually need to use low dielectric constant dielectric layers (also known as low-k dielectric layers) to ensure smaller RC (resistance and capacitance) delays. However, when making TSVs that pass through low-k dielectric layers, the oxidizing gases and hydrofluoric acid (HF) used in the etching process will damage the low-k materials, thereby affecting the reliability of the chip. Summary of the invention

[0004] The present application provides a chip and a manufacturing method thereof, a multi-chip stacking packaging structure, and an electronic device, which can reduce damage to a low-k dielectric layer when manufacturing a TSV (through silicon via) passing through the low-k dielectric layer (low dielectric constant dielectric layer).

[0005] The present application provides a chip, which may include: a semiconductor substrate, a low-k dielectric layer, a TSV, and a first sidewall protection structure. The low-k dielectric layer is arranged on the semiconductor substrate. The TSV runs through the semiconductor substrate and the low-k dielectric layer. The first sidewall protection structure is arranged between the TSV and the low-k dielectric layer. The first sidewall protection layer includes a first dielectric layer and a first metal layer, and the first dielectric layer is close to the low-k dielectric layer relative to the first metal layer.

[0006] By setting a first sidewall protection structure between the low-k dielectric layer and the TSV, the first sidewall protection structure can protect the hole wall of the low-k dielectric layer. In this way, when the hole depth is further increased by the subsequent etching process, the first sidewall protection structure can protect the previously formed hole wall and block the oxidizing gas and hydrofluoric acid (HF) used in the subsequent etching process from damaging the low-k material previously formed on the hole wall, thereby reducing the risk of damage to the low-k material and improving the reliability of the chip.

[0007] In some possible implementations, a through hole in the low-k dielectric layer having a TSV is a first through hole. The first through hole includes multiple side walls; wherein, in any two adjacent side walls, the side wall away from the bottom of the hole forms a first aperture, and the side wall close to the bottom of the hole forms a second aperture, and the first aperture is larger than the second aperture. The first side wall protection layer covers the surface of the first side wall; wherein the first side wall is the top side wall of the multiple side walls. In other words, the first through hole is manufactured and protected in sections, and the first side wall protection layer covers the side wall (first side wall) in the top area, so that the depth of the hole is increased by etching later, and the side wall in the top area can be protected.

[0008] In some possible implementations, the chip further includes a second sidewall protection structure; the second sidewall protection structure covers the second sidewall; the second sidewall is adjacent to the first sidewall. The second sidewall protection structure includes a second dielectric layer and a second metal layer, and the second dielectric layer is closer to the low-k dielectric layer than the second metal layer.

[0009] In some possible implementations, the second sidewall protection structure is located on a side of the first sidewall protection structure away from the low-k dielectric layer, and the second sidewall protection structure covers a side surface of the first sidewall protection structure.

[0010] In some possible implementations, the chip further includes a third sidewall protection structure; the third sidewall protection structure includes a third dielectric layer and a third metal layer, and the third dielectric layer is closer to the low-k dielectric layer than the third metal layer. The third sidewall protection structure covers a surface of the third sidewall; wherein the third sidewall is located on a side of the second sidewall away from the first sidewall.

[0011] In some possible implementations, the third sidewall protection structure is located on a side of the second sidewall protection structure away from the low-k dielectric layer, and the third sidewall protection structure covers a side surface of the second sidewall protection structure.

[0012] In some possible implementations, the third side wall is the bottommost side wall among the multiple sections of side walls.

[0013] In some possible implementations, the low-k dielectric layer includes one or more dielectric materials having a dielectric constant less than 4.2, such as hydrogen silsesquioxane (HSQ) and SiOCH.

[0014] In some possible implementations, the first dielectric layer includes one or more dielectric materials such as SiO2, SiN, and SiON.

[0015] In some possible implementations, the first metal layer includes one or more conductive materials such as TiN, AlN, and TaN.

[0016] The present application also provides a method for manufacturing a chip, the manufacturing method comprising: manufacturing a semiconductor substrate, and manufacturing a low-k dielectric layer on the semiconductor substrate. Forming a first through hole and a first sidewall protection structure in the low-k dielectric layer; wherein the first sidewall protection structure covers at least a portion of the sidewall of the first through hole, the first sidewall protection structure comprises a first dielectric layer and a first metal layer, and the first dielectric layer is closer to the low-k dielectric layer than the first metal layer. Forming a silicon through hole penetrating the low-k dielectric layer and the semiconductor substrate on the inner side of the first sidewall protection structure.

[0017] By adopting the manufacturing method of the present application, a first sidewall protection structure is manufactured through the sidewall of the first through hole, and the first sidewall protection structure can protect the hole wall of the low-k dielectric layer. In this way, when the hole depth is further increased by the subsequent etching process, the first sidewall protection structure can protect the hole wall covered by it, and block the oxidizing gas and hydrofluoric acid (HF) used in the subsequent etching process from damaging the low-k material of the hole wall, thereby reducing the risk of damage to the low-k material, thereby improving the reliability of the chip.

[0018] In some possible implementations, the forming of the first through hole and the first sidewall protection structure in the low-k dielectric layer includes: forming a first groove in the low-k dielectric layer, and forming a first sidewall protection structure on a sidewall of the first groove.

[0019] In some possible implementations, after forming a first groove in the low-k dielectric layer and forming a first sidewall protection structure on the sidewall of the first groove, the method further includes: extending the bottom of the first groove downward along the inner side of the first sidewall protection structure to form a second groove, and forming a second sidewall protection structure on the side of the first sidewall protection structure and the sidewall of the second groove; wherein the second sidewall protection structure includes a second dielectric layer and a second metal layer, and the second dielectric layer is close to the low-k dielectric layer relative to the second metal layer.

[0020] In this case, when the bottom of the first trench is extended downward along the inner side of the first sidewall protection structure to form the second trench, the first sidewall protection structure can protect the first sidewall and prevent the etching process from damaging the first sidewall.

[0021] In some possible implementations, after the second sidewall protection structure is formed on the side of the first sidewall protection structure and the sidewall of the second trench, the method further includes: penetrating the bottom of the second trench downward through the low-k dielectric layer along the inner side of the second sidewall protection structure to form a third trench; and forming a third sidewall protection structure on the side of the second sidewall protection structure and the sidewall of the third trench; wherein the third sidewall protection structure includes a third dielectric layer and a third metal layer, and the third dielectric layer is closer to the low-k dielectric layer relative to the third metal layer.

[0022] In this case, when the bottom of the second groove is extended downward along the inner side of the second sidewall protection structure to form a third groove, the first sidewall protection structure can protect the first sidewall, and the second sidewall protection structure can protect the second sidewall, thereby avoiding damage to the first sidewall and the second sidewall during the etching process.

[0023] The present application also provides a multi-chip stacked packaging structure, which includes a first chip and a second chip stacked in a stacked arrangement, wherein the first chip is a chip provided in any of the aforementioned possible implementation methods, and the first chip is electrically connected to the second chip through a through silicon via.

[0024] The present application also provides an electronic device, a circuit board, and a chip provided in any possible implementation method as described above, wherein the chip is electrically connected to the circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic plan view of a chip at a TSV position provided in an embodiment of the present application;

[0026] Figure 2 for Figure 1 Schematic diagram of the cross section at the O1-O2 position;

[0027] Figure 3 for Figure 2 Schematic diagram of semiconductor substrate and low-k dielectric layer;

[0028] Figure 4 A schematic diagram of the structure of a chip at a TSV position provided in an embodiment of the present application;

[0029] Figure 5 A schematic diagram of the structure of a chip at a TSV position provided in an embodiment of the present application;

[0030] Figure 6 A schematic diagram of the structure of a chip at a TSV position provided in an embodiment of the present application;

[0031] Figure 7 A flow chart of a chip manufacturing method provided in an embodiment of the present application;

[0032] Figure 8 A schematic diagram of a chip in the manufacturing process provided in an embodiment of the present application;

[0033] Fig. 9 A schematic diagram of a chip in the manufacturing process provided in an embodiment of the present application;

[0034] Fig.10 A schematic diagram of a chip in the manufacturing process provided in an embodiment of the present application;

[0035] Fig.11 A schematic diagram of a chip in the manufacturing process provided in an embodiment of the present application;

[0036] Fig.12 A schematic diagram of a chip during the manufacturing process provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0038] The terms "first", "second", etc. in the specification embodiments, claims and drawings of the present application are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one (item)" means one or more, and "multiple" means two or more. "Installation", "connection", "connected", etc. should be understood in a broad sense, for example, it can be an electrical connection or a mechanical connection; it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or it can be indirect through an intermediate medium, or it can be the internal connection of two elements. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, including a series of steps or units. Methods, systems, products or devices are not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or inherent to these processes, methods, products or devices. "Up", "down", "left", "right", etc. are only used relative to the orientation of the components in the drawings. These directional terms are relative concepts. They are used for description and clarification relative to the description, which may change accordingly according to the change of the orientation of the components in the drawings.

[0039] An embodiment of the present application provides an electronic device, which may be a terminal device, such as a mobile phone, a tablet computer, a smart bracelet, or a personal computer (PC), a server, a workstation, etc. The present application does not limit the setting form of the electronic device.

[0040] The electronic device provided in the embodiment of the present application includes a printed circuit board (PCB; also called a printed circuit board) and a multi-chip stacking packaging structure electrically connected to the circuit board. The stacking packaging structure can be applied to networks, AI (artificial intelligence), HPC (high performance computing), cloud and other devices with large capacity and high bandwidth requirements. The present application does not limit the application scenarios of the stacking packaging structure.

[0041] The multi-chip stacked packaging structure provided in an embodiment of the present application includes a plurality of stacked chips; wherein at least one chip is provided with a low-k dielectric layer and a through silicon via (TSV) penetrating the low-k dielectric layer, and the chip is electrically connected to other stacked chips through the through silicon via (TSV).

[0042] In the prior art, when making TSV, it is necessary to first make a through hole in the low-k dielectric layer. When making the through hole, the oxidizing gas and hydrofluoric acid (HF) used in the etching process will damage the low-k material on the side wall of the through hole, thereby affecting the reliability of the chip.

[0043] Based on this, an embodiment of the present application provides a chip, in which, during the process of making a through hole in a low-k dielectric layer, a sidewall protection structure is covered on the hole wall; that is, before penetrating the low-k dielectric layer, the sidewall protection structure is covered on the sidewall of the blind hole. In this way, when the depth of the hole is further increased through a subsequent etching process, the sidewall protection structure can protect the previously formed hole wall, and block the oxidizing gas and hydrofluoric acid (HF) used in the etching process from causing damage to the low-k material previously forming the hole wall, thereby reducing the risk of damage to the low-k material, thereby improving the reliability of the chip.

[0044] The specific configuration of the sidewall protection structure is described below in conjunction with a through silicon via (TSV) in a chip.

[0045] Figure 1 A schematic plan view of a chip at a TSV position provided in an embodiment of the present application, Figure 2 for Figure 1 Schematic diagram of the cross section at the O1-O2 position.

[0046] In an illustrative embodiment, the present application provides a chip, combined with Figure 1 and Figure 2 As shown, the chip includes a semiconductor substrate 1 and a low-k dielectric layer 2 arranged on the semiconductor substrate 1 .

[0047] The above-mentioned low-k dielectric layer 2 includes a low dielectric constant material (i.e., a low-k material), and the dielectric constant of the low-k material may be less than 4.2. The present application does not limit the low-k material used in the low-k dielectric layer 2, and it can be selected and set as needed in practice. In some possible implementations, one or more low-k materials such as hydrogenated silsesquioxane HSQ, SiOCH, etc. may be used in the low-k dielectric layer 2. For example, the low-k dielectric layer 2 may be a porous SiOCH film layer.

[0048] In addition, the low-k dielectric layer 2 can be a single film layer or multiple film layers. Of course, the low-k dielectric layer 2 can also include film layers of other non-low-k materials, and this application does not limit this. In practice, the low-k dielectric layer 2 can be set according to the application scenario of the chip.

[0049] The semiconductor substrate 1 may include a silicon (Si) wafer and a device layer and a metal wiring layer arranged on the surface of the silicon (Si) wafer. The device layer may include devices such as field effect transistors, capacitors, resistors, etc., which are not limited in this application.

[0050] On this basis, if Figure 1 and Figure 2 As shown, the chip also includes a through silicon via (TSV) penetrating the semiconductor substrate 1 and the low-k dielectric layer 2. It can also be said that the chip is provided with a through hole penetrating the semiconductor substrate 1 and the low-k dielectric layer 2, and the TSV is arranged in the through hole. Among them, the TSV may include a filling metal and a seed layer and a barrier layer located outside the filling metal, and the specific arrangement of the TSV is not limited in this application.

[0051] Figure 3 for Figure 2 Schematic diagram of a semiconductor substrate 1 and a low-k dielectric layer 2.

[0052] refer to Figure 3 As shown, in order to more clearly illustrate the improvements of the present application below, the through hole portion where the TSV is set in the low-k dielectric layer 2 is defined as a first through hole V1.

[0053] Combination Figure 2 and Figure 3 As shown, in the chip provided in the embodiment of the present application, by setting the first sidewall protection structure 11 on at least part of the sidewall of the first through hole V1, that is, setting the first sidewall protection structure 11 on at least part of the area between the TSV and the low-k dielectric layer 2, the first sidewall protection structure 11 can protect the sidewall of the first through hole V1. In this way, when the depth of the hole is increased by the etching process, the first sidewall protection structure 11 can prevent the oxidizing gas and hydrofluoric acid (HF) used in the etching process from damaging the low-k material of the hole wall, thereby reducing the risk of the low-k material of the hole wall being damaged, thereby improving the reliability of the chip.

[0054] The specific structure of the first side wall protection structure 11 can be set as required, as long as it can meet the above-mentioned relevant requirements.

[0055] Indicative, such as Figure 2As shown, in some possible implementations, the first sidewall protection structure 11 may include a first dielectric layer a1 and a first metal layer b1 that are stacked, and the first dielectric layer a1 is closer to the low-k dielectric layer 2 than the first metal layer b1. The first dielectric layer a1 can play a certain bonding role on the first metal layer b1, ensuring better bonding between the first metal layer b1 and the low-k material of the sidewall; at the same time, the first dielectric layer a1 also plays a certain isolation and blocking role, preventing the metal in the first metal layer b1 from diffusing into the low-k dielectric layer 2. The first metal layer b1 reacts very slowly or almost not at all with the oxidizing gas and hydrofluoric acid (HF) used in the etching process, so that it can play a protective role on the hole wall.

[0056] The present application does not limit the dielectric material forming the first dielectric layer a1, and it can be set as needed in practice. In some possible implementations, the first dielectric layer a1 can be made of one or more dielectric materials such as SiO2, SiN, and SiON.

[0057] The present application does not limit the dielectric material forming the first metal layer b1, and it can be set as needed in practice. In some possible implementations, the first metal layer b1 can be made of one or more materials such as TiN, AlN, and TaN.

[0058] In addition, the present application does not impose any restrictions on the shape, size, etc. of the first side wall protection structure 11, and it can be set as needed in practice.

[0059] In some possible implementations, reference is made to Figure 1 and Figure 2 As shown, the first sidewall protection structure 11 may be a hollow cylindrical structure arranged around the TSV. In this case, the first dielectric layer a1 and the first metal layer b1 may be two stacked hollow cylinders, the first metal layer b1 is located inside the first dielectric layer a1, and the TSV is located inside the first metal layer b1.

[0060] In addition, considering the actual manufacturing process, in order to better protect the side wall of the first through hole V1, in some possible implementation methods, the first through hole V1 can be manufactured in sections through multiple etching processes, and the side wall sections can be covered by different side wall protection structures to protect the sectioned side wall of the first through hole V1.

[0061] Indicative, such as Figure 3 As shown, in some possible implementations, the sidewall of the first through hole V1 can be divided into three sections from top to bottom: a first sidewall S1, a second sidewall S2, and a third sidewall S3. The first sidewall S1 is located in the top area, the third sidewall S3 is located in the bottom area, and the second sidewall S2 is located in the middle area. In this case, combined with Figure 2 As shown, a first sidewall protection structure 11, a second sidewall protection structure 12, and a third sidewall protection structure 13 can be respectively provided to protect the three sidewalls (S1, S2, S3). The first sidewall protection structure 11 can cover the surface of the first sidewall S1, the second sidewall protection structure 12 can cover the surface of the second sidewall S2, and the third sidewall protection structure 13 can cover the surface of the third sidewall S3.

[0062] The second sidewall protection structure 12 includes a second dielectric layer a2 and a second metal layer b2 stacked together, and the second dielectric layer a2 is closer to the low-k dielectric layer 2 than the second metal layer b2. The third sidewall protection structure 13 includes a third dielectric layer a3 and a third metal layer b3 stacked together, and the third dielectric layer a3 is closer to the low-k dielectric layer 2 than the third metal layer b3.

[0063] The relevant settings (such as materials, shapes, etc.) of the second dielectric layer a2 and the third dielectric layer a3 are similar to those of the first dielectric layer a1, and the relevant description of the first dielectric layer a1 can be referred to for details. For example, in some possible implementations, the materials of the second dielectric layer a2 and the third dielectric layer a3 can be the same as those of the first dielectric layer a1, and the second dielectric layer a2 and the third dielectric layer a3 can be hollow cylindrical structures.

[0064] Similarly, the second metal layer b2 and the third metal layer b3 are similar to those of the first metal layer b1 in terms of their materials, shapes, etc. For details, please refer to the above description of the first metal layer b1. For example, in some possible implementations, the materials of the second metal layer b2 and the third metal layer b3 may be the same as those of the first metal layer b1, and the second metal layer b2 and the third metal layer b3 may be hollow cylindrical structures.

[0065] In the actual manufacturing process, the first side wall S1 is first formed by an etching process, and a first side wall protection structure 11 is formed on the surface of the first side wall S1. Next, the second side wall S2 is formed by an etching process, and a second side wall protection structure 12 is formed on the surface of the second side wall S2. Next, the third side wall S3 is formed by an etching process, and a third side wall protection structure 13 is formed on the surface of the third side wall S3. For details, please refer to the manufacturing method section below.

[0066] It can be understood that when the second sidewall S2 is formed by etching, the first sidewall protection structure 11 can protect the first sidewall S1. When the third sidewall S3 is formed by etching, the first sidewall protection structure 11 can protect the first sidewall S1, and the second sidewall S2 can protect the second sidewall protection structure 12, thereby avoiding the oxidizing gas and hydrofluoric acid (HF) used in the subsequent etching process from damaging the low-k material of the hole wall.

[0067] It can be understood that the purpose of setting the second side wall protection structure 12 is mainly to protect the second side wall S2. Figure 2 As shown, the second sidewall protection structure 12 can extend from the top of the first through hole V1 to cover the second sidewall S2. In other words, the second sidewall protection structure 12 is located on the side of the first sidewall protection structure 11 away from the low-k dielectric layer 2, and the second sidewall protection structure 12 covers the second sidewall S2 and the side of the first sidewall protection structure 11 at the same time. For details, please refer to the manufacturing method section below.

[0068] Similarly, in order to simplify the production process and reduce production costs, refer to Figure 2 As shown, the third sidewall protection structure 13 can extend from the top of the first through hole V1 to cover the third sidewall S3. In other words, the third sidewall protection structure 13 is located on the side of the second sidewall protection structure 12 away from the low-k dielectric layer 2, and the third sidewall protection structure 13 covers the second sidewall S2 and the side of the second sidewall protection structure 12 at the same time. For details, please refer to the manufacturing method section below.

[0069] In addition, since the second side wall S2 is formed after the first side wall protection structure 11 is formed, the second side wall S2 is nearly flush with the inner side wall of the first side wall protection structure 11. Figure 3 As shown, the side wall of the first through hole V1 will form a step structure at the connection between the first side wall S1 and the second side wall S2, and the aperture d1 formed by the first side wall S1 will be larger than the aperture d1 formed by the second side wall S2, that is, the second side wall S2 is closer to the center position of the first through hole V1 relative to the first side wall S1.

[0070] Similarly, refer to Figure 3 As shown, the side wall of the first through hole V1 also forms a step structure at the connection between the second side wall S2 and the third side wall S3. The aperture formed by the second side wall S2 is larger than the aperture formed by the third side wall S3. The third side wall S3 is closer to the center of the first through hole V1 than the second side wall S2.

[0071] Figure 2 and Figure 3 The side wall of the first through hole V1 is merely divided into three sections, and each section of the side wall is covered with a side wall protection structure for schematic illustration, but the present application is not limited thereto.

[0072] For example, in some possible implementations, Figure 4 or Figure 5 As shown, the sidewall protection structure may be covered only on part of the sidewall of the first through hole V1. Figure 4The side wall of the first through hole V1 can be divided into three sections (S1, S2, S3), and the side wall protection structure can be covered only on the surface of the first side wall S1 and the second side wall S2; Figure 5 The side wall of the first through hole V1 may be divided into two sections (S1, S2), and the side wall protection structure may be covered only on the surface of the first side wall S1.

[0073] For another example, in some possible implementations, the side wall of the first through hole V1 is divided into four sections, five sections, etc.

[0074] In addition, the TSV in the above embodiments is described by taking the via middle as an example, but the present application is not limited thereto, and in other possible implementations, the TSV may also adopt via first and via last. Of course, according to the arrangement of the TSV, the arrangement of the sidewall protection structures (11, 12, 13) may be adjusted accordingly.

[0075] For example, when TSV adopts via first and via middle, the first via V1 and the sidewall protection structure (11, 12, 13) are arranged similarly, see Figure 2 As shown, a first through hole V1 is made from the front side of the chip to penetrate the low-k dielectric layer 2 and then penetrate the semiconductor substrate 1. The first through hole V1 is made by etching from the upper surface of the low-k dielectric layer 2 (the surface away from the semiconductor substrate 1) to the side close to the semiconductor substrate 1 in multiple sections, and correspondingly, multiple sidewall protection structures (11, 12, 13) are deposited from the upper surface side of the low-k dielectric layer 2.

[0076] For example, Figure 6 As shown, in the case where TSV adopts via last, the semiconductor substrate 1 is penetrated from the back of the chip, and then the first through hole V1 is made to penetrate the low-k dielectric layer 2. The first through hole V1 is made by etching from the lower surface of the low-k dielectric layer 2 (the surface close to the semiconductor substrate 1) to the side away from the semiconductor substrate 1 in multiple sections. In this case, multiple sidewall protection structures (11, 12, 13) can extend from the back of the semiconductor substrate 1 (i.e., the surface away from the low-k dielectric layer 2) to the side of the low-k dielectric layer 2, the top of the first through hole V1 is located on the side close to the semiconductor substrate 1, and the bottom of the first through hole V1 is located on the side away from the semiconductor substrate 1. The sidewall protection structure (11, 12, 13) can cover the hole wall portion in the semiconductor substrate 1. Of course, according to actual needs, in other possible implementation methods, the sidewall protection structure (11, 12, 13) located in the semiconductor substrate 1 can also be removed, and this application does not limit this.

[0077] In the present application, since the sidewall protection structure (11, 12, 13) is used to protect the sidewall of the first through hole V1, the risk of damage to the low-k material around the TSV can be reduced, thereby reducing the keep out zone (KOZ) around the TSV, increasing the design flexibility of the area outside the TSV and reducing the area of ​​the TSV area. At the same time, based on the setting of the sidewall protection structure (11, 12, 13), the present application can also ensure that the critical dimension CD (critical dimension) and the aspect ratio of the TSV remain unchanged, thereby ensuring the continuity of subsequent processes.

[0078] The sidewall protection structure is further described below in conjunction with a chip manufacturing method.

[0079] Schematically, the present application embodiment provides a method for manufacturing a chip, such as Figure 7 As shown, the production method may include:

[0080] Step 11. Reference Figure 8 As shown, a semiconductor substrate 1 is manufactured, and a low-k dielectric layer 2 is manufactured on the semiconductor substrate 1 .

[0081] In some possible implementations, reference is made to Figure 8 As shown, the above step 11 may include: providing a Si wafer, and manufacturing devices such as field effect transistors on the Si wafer to form a semiconductor substrate 1. Then, a low-k dielectric layer 2 is deposited on the surface of the semiconductor substrate 1 using one or more low-k materials such as hydrogenated silsesquioxane HSQ and SiOCH.

[0082] Step 12: Reference Fig. 9 As shown, a first groove G1 is formed in the low-k dielectric layer 2, and a first sidewall protection structure 11 is formed on the sidewall of the first groove G2. The first sidewall protection structure 11 includes a first dielectric layer a1 and a first metal layer b1, and the first dielectric layer a1 is closer to the low-k dielectric layer 2 than the first metal layer b1.

[0083] In some possible implementations, step 12 includes: referring to Fig. 9 As shown in (a), a dielectric layer ( Fig. 9(not shown), then apply photoresist PR (photo resist), and etch the upper surface of the low-k dielectric layer 2 through an etching process (dry etching or wet etching) to form a first trench G1. After the first trench G1 is etched, N2, H2 and other gases are used to remove the photoresist PR, and diluted HF is used to remove the residual polymer to ensure that the sidewall S1 of the first trench G1 is not damaged. Next, refer to Fig. 9 As shown in (b), a first dielectric layer a1 and a first metal layer b1 are sequentially deposited in the first trench G1. In this case, the first dielectric layer a1 and the first metal layer b1 covering the sidewall S1 of the first trench G1 form a first sidewall protection structure 11 to protect the sidewall S1.

[0084] It should be understood that the aperture of the first trench G1 formed in step 12 should be larger than the diameter of the TSV to be formed, so as to meet the requirements of the subsequent fabrication of the sidewall protection structure.

[0085] Step 13. Reference Fig.10 As shown, the bottom of the first trench G1 is extended downward along the inner side of the first sidewall protection structure 11 to form a second trench G2; and a second sidewall protection structure 12 is formed on the side of the first sidewall protection structure 11 and the sidewall of the second trench G2; wherein the second sidewall protection structure 12 includes a second dielectric layer a2 and a second metal layer b2, and the second dielectric layer a2 is close to the low-k dielectric layer 2 relative to the second metal layer b2.

[0086] In some possible implementations, step 13 may include: Fig.10 As shown in (a) and (b), a hard mask layer HM is formed on the surface of the first sidewall protection structure 11, and a thin photoresist layer PR (not shown in the figure) is covered on the hard mask layer HM. An etching process (dry etching or wet etching) is used to extend the bottom of the first trench G1 downward along the inner side of the first sidewall protection structure 11 to form a second trench G2. After the etching of the second trench G2 is completed, N2, H2 and other gases are used to remove the hard mask layer HM and the photoresist PR, and diluted HF is used to remove the residual polymer to ensure that the sidewall S2 of the second trench G2 is not damaged. Next, refer to Fig.10 As shown in (c), a second dielectric layer a2 and a second metal layer b2 are sequentially deposited in the second trench G2; in this case, the second dielectric layer a2 and the second metal layer b2 covering the sidewall S2 of the second trench G2 form a second sidewall protection structure 12 to protect the sidewall S2.

[0087] Step 14: Reference Fig.11As shown, the bottom of the second trench G2 is extended downward along the inner side of the second sidewall protection structure 12 to penetrate the low-k dielectric layer 2 to form a third trench G3; and a third sidewall protection structure 13 is formed on the side of the second sidewall protection structure 12 and the sidewall of the third trench G3; wherein the third sidewall protection structure 13 includes a third dielectric layer a3 and a third metal layer b3, and the third dielectric layer a3 is close to the low-k dielectric layer 2 relative to the third metal layer b3.

[0088] Step 14 is similar to step 13 above. In some possible implementations, reference is made to Fig.11 As shown, a hard mask layer can be first formed on the surface of the second sidewall protection structure 12 through step 14, and a thin photoresist layer can be covered on the hard mask layer. Then, the bottom of the second groove G2 is extended downward through the low-k dielectric layer 2 along the inner side of the second sidewall protection structure 12 through an etching process (dry etching or wet etching) to form a third groove G3. After the etching of the third groove G3 is completed, N2, H2 and other gases are used to remove the photoresist, and diluted HF is used to remove the residual polymer to ensure that the side wall S3 of the third groove G3 is not damaged. Next, the third dielectric layer a3 and the third metal layer b3 are deposited in the third groove G3 in sequence. In this case, the third dielectric layer a3 and the third metal layer b3 covering the side wall S3 of the third groove G3 form a third sidewall protection structure 13 to protect the side wall S3.

[0089] Step 15: Reference Fig.12 As shown, a TSV (Through Silicon Via) penetrating the low-k dielectric layer 2 and the semiconductor substrate 1 is formed inside the third sidewall protection structure 13 .

[0090] In some possible implementations, reference is made to Fig.11 and 12 As shown, the above step 15 may include: after completing the production of the third sidewall protection structure 13, etching downward from the inner side of the third sidewall protection structure 13 to form a through hole penetrating the low-k dielectric layer 2 and the semiconductor substrate 1, and making TSV in the through hole, and performing other subsequent processes according to actual needs, such as grinding process, etc.

[0091] It should be understood that in the embodiments of the present application, the size of the serial numbers of the above-mentioned production processes does not mean the order of execution. The execution order of each production process should be determined by the specific function and internal logic of the device, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0092] In addition, for other related contents in the above-mentioned production method, you can refer to the corresponding parts in the above-mentioned structural embodiment, and will not be repeated here; for other setting structures in the above-mentioned structural embodiment, you can refer to the above-mentioned production method and related production methods for adjustment, and will not be repeated here one by one.

[0093] For example, for Figure 4 , Figure 5 , Figure 6 The chip structure shown in the figure can refer to the description of the above steps 11 to 15, and the corresponding process adjustments can be made in combination with relevant technologies.

[0094] It should also be noted that the chip provided in the embodiment of the present application is not limited to the application in a multi-chip stacked packaging structure. The chip of the present application can be any chip that requires the setting of TSV to penetrate the low-k dielectric layer.

[0095] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A chip, characterized in that: include: Semiconductor substrate; A low dielectric constant dielectric layer, wherein the low dielectric constant dielectric layer is disposed on the semiconductor substrate; A through silicon via TSV, wherein the TSV penetrates the semiconductor substrate and the low dielectric constant dielectric layer; A first sidewall protection structure, wherein the first sidewall protection structure is disposed between the TSV and the low dielectric constant dielectric layer; The first sidewall protection layer includes a first dielectric layer and a first metal layer, and the first dielectric layer is closer to the low dielectric constant dielectric layer than the first metal layer.

2. The chip according to claim 1, characterized in that: The through hole in the low dielectric constant dielectric layer in which the TSV is arranged is a first through hole; The first through hole comprises a plurality of side walls; wherein, in any two adjacent side walls, the side wall away from the hole bottom forms a first aperture, the side wall close to the hole bottom forms a second aperture, and the first aperture is larger than the second aperture; The first sidewall protection layer covers the surface of the first sidewall; wherein the first sidewall is the topmost sidewall among the multiple sidewall sections.

3. The chip according to claim 2, characterized in that: The chip further includes a second sidewall protection structure; the second sidewall protection structure covers the second sidewall; the second sidewall and the first sidewall; The second sidewall protection junction includes a second dielectric layer and a second metal layer, and the second dielectric layer is closer to the low dielectric constant dielectric layer than the second metal layer.

4. The chip according to claim 3, characterized in that: The second sidewall protection structure is located on a side of the first sidewall protection structure away from the low dielectric constant dielectric layer, and the second sidewall protection structure covers a side surface of the first sidewall protection structure.

5. The chip according to claim 3, characterized in that: The chip further comprises a third sidewall protection structure; the third sidewall protection structure comprises a third dielectric layer and a third metal layer, and the third dielectric layer is closer to the low dielectric constant dielectric layer than the third metal layer; The third sidewall protection structure covers the surface of the third sidewall; wherein the third sidewall is located on a side of the second sidewall away from the first sidewall.

6. The chip according to claim 5, characterized in that: The third sidewall protection structure is located on a side of the second sidewall protection structure away from the low dielectric constant dielectric layer, and the third sidewall protection structure covers a side surface of the second sidewall protection structure.

7. The chip according to claim 5 or 6, characterized in that: The third side wall is the bottommost side wall among the multiple sections of side walls.

8. The chip according to any one of claims 1 to 7, characterized in that: The low dielectric constant dielectric layer includes at least one of hydrogenated silsesquioxane HSQ and SiOCH.

9. The chip according to any one of claims 1 to 8, characterized in that: The first dielectric layer includes one or more of SiO2, SiN, and SiON; The first metal layer includes one or more of TiN, AlN and TaN.

10. A method for manufacturing a chip, characterized in that: include: Manufacturing a semiconductor substrate, and manufacturing a low dielectric constant dielectric layer on the semiconductor substrate; A first through hole and a first sidewall protection structure are formed in the low-k dielectric layer; wherein the first sidewall protection structure covers at least a portion of the sidewall of the first through hole, the first sidewall protection structure comprises a first dielectric layer and a first metal layer, and the first dielectric layer is closer to the low-k dielectric layer than the first metal layer; A through silicon via is formed inside the first sidewall protection structure and penetrates the low dielectric constant dielectric layer and the semiconductor substrate.

11. The method for manufacturing a chip according to claim 10, characterized in that: The forming of a first through hole and a first sidewall protection structure in the low dielectric constant dielectric layer comprises: A first groove is formed in the low dielectric constant dielectric layer, and the first sidewall protection structure is formed on the sidewall of the first groove.

12. The method for manufacturing a chip according to claim 11, characterized in that: After forming a first groove in the low dielectric constant dielectric layer and forming the first sidewall protection structure on the sidewall of the first groove, the method further includes: The bottom of the first groove is extended downward along the inner side of the first sidewall protection structure to form a second groove, and a second sidewall protection structure is formed on the side of the first sidewall protection structure and the sidewall of the second groove; wherein the second sidewall protection structure includes a second dielectric layer and a second metal layer, and the second dielectric layer is close to the low dielectric constant dielectric layer relative to the second metal layer.

13. The method for manufacturing a chip according to claim 12, characterized in that: After forming the second sidewall protection structure on the side of the first sidewall protection structure and the sidewall of the second trench, the method further includes: The bottom of the second groove is downwardly penetrated through the low dielectric constant dielectric layer along the inner side of the second sidewall protection structure to form a third groove; and a third sidewall protection structure is formed on the side of the second sidewall protection structure and the sidewall of the third groove; wherein the third sidewall protection structure includes a third dielectric layer and a third metal layer, and the third dielectric layer is close to the low dielectric constant dielectric layer relative to the third metal layer.

14. A multi-chip stacking packaging structure, characterized in that: It comprises a first chip and a second chip which are stacked, wherein the first chip is the chip as claimed in any one of claims 1 to 9, and the first chip is electrically connected to the second chip through the through silicon via.

15. An electronic device, characterized in that: A circuit board and a chip as claimed in any one of claims 1 to 9, wherein the chip is electrically connected to the circuit board.

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