Capacitance test structure and method for obtaining capacitances of a multi-capacitance structure

Abstract

The application relates to a kind of capacitance test structure and the method for obtaining the capacitance of multiple capacitance structure.The capacitance test structure includes main test unit, first parasitic capacitance test unit and second parasitic capacitance test unit, wherein the parasitic capacitance produced by metal connection is same, the parasitic capacitance produced by metal pad is same, the capacitance test is carried out using the three test units respectively, and the corresponding test data can be obtained, and then according to the equation C11=C1-[C2-(C3-C2) / (n-1)], the capacitance of the multiple capacitance structure to be measured can be calculated, the influence of parasitic capacitance can be reduced, the capacitance accuracy of the multiple capacitance structure to be measured can be improved, in addition, the first quantity is greater than the sum of the second quantity and the third quantity, so that the area occupied by the parasitic capacitance test structure can be reduced, and the wafer test area can be saved.The method for obtaining the capacitance of multiple capacitance structure adopts the above-mentioned capacitance test structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a capacitance test structure and a method for obtaining capacitance of a multi-capacitor structure. Background Art

[0002] WAT (Wafer Acceptance Test) is a wafer acceptance test. After the wafer product is tape-out, WAT performs electrical testing on specific test structures (test keys) formed on the wafer to determine whether the wafer product meets the electrical specifications of the corresponding process technology platform and detect any process anomalies.

[0003] When performing WAT to test the capacitance of a capacitor structure formed on a wafer, since the metal wires connecting the capacitor structure, the metal pads connecting the metal wires, the probes contacting the metal pads, and the tester connected to the probes may all generate parasitic capacitance, the capacitance directly tested includes a parasitic capacitance portion. If this capacitance is directly used as the capacitance of the capacitor structure to be tested, the accuracy is poor.

[0004] In order to deduct the influence of parasitic capacitance and obtain a more accurate capacitance, in addition to the main test unit containing the capacitor structure to be tested and its connected metal wiring and test pads, a parasitic capacitance test unit can also be set in the wafer test area to test the parasitic capacitance. The structure and formation method of the parasitic capacitance test unit are basically the same as those of the main test unit. The difference is that the capacitor structure in the parasitic capacitance test unit is disconnected from the metal wiring, so that the capacitance test data tested is parasitic capacitance. In this way, the capacitance test data tested by the main test unit and the parasitic capacitance test unit are subtracted, and the difference is the capacitance of the capacitor structure to be tested. Since the influence of the parasitic capacitance is deducted, the capacitance of the capacitor structure to be tested is more accurate.

[0005] In some cases, the capacitor structure to be tested includes multiple capacitor devices arranged horizontally and electrically interconnected, which occupy a large area. If a parasitic capacitance test unit is set according to the structure of the main test unit, the parasitic capacitance test unit will also occupy a large area, which will squeeze the test area on the wafer and affect the layout of the test area. Summary of the Invention

[0006] In order to obtain the capacitance of a capacitor structure including multiple capacitor devices, while reducing the influence of parasitic capacitance to improve data accuracy and save the test area, the present invention provides a capacitor test structure and a method for obtaining the capacitance of a multi-capacitor structure.

[0007] In one aspect, the present invention provides a capacitance test structure, comprising:

[0008] A main test unit includes a multi-capacitor structure to be tested formed on a wafer, at least two first metal pads, and a first metal connection connecting the multi-capacitor structure to be tested and the at least two first metal pads, wherein the multi-capacitor structure to be tested includes a first number of capacitor devices arranged laterally and electrically connected on the wafer;

[0009] a first parasitic capacitance testing unit, comprising a first capacitance structure formed on the wafer, at least two second metal pads, and a second metal connection connecting the first capacitance structure and the at least two second metal pads, wherein the first capacitance structure comprises a second number of capacitance devices, and when the second number is greater than 1, the second number of capacitance devices are connected in parallel;

[0010] a second parasitic capacitance testing unit, comprising a second capacitance structure formed on the wafer, at least two third metal pads, and a third metal connection connecting the second capacitance structure and the at least two third metal pads, wherein the second capacitance structure comprises a third number of the capacitance devices connected in parallel, wherein the third number is n times the second number, the first number is greater than the sum of the second number and the third number, and n is an integer greater than 1;

[0011] The first metal connection, the second metal connection, and the third metal connection generate the same parasitic capacitance during capacitance testing; the at least two first metal pads, the at least two second metal pads, and the at least two third metal pads generate the same parasitic capacitance during capacitance testing; and the capacitance of the multi-capacitor structure to be tested satisfies the equation:

[0012] C11=C1-[C2-(C3-C2) / (n-1)], where C11, C1, C2, and C3 are respectively the capacitance of the multi-capacitor structure to be tested and the capacitance data obtained by performing capacitance testing using the main test unit, the first parasitic capacitance test unit, and the second parasitic capacitance test unit.

[0013] Optionally, in the multi-capacitor structure to be tested, the first number of capacitor devices are arranged in an array.

[0014] Optionally, the first metal connection line, the second metal connection line and the third metal connection line have the same material, structure and pattern.

[0015] Optionally, the at least two first metal pads, the at least two second metal pads, and the at least two third metal pads have the same material, structure, and pattern.

[0016] Optionally, the third number is twice the second number.

[0017] Optionally, the second number is 1 and the third number is 2.

[0018] Optionally, in the multi-capacitor structure to be tested, the first number of capacitor devices are connected in series, in parallel, or in a mixed series-parallel connection.

[0019] Optionally, when the first number of capacitive devices are connected in parallel, the capacitance of the multi-capacitor structure to be measured further satisfies the equation: C11 = (first number / second number)(C3-C2) / (n-1).

[0020] On the other hand, the present invention provides a method for obtaining the capacitance of a multi-capacitor structure, using the above-mentioned test structure, the method for obtaining the capacitance of the multi-capacitor structure includes:

[0021] Connecting a tester for testing capacitance to a probe card, the probe card comprising a set of probes for connecting the at least two first metal pads, the at least two second metal pads, and the at least two third metal pads;

[0022] Making the probe contact the at least two first metal pads and performing a first capacitance test to obtain capacitance data corresponding to the main test unit;

[0023] making the probe contact the at least two second metal pads and performing a second capacitance test to obtain capacitance data corresponding to the first parasitic capacitance test unit;

[0024] making the probe contact the at least two third metal pads and performing a third capacitance test to obtain capacitance data corresponding to the second parasitic capacitance test unit;

[0025] Substitute the capacitance data corresponding to the main test unit, the first parasitic capacitance test unit, and the second parasitic capacitance test unit into the equation C11=C1-[C2-(C3-C2) / (n-1)] to obtain the capacitance of the multi-capacitor structure to be tested.

[0026] Optionally, before performing the first capacitance test, the second capacitance test, and the third capacitance test, one end of the probe away from the metal pad is welded to a substrate and connected to the tester through the substrate.

[0027] The capacitance test structure provided by the present invention includes a main test unit, a first parasitic capacitance test unit and a second parasitic capacitance test unit. In the three test units, the parasitic capacitance generated by the metal connection is the same, and the parasitic capacitance generated by the metal pad is the same. By respectively using the main test unit, the first parasitic capacitance test unit and the second parasitic capacitance test unit to perform capacitance testing to obtain corresponding test data, and according to the equation C11=C1-[C2-(C3-C2) / (n-1)], the capacitance of the multi-capacitor structure to be tested can be calculated. The calculated capacitance of the multi-capacitor structure to be tested does not include the parasitic capacitance that is the same as the three test units, which can reduce the influence of parasitic capacitance and improve the capacitance accuracy of the multi-capacitor structure to be tested. In addition, the first number is greater than the sum of the second number and the third number. Compared with setting a parasitic capacitance test structure containing a first number of capacitor devices to obtain parasitic capacitance, the area occupied by the parasitic capacitance test structure can be reduced, the area of ​​the wafer test area can be saved, and the setting of the wafer test area can be more flexible.

[0028] The method for obtaining the capacitance of a multi-capacitor structure provided by the present invention adopts the above-mentioned capacitance test structure, and uses the main test unit, the first parasitic capacitance test unit and the second parasitic capacitance test unit to test and obtain corresponding capacitance data and substitute them into the equation C11=C1-[C2-(C3-C2) / (n-1)] to calculate the capacitance of the multi-capacitor structure to be tested (i.e., C11). Since the influence of parasitic capacitance is reduced, the calculated capacitance of the multi-capacitor structure to be tested has higher accuracy and can save the area of ​​the wafer test area. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 1 is a schematic diagram of a main test unit in a capacitance test structure according to an embodiment of the present invention and performing capacitance testing using the main test unit.

[0030] Figure 2 3 is a schematic diagram of a first parasitic capacitance testing unit in a capacitance testing structure according to an embodiment of the present invention and performing capacitance testing using the first parasitic capacitance testing unit.

[0031] Figure 3 3 is a schematic diagram of a second parasitic capacitance testing unit in a capacitance testing structure according to an embodiment of the present invention and performing capacitance testing using the second parasitic capacitance testing unit.

[0032] Figure 4 4 is a flow chart of a method for obtaining capacitance of a multi-capacitor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0033] The following is a further detailed description of the capacitance test structure of the present invention and the method for obtaining the capacitance of a multi-capacitor structure with reference to the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will become clearer. It should be noted that the terms "first", "second", etc. in the specification are used to distinguish between similar elements and are not necessarily used to describe a specific order or time sequence. It is to be understood that, where appropriate, these terms used in this way are interchangeable. It should be understood that the drawings of the specification are all in a very simplified form and are all in non-precise proportions, which are only used to facilitate and clearly assist in illustrating the purpose of the embodiments of the present invention. In addition, spatial relative terms are intended to include different orientations in use or operation in addition to the orientation of the device described in the figure. For example, if the structure in the drawing is inverted or positioned in other different ways (such as rotated), the exemplary term "on..." may also include "under..." and other orientation relationships.

[0034] The test unit for capacitance test is generally included in the capacitor structure to be measured formed in the test area (such as cutting road area) of wafer during wafer product tape-out, the metal wire connecting the capacitor structure to be measured and the metal pad connected to the capacitor structure to be measured by the metal wire. When carrying out capacitance test, the probe on the probe card can be used to contact the metal pad, and the probe card is connected to a tester in addition, and the probe card can transmit an electrical signal between the tester and the metal pad. When carrying out capacitance test, parasitic capacitance will be generated due to the metal wire between the tester, probe card probe, metal pad and the capacitor structure to be measured and the metal pad, and the test data obtained by directly using the above-mentioned test structure is the sum of the capacitance of the capacitor structure to be measured and the parasitic capacitance. If parasitic capacitance is deducted from the test result, the value obtained is closer to the actual value of the capacitance of the capacitor structure to be measured, that is, compared to directly using the test result as the capacitance of the capacitor structure to be measured, accuracy is higher. In order to obtain the accurate value of the capacitance of the capacitor structure to be measured, a parasitic capacitance test unit for testing parasitic capacitance can be additionally provided.

[0035] The embodiments of the present invention first relate to a capacitance test structure. Specifically, the embodiments of the present invention relate to a capacitance test structure capable of testing the capacitance of a capacitance structure including multiple capacitance devices, wherein, in order to reduce the influence of parasitic capacitance, the capacitance test structure includes a parasitic capacitance test unit in addition to a main test unit for testing the sum of the capacitance and parasitic capacitance of the capacitance structure to be tested, and, in order to avoid the parasitic capacitance test unit occupying a large area and affecting the wafer test area layout, the parasitic capacitance test unit in the capacitance test structure includes a first parasitic capacitance test unit and a second parasitic capacitance test unit, as described in detail below.

[0036] In the embodiment of the present invention, the capacitance test structure includes a main test unit 110 , a first parasitic capacitance test unit 120 and a second parasitic capacitance test unit 120 , which are described in detail as follows.

[0037] Reference Figure 1 The main test unit 110 includes a multi-capacitor structure 10 to be tested formed on a wafer, at least two first metal pads (such as Figure 1 The multi-capacitor structure 10 to be tested comprises a first number of capacitor devices D1 that are laterally arranged and electrically connected on the wafer.

[0038] The main test unit 110 is used to perform a capacitance test on a multi-capacitor structure 10 to be tested, wherein the multi-capacitor structure 10 to be tested includes a first number of capacitor devices D1, and the multi-capacitor structure 10 to be tested is formed, for example, on a surface area of ​​a wafer. The first number is, for example, an integer greater than 3. The first number of capacitor devices can be connected in series, in parallel, or in a mixed series-parallel connection to form the multi-capacitor structure 10 to be tested. The multi-capacitor structure 10 to be tested may have at least two connection ends, and the first metal connection W1 may include a metal line and a via formed above the multi-capacitor structure 10 to be tested, and the first metal connection W1 may be connected to the multi-capacitor structure 10 to be tested by connecting the at least two connection ends. The first metal pad is, for example, formed above the first metal connection W1 and connected to the multi-capacitor structure 10 to be tested via the first metal connection W1. As an example, the first number of capacitor devices D1 in the multi-capacitor structure 10 to be tested are, for example, connected in parallel, the upper plates of each capacitor device D1 are connected and connected to the first metal pad PAD1, and the lower plates of each capacitor device D1 are connected and connected to the second metal pad PAD2. In this embodiment, the first number of capacitor devices are arranged in an array, which may be arranged in multiple rows and columns. However, this is not limiting. In other embodiments, the first number of capacitor devices in the multi-capacitor structure 10 to be tested may not be arranged in an array.

[0039] When the capacitance of the multi-capacitor structure 10 to be tested is tested using the main test unit 110, a probe can be used to contact each of the first metal pads in the main test unit 110, and the other end of the probe can be connected to a tester for performing capacitance testing. When the capacitance test is performed using the main test unit 110, the capacitance test data (denoted as C1) measured by the tester is the sum of the capacitance of the multi-capacitor structure 10 to be tested (denoted as C11) and a total parasitic capacitance (denoted as Ct), which satisfies the following equation (1):

[0040] C1=C11+Ct (1)

[0041] In equation (1), the total parasitic capacitance Ct includes the parasitic capacitance caused by the first metal connection, the parasitic capacitance caused by the first metal pad, the parasitic capacitance caused by the probe, and the parasitic capacitance caused by the tester.

[0042] Reference Figure 2 The first parasitic capacitance test unit 120 includes a first capacitance structure 20 formed on the wafer, at least two second metal pads (such as Figure 2 The first capacitor structure 20 includes a first capacitor structure 20 and a second metal connection line W2 connecting the first capacitor structure 20 and the at least two second metal pads. The first capacitor structure 20 includes a second number of capacitor devices D1. When the second number is greater than 1, the second number of capacitor devices are connected in parallel. As an example, the second number is 1.

[0043] Reference Figure 3 The second parasitic capacitance test unit 130 includes a second capacitance structure 30 formed on the wafer, at least two third metal pads (such as Figure 3 The second capacitor structure 30 includes a third number of capacitor devices D1 connected in parallel. As an example, the third number is 2.

[0044] The first parasitic capacitance test unit 120 and the second parasitic capacitance test unit 130 are used to calculate the total parasitic capacitance Ct in the above equation (1) using the corresponding capacitance detection values. Specifically, in this embodiment, the main test unit 110, the first parasitic capacitance test unit 120, and the second parasitic capacitance test unit 130 are made to have substantially the same total parasitic capacitance Ct during the capacitance test. In this way, after the corresponding capacitance test data C1 is measured by the main test unit 110 and the total parasitic capacitance Ct is obtained by the first parasitic capacitance test unit 120 and the second parasitic capacitance test unit 130, the capacitance C11 of the multi-capacitor structure 10 to be tested can be calculated according to the above equation (1).

[0045] When the first parasitic capacitance test unit 120 is used to perform capacitance testing, the corresponding parasitic capacitance includes the parasitic capacitance generated by the second metal connection W2, the parasitic capacitance generated by the second metal pad, the capacitance generated by the probe connected to the second metal pad, and the capacitance generated by the tester. When the second parasitic capacitance test unit 130 is used to perform capacitance testing, the corresponding parasitic capacitance includes the parasitic capacitance generated by the third metal connection W3, the parasitic capacitance generated by the third metal pad, the capacitance generated by the probe connected to the third metal pad, and the capacitance generated by the tester. In this embodiment, the parasitic capacitance generated by the first metal connection W1, the second metal connection W2, and the third metal connection W3 during capacitance testing is set to be the same, the parasitic capacitance generated by the first metal pad in the main test unit 110, the second metal pad in the first parasitic capacitance test unit 120, and the third metal pad in the second parasitic capacitance test unit 130 are the same, and in addition, the same tester 150 and probe 141 (refer to Figures 1 to 3 ) performs capacitance testing on the main test unit 110, the first parasitic capacitance test unit 120, and the second parasitic capacitance test unit 130, so that the total parasitic capacitance Ct corresponding to the main test unit 110, the first parasitic capacitance test unit 120, and the second parasitic capacitance test unit 130 are substantially the same.

[0046] As an example, the first metal connection W1 in the main test unit 110, the second metal connection W2 in the first parasitic capacitance test unit 120, and the third metal connection W3 in the second parasitic capacitance test unit 130 have the same material, structure, and pattern. Therefore, when performing a capacitance test, the parasitic capacitance generated by the first metal connection W1, the second metal connection W2, and the third metal connection W3 is the same. In addition, as an example, the first metal pad in the main test unit 110, the second metal pad in the first parasitic capacitance test unit 120, and the third metal pad in the second parasitic capacitance test unit 130 have the same material, structure, and pattern. Therefore, when performing a capacitance test, the parasitic capacitance generated by the at least two first metal pads, the at least two second metal pads, and the at least two third metal pads is the same.

[0047] To save area on the wafer test region, the total occupied area of ​​the first parasitic capacitance test unit 120 and the second parasitic capacitance test unit 130 can be set to be smaller than the occupied area of ​​the main test unit 110. In this embodiment, the total number of capacitive devices D1 in the first parasitic capacitance test unit 120 and the second parasitic capacitance test unit 130 is smaller than the number of capacitive devices D1 in the main test unit 110, that is, the first number is greater than the sum of the second number and the third number. As a result, the total occupied area of ​​the first parasitic capacitance test unit 120 and the second parasitic capacitance test unit 130 is smaller than the occupied area of ​​the main test unit 110. Compared to setting up the parasitic capacitance test structure according to the arrangement of the capacitive devices D1 of the main test structure 110, the area of ​​the test region can be saved.

[0048] The capacitance test data obtained by performing capacitance testing using the first parasitic capacitance testing unit 120 is recorded as C2, wherein the capacitance of the first capacitance structure 20 is recorded as C21, and the total parasitic capacitance is Ct, which satisfies the following equation (2):

[0049] C2=C21+Ct (2)

[0050] The capacitance test data obtained by performing capacitance testing using the second parasitic capacitance testing unit 130 is recorded as C3, wherein the capacitance of the second capacitance structure 30 is recorded as C31, and the total parasitic capacitance is Ct, which satisfies the following equation (3):

[0051] C3=C31+Ct (3)

[0052] In the above equations (1) and (2), the capacitance C21 of the first capacitor structure 20 is the product of the capacitance of the single capacitor device D1 and the second number, that is, C21 = the second number × the capacitance of the single capacitor device. The capacitance C31 of the second capacitor structure 30 is the product of the capacitance of the single capacitor device D1 and the third number, that is, C31 = the third number × the capacitance of the single capacitor device. In this embodiment, the third number is n times the second number (n>1 and is an integer), so the capacitance C31 of the second capacitor structure 30 is n times the capacitance C21 of the first capacitor structure 20, that is, the following equation (4) is satisfied:

[0053] C31=n×C21 (4)

[0054] Subtracting equation (3) from equation (2) yields equation (5), which in turn yields equation (6):

[0055] C3-C2=(n-1)C21 (5)

[0056] C21=(C3-C2) / (n-1) (6)

[0057] Further, substituting equation (6) into equation (2), the following equation (7) can be obtained:

[0058] Ct= C2- (C3- C2) / (n- 1) (7)

[0059] Further, substituting equation (7) into equation (1), the following equation (8) can be obtained:

[0060] C11= C1- [C2- (C3- C2) / (n- 1)] (8)

[0061] Equation (8) shows the relationship between the capacitance C11 of the to-be-tested multi-capacitance structure 10 and the capacitance test data C1-C3 obtained by respectively using the main test unit 110, the first parasitic capacitance test unit 120 and the second parasitic capacitance test unit 130 to perform capacitance test. Therefore, after obtaining the capacitance test data C1-C3, the capacitance C11 of the to-be-tested multi-capacitance structure 10 can be calculated according to equation (8), and the calculated value of the capacitance C11 reduces the influence of parasitic capacitance and is accurate. As an example, the third number is twice the second number (i.e. n = 2).

[0062] In some embodiments, in the main test unit 110, the first number of capacitor devices D1 are connected in parallel, and the capacitance C11 of the to-be-tested multi-capacitance structure 10 is the sum of the capacitances of each capacitor device D1, i.e. equal to the product of the capacitance of a single capacitor device D1 and the first number. Since the capacitance C21 of the first capacitance structure 20 in the first parasitic capacitance test unit 120 is the product of the capacitance of a single capacitor device D1 and the second number, the following equation (9) can be obtained:

[0063] C11 / first number = C21 / second number (9)

[0064] Substituting equation (6) into equation (9), the following equation (10) can be obtained:

[0065] C11= (first number / second number) (C3- C2) / (n- 1) (10)

[0066] It can be seen that after obtaining the corresponding capacitance test data C2 and C3 by respectively using the first parasitic capacitance test unit 120 and the second parasitic capacitance test unit 130 to perform capacitance test, the capacitance C11 of the to-be-tested multi-capacitance structure 10 can also be calculated according to equation (10). The capacitance C11 calculated by equation (10) can be used to verify or correct the capacitance C11 obtained by equation (9). For example, according to the need, the capacitance C11 of the to-be-tested multi-capacitance structure 10 can be calculated according to equation (9) and equation (10) respectively, and the average of the two is taken as the capacitance of the to-be-tested multi-capacitance structure 10 to improve the accuracy.

[0067] The capacitance test structure described in the above embodiment can be used to obtain the capacitance C11 of the multi-capacitance structure 10 to be tested including multiple capacitance devices D1. The obtained capacitance C11 does not include the above-mentioned total parasitic capacitance Ct, which can reduce the influence of parasitic capacitance and improve the capacitance accuracy of the multi-capacitance structure to be tested. In addition, the first number is greater than the sum of the second number and the third number. Compared with setting up a parasitic capacitance test structure containing the first number of capacitance devices to obtain parasitic capacitance, the area occupied by the parasitic capacitance test structure can be reduced, the area of ​​the test area can be saved, and the setting of the test area can be more flexible.

[0068] An embodiment of the present invention also relates to a method for obtaining the capacitance of a multi-capacitor structure. The multi-capacitor structure includes a plurality of electrically connected capacitor devices, wherein the plurality of capacitor devices can be connected in series, in parallel, or in a mixed series-parallel connection. The method for obtaining the capacitance of a multi-capacitor structure adopts the capacitance test structure described in the above embodiment, wherein the multi-capacitor structure to obtain the capacitance is the multi-capacitor structure 10 to be tested in the main test unit 110. The features of the main test unit 110, the first parasitic capacitance test unit 120, and the second parasitic capacitance test unit 130 can be referred to the description in the above embodiment and will not be repeated here.

[0069] Reference Figures 1 to 4 , the method for obtaining the capacitance of the multi-capacitor structure includes the following process:

[0070] Step S1 , connecting a tester 150 for capacitance testing to a probe card, wherein the probe card includes a set of probes 141 for connecting the at least two first metal pads, the at least two second metal pads, and the at least two third metal pads;

[0071] Step S2, making the probe contact the at least two first metal pads and performing a first capacitance test to obtain capacitance test data corresponding to the main test unit 110;

[0072] Step S3, making the probe contact the at least two second metal pads and performing a second capacitance test to obtain capacitance test data corresponding to the first parasitic capacitance testing unit 120;

[0073] Step S4, making the probe contact the at least two third metal pads and performing a third capacitance test to obtain capacitance test data corresponding to the second parasitic capacitance testing unit 130; and

[0074] Substitute the capacitance test data corresponding to the main test unit 110, the first parasitic capacitance test unit 120, and the second parasitic capacitance test unit 130 into the equation

[0075] C11=C1-[C2-(C3-C2) / (n-1)], to obtain the capacitance C11 of the multi-capacitor structure 10 to be measured.

[0076] In the above method for obtaining the capacitance of the multi-capacitor structure, the order of the capacitance tests in step S2, step S3 and step S4 is not particularly limited. The first capacitance test may be performed first, or the second capacitance test or the third capacitance test, and the last test may be performed last, or the first capacitance test or the second capacitance test.

[0077] Reference Figures 1 to 3 In some embodiments, before performing the capacitance test of steps S2 to S4, the probe 141 can be set so that the end away from the metal pad (i.e., the end opposite to the needle tip) is welded to a substrate 142 and connected to the tester 150 through the substrate 142 to fix the position of the probe before performing the first capacitance test, the second capacitance test, and the third capacitance test. This ensures that the parasitic capacitance introduced by the probe 141 during the first capacitance test, the second capacitance test, and the third capacitance test is basically consistent, and the parasitic capacitance introduced by the tester 150 is basically consistent.

[0078] In an embodiment of the present invention, a method for obtaining the capacitance of a multi-capacitor structure adopts the above-mentioned capacitance test structure, and uses the main test unit 110, the first parasitic capacitance test unit 120 and the second parasitic capacitance test unit 130 to detect the corresponding capacitance and substitute it into equation (1). The capacitance C11 of the multi-capacitor structure 10 to be tested can be obtained, that is, the capacitance of the multi-capacitor structure formed by the multiple capacitor devices D1 can be obtained, and the influence of the parasitic capacitance is reduced, so that the accuracy of the capacitance test data is higher, and the area of ​​the wafer test area can be saved, making the setting of the wafer test area more flexible.

[0079] The above description is only a description of the preferred embodiment of the present invention, and does not limit the scope of the rights of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A capacitance test structure, characterized in that: include: A main test unit includes a multi-capacitor structure to be tested formed on a wafer, at least two first metal pads, and a first metal connection connecting the multi-capacitor structure to be tested and the at least two first metal pads, wherein the multi-capacitor structure to be tested includes a first number of capacitor devices arranged laterally and electrically connected on the wafer; a first parasitic capacitance testing unit, comprising a first capacitance structure formed on the wafer, at least two second metal pads, and a second metal connection connecting the first capacitance structure and the at least two second metal pads, wherein the first capacitance structure comprises a second number of capacitance devices, and when the second number is greater than 1, the second number of capacitance devices are connected in parallel; a second parasitic capacitance testing unit, comprising a second capacitance structure formed on the wafer, at least two third metal pads, and a third metal connection connecting the second capacitance structure and the at least two third metal pads, wherein the second capacitance structure comprises a third number of the capacitance devices connected in parallel, wherein the third number is n times the second number, the first number is greater than the sum of the second number and the third number, and n is an integer greater than 1; The first metal connection, the second metal connection, and the third metal connection generate the same parasitic capacitance during capacitance testing; the at least two first metal pads, the at least two second metal pads, and the at least two third metal pads generate the same parasitic capacitance during capacitance testing; and the capacitance of the multi-capacitor structure to be tested satisfies the equation: C11=C1-[C2-(C3-C2) / (n-1)], where C11, C1, C2, and C3 are respectively the capacitance of the multi-capacitor structure to be tested and the capacitance data obtained by performing capacitance testing using the main test unit, the first parasitic capacitance test unit, and the second parasitic capacitance test unit.

2. The capacitance test structure according to claim 1, wherein: In the multi-capacitor structure to be tested, the first number of capacitor devices are arranged in an array.

3. The capacitance test structure according to claim 1, wherein: The first metal connection line, the second metal connection line and the third metal connection line have the same material, structure and pattern.

4. The capacitance test structure according to claim 1, wherein: The at least two first metal pads, the at least two second metal pads, and the at least two third metal pads have the same material, structure, and pattern.

5. The capacitance test structure according to claim 1, wherein: The third number is twice the second number.

6. The capacitance test structure according to claim 1, wherein: The second number is 1, and the third number is 2.

7. The capacitance test structure according to any one of claims 1 to 5, characterized in that: In the multi-capacitor structure to be tested, the first number of capacitor devices are connected in series, in parallel, or in a mixed series-parallel connection.

8. The capacitance test structure according to claim 6, wherein: When the first number of capacitive devices are connected in parallel, the capacitance of the multi-capacitor structure to be measured further satisfies the equation: C11 = (first number / second number)(C3-C2) / (n-1).

9. A method for obtaining capacitance of a multi-capacitor structure, characterized in that: Using the capacitance test structure according to any one of claims 1 to 8, the method for obtaining the capacitance of the multi-capacitor structure includes: Connecting a tester for testing capacitance to a probe card, the probe card comprising a set of probes for connecting the at least two first metal pads, the at least two second metal pads, and the at least two third metal pads; making the probe contact the at least two first metal pads and performing a first capacitance test to obtain capacitance data corresponding to the main test unit; making the probe contact the at least two second metal pads and performing a second capacitance test to obtain capacitance data corresponding to the first parasitic capacitance test unit; making the probe contact the at least two third metal pads and performing a third capacitance test to obtain capacitance data corresponding to the second parasitic capacitance test unit; Substitute the capacitance data corresponding to the main test unit, the first parasitic capacitance test unit, and the second parasitic capacitance test unit into the equation C11=C1-[C2-(C3-C2) / (n-1)] to obtain the capacitance of the multi-capacitor structure to be tested.

10. The method for obtaining capacitance of a multi-capacitor structure according to claim 9, wherein: Before performing the first capacitance test, the second capacitance test, and the third capacitance test, one end of the probe away from the metal pad is welded to a substrate and connected to the tester through the substrate.

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