Novel hybrid nested noise shaping architecture suitable for noise shaping SAR ADC

Abstract

The invention provides a novel hybrid nested noise shaping architecture suitable for a noise shaping SAR ADC (Synthetic Aperture Radar Analog to Digital Converter), the shaping architecture adopts a dynamically working closed-loop cascode FIA as a residual amplifier, so that the power consumption is reduced by eliminating the quiescent current of the amplifier and removing a gain calibration circuit; the shaping architecture executes fourth-order noise shaping through a second-order CIFF and a second-order EF noise shaping loop which are nested so as to achieve high precision during noise shaping at the same oversampling rate, and the shaping architecture reduces the capacitance value of a sampling capacitor through an integrated sampling noise cancellation (SNC) method so as to save the area of a chip; according to the architecture, a closed-loop cascode FIA is used as a residual amplifier, and a CIFF and an EF are used as noise shaping loops, so that the problem that high precision and low power consumption are difficult to realize simultaneously by a traditional noise shaping SAR ADC is solved. In addition, a sampling KT / C noise cancellation (SNC) technology is also integrated, so that the capacitance value of a sampling capacitor is reduced, and the area of a chip is saved.

Description

Technical Field

[0001] The present invention relates to the field of noise processing technology, and in particular to a novel hybrid nested noise shaping architecture suitable for noise shaping SAR ADC. Background Art

[0002] Noise shaping is achieved by inputting the residual voltage quantized by the analog-to-digital converter (ADC) into the noise shaping architecture and passing the output of the noise shaping architecture back to the ADC to achieve the effect of shaping the quantization noise of the ADC to a high frequency, thereby improving the accuracy of the ADC. The noise shaping ADC needs to add a loop filter to the original ADC to form a noise shaping loop. Common noise shaping loops include cascaded integrator feed-forward (CIFF) and error feedback (EF). Among various types of noise shaping ADCs, the noise shaping successive approximation register (SAR) ADC has attracted much attention because it inherits the advantages of SAR ADC's excellent power efficiency and easy digital implementation.

[0003] There are several types of noise shaping architectures currently available. Their architectures and shortcomings are as follows:

[0004] (1) An infinite impulse response (IIR) filter is formed through a closed-loop active amplifier to form a noise shaping architecture. However, this will seriously increase the power consumption of the ADC.

[0005] (2) By sharing the charge between capacitors, a fully passive loop filter is formed to form a noise shaping architecture. However, since the charge sharing between capacitors will cause the transmission signal to attenuate step by step, the noise shaping effect is poor and it is impossible to achieve too high accuracy;

[0006] (3) A loop filter composed of an open-loop dynamic amplifier and a passive switched capacitor is used to form a noise shaping architecture. The gain of the open-loop dynamic amplifier can compensate for the signal attenuation caused by charge sharing between capacitors. However, the gain of the open-loop dynamic amplifier varies greatly with process-voltage-temperature (PVT) fluctuations, and usually requires an additional gain calibration circuit;

[0007] (4) A loop filter composed of an open-loop floating inverter amplifier (FIA) and a switched capacitor is used to form a noise shaping architecture. Compared with ordinary open-loop dynamic amplifiers, the gain of the open-loop FIA has better PVT robustness, but the open-loop FIA is limited by the trade-off between the load capacitance and the output linearity and is not suitable for high-precision noise shaping SAR ADCs. Summary of the invention

[0008] The present invention proposes a novel hybrid nested noise shaping architecture suitable for noise shaping SAR ADC, which adopts a closed-loop common source and common gate FIA ​​as a residual amplifier and uses CIFF and EF as a noise shaping loop to solve the problem that traditional noise shaping SAR ADC is difficult to achieve high precision and low power consumption at the same time. In addition, sampling KT / C noise cancellation (SNC) technology is also integrated to reduce the capacitance of the sampling capacitor and save chip area.

[0009] The present invention adopts the following technical solutions.

[0010] A novel hybrid nested noise shaping architecture suitable for noise shaping SAR ADC is characterized in that: the shaping architecture adopts a dynamically operating closed-loop common-source and common-gate FIA ​​as a residual amplifier to reduce power consumption by eliminating the quiescent current of the amplifier and removing the gain calibration circuit; the shaping architecture performs fourth-order noise shaping by nested second-order CIFF and second-order EF noise shaping loops to achieve high accuracy when shaping noise at the same oversampling rate; the shaping architecture reduces the capacitance of the sampling capacitor by integrating a sampling KT / C noise cancellation (SNC) method to save chip area.

[0011] The top-level circuit of the shaping architecture is as follows Figure 1 As shown in part a of FIG. 1 , it includes a CIFF noise shaping loop CIFF loop, an EF noise shaping loop EF loop, a residual amplifier (ResidueAmplifier) ​​and a sampling noise elimination module SNC; the top circuit is connected through port V DACN 、V DACP Connected to the capacitive digital-to-analog converter CDAC (capacitive digital-to-analog converter, CDAC) of the SAR ADC through port V P 、V N Connected to the comparator of SAR ADC.

[0012] The noise source and noise shaping implementation flow of the nested noise shaping architecture is as follows:

[0013] (1) The noise sources processed by the noise shaping architecture mainly include two parts:

[0014] ① SAR ADC will generate quantization noise after completing one quantization, and the quantization noise is evenly distributed in the range from 0Hz to half the sampling frequency;

[0015] ② The sampling noise generated when the SAR ADC samples the input signal. The quantization noise and sampling noise of the SAR ADC are both transmitted through port V DACP and V DACN Passed into the noise shaping architecture.

[0016] (2) The noise shaping implementation process is as follows. ① First, after the SAR ADC samples the input signal, the sampling noise passes through port V DACP and V DACN ② The quantization noise generated by the SAR ADC is extracted and amplified by the residual amplifier after the SAR ADC completes the quantization process of the current cycle; ③ After that, the amplified quantization noise is simultaneously transmitted to the CIFF noise shaping loop and the EF noise shaping loop. The CIFF noise shaping loop and the EF noise shaping loop perform high-pass filtering on the quantization noise, so that the low-frequency (within the signal bandwidth frequency range) quantization noise is suppressed. ④ Finally, the filtered quantization noise is transmitted through port V P 、V N 、V DACP 、V DACN It is then transmitted back to the SAR ADC and participates in the quantization process of the next cycle. At this time, the influence of quantization noise within the signal bandwidth frequency range will be suppressed, and the effect of noise shaping is finally achieved.

[0017] Specific circuit components are connected as follows Figure 1 to Figure 3 As shown. The top circuit consists of switches S1 to S 52 , capacitor C DELN , capacitor C DELP , capacitor C FIR1N , capacitor C FIR1P , capacitor C FIR2N , capacitor C FIR2P , capacitor C EXAN , capacitor C EXAP , capacitor C SUMN , capacitor C SUMP , capacitor C SNCN , capacitor C SNCP , capacitor C INT1N , capacitor C INT1P , capacitor C RESN , capacitor C RESP , capacitor C INT2_1, capacitor C INT2_2 , capacitor C INT2_3 , capacitor C INT2_4 and amplifier G, amplifier G NC composition.

[0018] One end of the switch S1 is connected to port V CM The other end is connected to switch S3, switch S5 and capacitor C DELP One end of switch S2 is connected to port V CM The other end is connected to switch S4, switch S6 and capacitor C DELN One end of switch S3 is connected to port V DACP The other end is connected to switch S1, switch S5 and capacitor C DELP One end of switch S4 is connected to port V DACN The other end is connected to switch S2, switch S6 and capacitor C DELN One end of the switch S5 is connected to the switch S7 and the capacitor C FIR2P One end of the switch S1, the other end of the switch S3 and the capacitor C DELP One end of the switch S6 is connected to the switch S8 and the capacitor C FIR2N One end of the switch S2, the other end of the switch S4 and the capacitor C DELN One end of switch S7 is connected to port V ON , the other end is connected to switch S5 and capacitor C FIR2P One end of switch S8 is connected to port V OP , the other end is connected to switch S6 and capacitor C FIR2N One end of switch S9 is connected to port V DACP , the other end is connected to the switch S 11 And the capacitor C FIR1P One end of switch S 10 Connect one end of the port V DACN , the other end is connected to the switch S 12 And the capacitor C FIR1N One end of switch S 11 Connect one end of the port V OP , the other end is connected to switch S9 and capacitor C FIR1P One end of switch S 12 Connect one end of the port V ON , the other end is connected to the switch S 10 And the capacitor C FIR1N One end of switch S 13 Connect one end of the port V CM , the other end is connected to port V ON ; Switch S 14Connect one end of the port V CM , the other end is connected to port V OP ; Switch S 15 Connect one end of the port V DACP , and the other end is connected to the positive (+) input terminal (V IP2 ), switch S 17 And the capacitor C EXAP One end of switch S 16 Connect one end of the port V DACN The other end is connected to the negative (-) input terminal of amplifier G (V IN2 ), switch S 18 And the capacitor C EXAN One end of switch S 17 One end is connected to the positive (+) input terminal (V IP2 ), switch S 15 And the capacitor C EXAP One end is connected to port V CM ; Switch S 18 One end is connected to the negative (-) input terminal (V IN2 ), switch S 16 And the capacitor C EXAN , the other end is connected to port V CM ; Switch S 19 Connect one end of the port V DACP , the other end is connected to port V CM ; Switch S 20 Connect one end of the port V DACN , the other end is connected to port V CM ; Switch S 21 One end of the node is connected to node ① (such as Figure 1 The other end is connected to port V CM ; Switch S 22 One end is connected to node ②, and the other end is connected to port V CM ; Switch S 23 Connect one end of the port V DACP , the other end is connected to the switch S 27 And the capacitor C SNCP One end of switch S 24 Connect one end of the port V DACN , the other end is connected to the switch S 28 And the capacitor C SNCN One end of switch S 25 One end is connected to node ①, and the other end is connected to switch S 29 And the capacitor C SNCP One end of switch S 26One end is connected to node ②, and the other end is connected to switch S 30 And the capacitor C SNCN One end of switch S 27 One end of the amplifier is connected to G NC The positive (+) output terminal (V OUTP1 ), the other end is connected to the switch S 23 And the capacitor C SNCP One end of switch S 28 One end of the amplifier is connected to G NC The negative (-) output terminal (V OUTN1 ), the other end is connected to the switch S 24 And the capacitor C SNCN One end of switch S 29 Connect one end of the port V CM , the other end is connected to the switch S 25 And the capacitor C SNCP One end of switch S 30 Connect one end of the port V CM , the other end is connected to the switch S 26 And the capacitor C SNCN One end of switch S 31 Connect one end of the port V CM , the other end is connected to the switch S 33 And the capacitor C RESP One end of switch S 32 Connect one end of the port V CM , the other end is connected to the switch S 34 And the capacitor C RESN One end of switch S 33 One end is connected to node ①, and the other end is connected to switch S 31 And the capacitor C RESP One end of switch S 34 One end is connected to node ②, and the other end is connected to switch S 32 And the capacitor C RESN One end of switch S 35 One end is connected to node ③, and the other end is connected to switch S 39 And the capacitor C INT1P One end of switch S 36 One end is connected to node ④, and the other end is connected to switch S 46 And the capacitor C INT1N One end of switch S 37 One end is connected to node ③, and the other end is connected to port V OP ; Switch S 38 One end is connected to node ④, and the other end is connected to port V ON ; Switch S 39 One end of the switch S35 And the capacitor C INT1P One end of the switch S 42 And the capacitor C INT2_1 One end of switch S 40 One end is connected to node ③, and the other end is connected to switch S 41 And the capacitor C INT2_1 One end of switch S 41 One end of the switch S 40 And the capacitor C INT2_1 One end of the switch S 45 And the capacitor C INT2_2 One end of switch S 42 One end is connected to node ④, and the other end is connected to switch S 39 And the capacitor C INT2_1 One end of switch S 43 One end is connected to node ③, and the other end is connected to switch S 44 And the capacitor C INT2_2 One end of switch S 44 Connect one end of the port V P , the other end is connected to the switch S 43 And the capacitor C INT2_2 One end of switch S 45 One end is connected to node ④, and the other end is connected to switch S 41 And the capacitor C INT2_2 One end of switch S 46 One end of the switch S 36 And the capacitor C INT1N One end of the switch S 47 And the capacitor C INT2_3 One end of switch S 47 One end is connected to node ③, and the other end is connected to switch S 46 And the capacitor C INT2_3 One end of switch S 48 One end of the switch S 49 And the capacitor C INT2_3 One end of the switch S 50 And the capacitor C INT2_4 One end of switch S 49 One end is connected to node ④, and the other end is connected to switch S 48 And the capacitor C INT2_3 One end of switch S 50 One end is connected to node ③, and the other end is connected to switch S 48 And the capacitor C INT2_4 One end of switch S 51 Connect one end of the port V N , the other end is connected to the switch S52 And the capacitor C INT2_4 One end of switch S 52 One end is connected to node ④, and the other end is connected to switch S 51 And the capacitor C INT2_4 One end of the capacitor C DELN Connect one end of the port V CM , the other end is connected to one end of switch S2, switch S4 and switch S6; capacitor C DELN Connect one end of the port V CM , the other end is connected to one end of switch S1, switch S3 and switch S5; capacitor C FIR1N Connect one end of the port V CM , the other end is connected to the switch S 10 And switch S 12 One end of the capacitor C FIR1P Connect one end of the port V CM , the other end is connected to switch S9 and switch S 11 One end of the capacitor C FIR2N Connect one end of the port V CM , the other end is connected to switch S6 and one end of switch S8; capacitor C FIR2P Connect one end of the port V CM , the other end is connected to switch S5 and one end of switch S7; capacitor C EXAN Connect one end of the port V OP The other end is connected to the negative (-) input terminal of amplifier G (V IN2 ), switch S 16 And switch S 18 One end of the capacitor C EXAP Connect one end of the port V ON , and the other end is connected to the positive (+) input terminal (V IP2 ), switch S 15 And switch S 17 One end of the capacitor C SUMN Connect one end of the port V DACN , the other end is connected to node ②; capacitor C SUMP Connect one end of the port V DACP , the other end is connected to node ①; capacitor C SNCN One end of the switch S 24 And switch S 28 One end of the switch S 26 And switch S 30 One end of the capacitor C SNCP One end of the switch S 23 And switch S 27 One end of the switch S 25And switch S 29 One end of the capacitor C INT1N One end is connected to node ②, and the other end is connected to switch S 36 And switch S 46 One end of the capacitor C INT1P One end is connected to node ①, and the other end is connected to switch S 35 And switch S 39 One end of the capacitor C RESN One end is connected to node ④, and the other end is connected to switch S 32 And switch S 34 One end of the capacitor C RESP One end is connected to node ③, and the other end is connected to switch S 31 And switch S 33 One end of the capacitor C INT2_1 One end of the switch S 39 And switch S 42 One end of the switch S 40 And switch S 41 One end of the capacitor C INT2_2 One end of the switch S 41 And switch S 45 One end of the switch S 43 And switch S 44 One end of the capacitor C INT2_3 One end of the switch S 46 And switch S 47 One end of the switch S 48 And switch S 49 One end of the capacitor C INT2_4 One end of the switch S 48 And switch S 50 One end of the switch S 51 And switch S 52 One end of the amplifier G's positive (+) input (V IP2 )Connect switch S 15 , switch S 17 And the capacitor C EXAP One end, negative (-) input terminal (V IN2 )Connect switch S 16 , switch S 18 And the capacitor C EXAN One end, positive output end (V OUTP2 ) Connect port V OP , negative (-) output terminal (V OUTN2 ) Connect port V ON ; Amplifier G NC The positive (+) input terminal (V IP1) connects to node ①, the negative (-) input terminal (V IN1 ) connects to node ②, the positive output terminal (V OUTP1 )Connect switch S 27 One end, negative (-) output end (V OUTN1 )Connect switch S 28 one end.

[0019] The noise shaping process of the shaping architecture is as follows: First, the SAR ADC sampling noise voltage is passed through V DACP and V DACN The port is passed to the SNC circuit to be offset, and then the residual voltage of the current cycle obtained after quantization of the SAR ADC is input into the hybrid nested noise shaping architecture, amplified by the residual amplifier, and then the amplified residual voltage is input into the CIFF and EF noise shaping loops respectively; finally, the output voltages of the CIFF and EF noise shaping loops are respectively output through V P 、V N and V DACP 、V DACN The port is transmitted back to the SAR ADC to implement the noise shaping function.

[0020] The residual amplifier input voltage signal is V DACP and V DACN , the output is V OP and V ON After the input signal is quantized by the SARADC, the residual voltage of the current cycle is obtained, which is amplified by the residual amplifier and input into the CIFF and EF noise shaping loops.

[0021] The SNC circuit is independent of the rest of the hybrid nested noise shaping architecture, which includes a plurality of capacitors and switches;

[0022] In the sampling noise elimination module SNC part of the shaping architecture, if the sampling KT / C noise cannot be shaped, it will all be passed to the output end, and a large sampling capacitor will be used to reduce the sampling KT / C noise. By using SNC technology to reduce the sampling KT / C noise, a smaller sampling capacitor can be used under the same accuracy requirements, reducing the area overhead of the circuit and making the ADC easier to be driven by the previous circuit; the working process of SNC includes the extraction stage and the elimination stage.

[0023] The SNC circuit uses an amplifier G NC ( Figure 1 Indicated as G NC ) adopts an open-loop FIA architecture, and its circuit is as follows Figure 2 As shown, M N1 、M N2 、M P1 、MP2 As an input tube, it realizes the function of inverting and amplifying the input signal. RSV1 As an energy storage capacitor, it realizes the function of providing energy during the amplification stage.

[0024] Assume M N× Both represent N-type metal-oxide-semiconductor field-effect transistor MOS, M P× All represent P-type metal-oxide-semiconductor field-effect transistors MOS, where × represents any number, then in the SNC circuit, M N1 、M N2 、M P1 、M P2 As an input tube, it can realize the function of inverting and amplifying the input signal. RSV1 As an energy storage capacitor, it provides energy during the amplification stage;

[0025] Amplifier G NC The circuit consists of switch S 53 ~S 56 , capacitor C RSV1 and transistor M N1 , transistor M N2 , transistor M P1 , transistor M P2 . The switch S 53 One end is connected to the power supply V DD , the other end is connected to the switch S 55 And the capacitor C RSV1 One end of switch S 54 One end is connected to ground GND, and the other end is connected to the switch S 56 And the capacitor C RSV1 One end of switch S 55 One end of the switch S 53 And the capacitor C RSV1 One end is connected to transistor M P1 The source terminal and transistor M P2 Source end; switch S 56 One end of the switch S 54 And the capacitor C RSV1 One end is connected to transistor M N1 The source terminal and transistor M N2 Source terminal; transistor M P1 The source terminal is connected to transistor M P2 Source and switch S 55 One end of transistor M P1 The drain terminal is connected to the amplifier G NC Negative (-) output terminal (V OUTN1 ), transistor M P1 The gate terminal is connected to the amplifier GNC Positive (+) input terminal (V IP1 ); transistor M P2 The source terminal is connected to transistor M P1 Source and switch S 55 One end of transistor M P2 The drain terminal is connected to the amplifier G NC Positive (+) output terminal (V OUTP1 ), transistor M P2 The gate terminal is connected to the amplifier G NC Negative (-) input terminal (V IN1 ); transistor M N1 The source terminal is connected to transistor M N2 Source and switch S 56 One end of transistor M N1 The drain terminal is connected to the amplifier G NC Negative (-) output terminal (V OUTN1 ), transistor M N1 The gate terminal is connected to the amplifier G NC Positive (+) input terminal (V IP1 ); transistor M N2 The source terminal is connected to transistor M N1 Source and switch S 56 One end of transistor M N2 The drain terminal is connected to the amplifier G NC Positive (+) output terminal (V OUTP1 ), transistor M N2 The gate terminal is connected to the amplifier G NC Negative (-) input terminal (V IN1 ).

[0026] Its workflow is:

[0027] ① When it is in the reset stage, the energy storage capacitor C RSV1 Charging;

[0028] ② When it is in the amplification stage, the power supply is disconnected and supplied through the energy storage capacitor to make the open-loop FIA in a dynamic working condition, and its characteristic of no static current is used to achieve low power consumption.

[0029] During the extraction phase of the SNC noise cancellation process, the input signal and sampled noise voltage are measured by V DACP and V DACN Port passes to amplifier G NC At the input end, the input signal and the sampling noise voltage are NC Amplified and stored in capacitor C SNCN , C SNCP middle;

[0030] During the elimination phase of the SNC noise elimination process, the capacitor CSNCN , C SNCP With C SUMN , C SUMP Charge sharing is performed to transfer the sampled noise voltage to capacitor C SUMN , C SUMP and the capacitor C SUMN , C SUMP The sampling noise voltage and V DACP 、V DACN The sampling noise voltage introduced into the port has opposite polarity and can be cancelled.

[0031] The residual amplifier circuit includes a closed-loop cascode FIA, switches, and capacitors. During its operation, the circuit of the cascode FIA ​​is as follows: Figure 3 As shown, M N3 、M N4 、M P3 、M P4 As an input tube, it realizes the function of inverting and amplifying the input signal. RSV2 As an energy storage capacitor, it provides energy during the amplification stage. The cascode FIA ​​is constructed by adding a cascode transistor M N5 、M N6 、M P5 、M P6 To increase the output impedance to achieve high DC gain, the cascode FIA ​​is used as an amplifier in a closed-loop structure to reduce the static gain error. Its working process is the same as that of the open-loop FIA.

[0032] The amplifier G circuit consists of switch S 57 ~S 60 , capacitor C RSV2 , transistor M N3 、M N4 、M P3 、M P4 and transistor M N5 、M N6 、M P5 、M P6 .

[0033] The switch S 57 One end is connected to the power supply V DD , the other end is connected to the switch S 59 And the capacitor C RSV2 One end of switch S 58 One end is connected to ground GND, and the other end is connected to the switch S 60 And the capacitor C RSV2 One end of switch S 59 One end of the switch S 57 And the capacitor C RSV2 One end is connected to transistor MP3 The source terminal and transistor M P4 Source end; switch S 60 One end of the switch S 58 And the capacitor C RSV2 One end is connected to transistor M N3 The source terminal and transistor M N4 Source terminal; transistor M P3 The source terminal is connected to transistor M P4 Source and switch S 59 One end of transistor M P3 The drain terminal is connected to transistor M P5 Source terminal, transistor M P3 The gate terminal is connected to the positive (+) input terminal of amplifier G (V IP2 ); transistor M P4 The source terminal is connected to transistor M P3 Source and switch S 59 One end of transistor M P4 The drain terminal is connected to transistor M P6 Source terminal, transistor M P4 The gate terminal is connected to the negative (-) input terminal of the amplifier G (V IN2 ); transistor M N3 The source terminal is connected to transistor M N4 Source and switch S 60 One end of transistor M N3 The drain terminal is connected to transistor M N5 Source terminal, transistor M N3 The gate terminal is connected to the positive (+) input terminal of amplifier G (V IP2 ); transistor M N4 The source terminal is connected to transistor M N3 Source and switch S 60 One end of transistor M N4 The drain terminal is connected to transistor M N6 Source terminal, transistor M N4 The gate terminal is connected to the negative (-) input terminal of the amplifier G (V IN2 ); transistor M P5 The source terminal is connected to transistor M P3 Drain terminal, transistor M P5 The drain terminal is connected to the negative (-) output terminal of amplifier G (V OUTN2 ), transistor M P5 Gate terminal connected to port V CM ; Transistor M P6 The source terminal is connected to transistor M P4 Drain terminal, transistor M P6 The drain terminal is connected to the positive (+) output terminal of amplifier G (V OUTP2 ), transistor M P6 Gate terminal connected to port V CM; Transistor M N5 The source terminal is connected to transistor M N3 Drain terminal, transistor M N5 The drain terminal is connected to the negative (-) output terminal of amplifier G (V OUTN2 ), transistor M N5 Gate terminal connected to port V CM ; Transistor M N6 The source terminal is connected to transistor M N4 Drain terminal, transistor M N6 The drain terminal is connected to the positive (+) output terminal of amplifier G (V OUTP2 ), transistor M N6 Gate terminal connected to port V CM .

[0034] The voltage signal of the CIFF noise shaping loop is V OP and V ON , the output is V P and V N ;CIFF noise shaping loop is capacitor C RESN , C RESP , C INT1N , C INT1P , C INT2_1 , C INT2_2 , C INT2_3 , C INT2_4 The second-order passive IIR filter formed by each switch;

[0035] The workflow of the CIFF noise shaping loop is as follows:

[0036] ①Switch S 31 , S 32 , S 37 , S 38 Closed, switch S 31 , S 32 , S 37 , S 38 The remaining switches of the module to which it belongs are disconnected, and the amplified residual voltage is stored in the capacitor C RESN , C RESP superior;

[0037] ②Switch S 33 , S 34 , S 35 , S 36 Closed, switch S 33 , S 34 , S 35 , S 36 The remaining switches of the module to which it belongs are disconnected, and the capacitor C RESN , C RESP and C INT1N , CINT1P Charge sharing between them realizes the first level integration;

[0038] ③Switch S 31 , S 32 , S 40 , S 42 , S 43 , S 45 , S 47 , S 49 , S 50 , S 52 Closed, switch S 31 , S 32 , S 40 , S 42 , S 43 , S 45 , S 47 , S 49 , S 50 , S 52 The remaining switches of the module to which it belongs are disconnected, and the capacitor C INT2_1 , C INT2_2 , C INT2_3 , C INT2_4 Connected in parallel with capacitor C RESN , C RESP Charge sharing is performed in a fully differential circuit to achieve second-level integration;

[0039] ④Switch S 39 , S 41 , S 44 , S 46 , S 48 , S 51 Closed, the other switches are open, and the capacitor C INT2_1 , C INT2_2 Then connect in series to V P Terminal, capacitor C INT2_3 , C INT2_4 Then connect in series to V N terminal to amplify the second stage integrated voltage by four times, and at the same time, the capacitor C INT1P , C INT2_1 , C INT2_2 Series, capacitor C INT1N , C INT2_3 , C INT2_4 connected in series, so the first and second stage integrated voltages are both connected through V P and V N Passed back to the SAR ADC.

[0040] The voltage signal of the EF noise shaping loop is V OP and V ON , the output is V DACP and VDACN EF noise shaping loop has capacitors C with the same capacitance value FIR1N , C FIR1P , C FIR2N , C FIR2P , C DELN , C DELP It is composed of a second-order passive finite impulse response filter FIR (finite impulse response, FIR) composed of each switch;

[0041] The working process of the EF noise shaping loop is as follows:

[0042] ①Switches S1 and S2 are closed, and the other switches are open. DELN , C DELP Reset;

[0043] ②Switches S5 and S6 are closed, and the other switches are open, capacitor C FIR2N , C FIR2P The voltage stored in the previous cycle, which is the residual voltage amplified by the residual amplifier in the previous cycle, is transferred to the capacitor C through charge sharing. DELN , C DELP superior;

[0044] ③Switch S7, S8, S 11 , S 12 The remaining switches are closed and the residual voltage of the previous cycle amplified by the residual amplifier is stored in the capacitor C FIR1N , C FIR1P and C FIR2N , C FIR2P superior;

[0045] ④Switch S3, S4, S9, S 10 Close, the other switches are open, follow Figure 1 The connection relationship in part a is that the capacitor C FIR1N , C FIR1P and C DELN , C DELP The voltage on the V DACP and V DACN port.

[0046] The present invention proposes a novel hybrid nested noise shaping architecture suitable for noise shaping SAR ADC, which adopts a closed-loop common source and common gate FIA ​​as a residual amplifier and uses CIFF and EF as a noise shaping loop to solve the problem that traditional noise shaping SAR ADC is difficult to achieve high precision and low power consumption at the same time. In addition, sampling KT / C noise cancellation (SNC) technology is also integrated to reduce the capacitance of the sampling capacitor and save chip area:

[0047] The present invention is an innovation for the noise shaping architecture and can be applied to the noise shaping SAR ADC. The present invention has the advantages of the traditional noise shaping architecture and improves the accuracy while maintaining low power consumption. Therefore, it can be used for noise shaping SAR ADC to sample and quantize weak signals, such as temperature signals, biological signals, and weak current signals. The noise shaping SAR ADC using the noise shaping architecture can be applied to the fields of precision data acquisition systems, communication systems, medical equipment, audio signal processing, and image sensors.

[0048] The present invention is an innovative optimization of the noise shaping architecture. The fourth-order noise shaping of the SAR ADC is realized through the novel architecture. The architecture adopts a closed-loop common source and common gate FIA ​​as a residual amplifier, and achieves high precision while maintaining low power consumption. A sampling noise cancellation (SNC) module is integrated in the architecture. Under the same accuracy requirements, the ADC is allowed to use a smaller sampling capacitor, reducing the area overhead, and making the ADC easier to be driven by the front-stage circuit. The present invention is compatible with multiple mainstream integrated circuit design platforms such as Cadence, Pspice, and Hspice.

[0049] The architecture of the present invention has the following advantages:

[0050] (1) The novel hybrid nested noise shaping architecture of the present invention can achieve fourth-order noise shaping through CIFF and EF noise shaping loops, and can achieve higher accuracy at the same oversampling ratio (OSR);

[0051] (2) The closed-loop cascode FIA ​​in the novel hybrid nested noise shaping architecture of the present invention works dynamically, without the static current in the traditional amplifier, which can effectively reduce power consumption;

[0052] (3) In the architecture of the present invention, compared with the open-loop FIA, the output linearity of the closed-loop cascode FIA ​​is improved and is not limited by the output load capacitance, further optimizing the accuracy;

[0053] (4) The closed-loop cascode FIA ​​has good PVT robustness and does not require any gain calibration circuit, further reducing power consumption.

[0054] The advantages of the present invention also lie in:

[0055] (1) High precision: SAR ADC can achieve fourth-order noise shaping through this new hybrid nested noise shaping architecture, achieving higher precision under the same OSR. At the same time, since the closed-loop common source and common gate FIA ​​is used as the residual amplifier in this noise shaping architecture, it is not limited by the trade-off between the output load capacitance and the output linearity. Therefore, the overall KT / C noise can be reduced by increasing the load capacitance, thereby achieving a high-precision SAR ADC;

[0056] (2) Low power consumption: This new hybrid nested noise shaping architecture adopts full dynamic operation and does not use any modules that consume static current. In addition, the closed-loop cascode FIA ​​adopted does not require additional gain calibration circuits. Therefore, the ADC has the characteristics of low power consumption;

[0057] (3) Good PVT robustness: Since a closed-loop cascode FIA ​​is used as the residual amplifier, its gain has good PVT robustness, so that the noise transfer function (NTF) of the hybrid nested noise shaping architecture also has good PVT robustness. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0059] Attached Figure 1 It is the novel hybrid nested noise shaping architecture described in the present invention (part a is the top-level circuit diagram, and part b is the corresponding timing diagram of each switch control signal);

[0060] Attached Figure 2 is an open loop FIA amplifier ( Figure 1 Medium G NC ) circuit diagram;

[0061] Attached Figure 3 It is a common source and common gate FIA ​​amplifier ( Figure 1 G) is a circuit diagram. DETAILED DESCRIPTION

[0062] As shown in the figure, a new hybrid nested noise shaping architecture suitable for noise shaping SAR ADC is characterized in that: the shaping architecture adopts a dynamically operating closed-loop common-source and common-gate FIA ​​as a residual amplifier to reduce power consumption by eliminating the quiescent current of the amplifier and removing the gain calibration circuit; the shaping architecture performs fourth-order noise shaping through nested second-order CIFF and second-order EF noise shaping loops to achieve high accuracy when shaping noise at the same oversampling rate, and the shaping architecture reduces the capacitance of the sampling capacitor by integrating a sampling noise cancellation (sampling KT / C noise cancellation, SNC) method to save chip area.

[0063] The top-level circuit of the shaping architecture is as follows Figure 1 As shown in part a of FIG. 1 , it includes a CIFF noise shaping loop CIFF loop, an EF noise shaping loop EF loop, a residual amplifier (ResidueAmplifier) ​​and a sampling noise elimination module SNC; the top circuit is connected through port V DACN 、V DACP Connected to the capacitive digital-to-analog converter CDAC (capacitive digital-to-analog converter, CDAC) of the SAR ADC through port V P 、V N Connected to the comparator of SAR ADC.

[0064] The noise source and noise shaping implementation flow of the nested noise shaping architecture is as follows:

[0065] (1) The noise sources processed by the noise shaping architecture mainly include two parts:

[0066] ① SAR ADC will generate quantization noise after completing one quantization, and the quantization noise is evenly distributed in the range from 0Hz to half the sampling frequency;

[0067] ② The sampling noise generated when the SAR ADC samples the input signal. The quantization noise and sampling noise of the SAR ADC are both transmitted through port V DACP and V DACN Passed into the noise shaping architecture.

[0068] (2) The noise shaping implementation process is as follows. ① First, after the SAR ADC samples the input signal, the sampling noise passes through port V DACP and V DACN② The quantization noise generated by the SAR ADC is extracted and amplified by the residual amplifier after the SAR ADC completes the quantization process of the current cycle; ③ After that, the amplified quantization noise is simultaneously transmitted to the CIFF noise shaping loop and the EF noise shaping loop. The CIFF noise shaping loop and the EF noise shaping loop perform high-pass filtering on the quantization noise, so that the low-frequency (within the signal bandwidth frequency range) quantization noise is suppressed. ④ Finally, the filtered quantization noise is transmitted through port V P 、V N 、V DACP 、V DACN It is then transmitted back to the SAR ADC and participates in the quantization process of the next cycle. At this time, the influence of quantization noise within the signal bandwidth frequency range will be suppressed, and the effect of noise shaping is finally achieved.

[0069] Specific circuit components are connected as follows Figure 1 to Figure 3 As shown. The top circuit consists of switches S1 to S 52 , capacitor C DELN , capacitor C DELP , capacitor C FIR1N , capacitor C FIR1P , capacitor C FIR2N , capacitor C FIR2P , capacitor C EXAN , capacitor C EXAP , capacitor C SUMN , capacitor C SUMP , capacitor C SNCN , capacitor C SNCP , capacitor C INT1N , capacitor C INT1P , capacitor C RESN , capacitor C RESP , capacitor C INT2_1 , capacitor C INT2_2 , capacitor C INT2_3 , capacitor C INT2_4 and amplifier G, amplifier G NC One end of the switch S1 is connected to port V CM The other end is connected to switch S3, switch S5 and capacitor C DELP One end of switch S2 is connected to port V CM The other end is connected to switch S4, switch S6 and capacitor C DELN One end of switch S3 is connected to port V DACP The other end is connected to switch S1, switch S5 and capacitor C DELP One end of switch S4 is connected to port V DACN The other end is connected to switch S2, switch S6 and capacitor C DELNOne end of the switch S5 is connected to the switch S7 and the capacitor C FIR2P One end of the switch S1, the other end of the switch S3 and the capacitor C DELP One end of the switch S6 is connected to the switch S8 and the capacitor C FIR2N One end of the switch S2, the other end of the switch S4 and the capacitor C DELN One end of switch S7 is connected to port V ON , the other end is connected to switch S5 and capacitor C FIR2P One end of switch S8 is connected to port V OP , the other end is connected to switch S6 and capacitor C FIR2N One end of switch S9 is connected to port V DACP , the other end is connected to the switch S 11 And the capacitor C FIR1P One end of switch S 10 Connect one end of the port V DACN , the other end is connected to the switch S 12 And the capacitor C FIR1N One end of switch S 11 Connect one end of the port V OP , the other end is connected to switch S9 and capacitor C FIR1P One end of switch S 12 Connect one end of the port V ON , the other end is connected to the switch S 10 And the capacitor C FIR1N One end of switch S 13 Connect one end of the port V CM , the other end is connected to port V ON ; Switch S 14 Connect one end of the port V CM , the other end is connected to port V OP ; Switch S 15 Connect one end of the port V DACP , and the other end is connected to the positive (+) input terminal (V IP2 ), switch S 17 And the capacitor C EXAP One end of switch S 16 Connect one end of the port V DACN The other end is connected to the negative (-) input terminal of amplifier G (V IN2 ), switch S 18 And the capacitor C EXAN One end of switch S 17 One end is connected to the positive (+) input terminal (V IP2 ), switch S 15 And the capacitor C EXAPOne end is connected to port V CM ; Switch S 18 One end is connected to the negative (-) input terminal (V IN2 ), switch S 16 And the capacitor C EXAN , the other end is connected to port V CM ; Switch S 19 Connect one end of the port V DACP , the other end is connected to port V CM ; Switch S 20 Connect one end of the port V DACN , the other end is connected to port V CM ; Switch S 21 One end of the node is connected to node ① (such as Figure 1 The other end is connected to port V CM ; Switch S 22 One end is connected to node ②, and the other end is connected to port V CM ; Switch S 23 Connect one end of the port V DACP , the other end is connected to the switch S 27 And the capacitor C SNCP One end of switch S 24 Connect one end of the port V DACN , the other end is connected to the switch S 28 And the capacitor C SNCN One end of switch S 25 One end is connected to node ①, and the other end is connected to switch S 29 And the capacitor C SNCP One end of switch S 26 One end is connected to node ②, and the other end is connected to switch S 30 And the capacitor C SNCN One end of switch S 27 One end of the amplifier is connected to G NC The positive (+) output terminal (V OUTP1 ), the other end is connected to the switch S 23 And the capacitor C SNCP One end of switch S 28 One end of the amplifier is connected to G NC The negative (-) output terminal (V OUTN1 ), the other end is connected to the switch S 24 And the capacitor C SNCN One end of switch S 29 Connect one end of the port V CM , the other end is connected to the switch S 25 And the capacitor C SNCP One end of switch S30 Connect one end of the port V CM , the other end is connected to the switch S 26 And the capacitor C SNCN One end of switch S 31 Connect one end of the port V CM , the other end is connected to the switch S 33 And the capacitor C RESP One end of switch S 32 Connect one end of the port V CM , the other end is connected to the switch S 34 And the capacitor C RESN One end of switch S 33 One end is connected to node ①, and the other end is connected to switch S 31 And the capacitor C RESP One end of switch S 34 One end is connected to node ②, and the other end is connected to switch S 32 And the capacitor C RESN One end of switch S 35 One end is connected to node ③, and the other end is connected to switch S 39 And the capacitor C INT1P One end of switch S 36 One end is connected to node ④, and the other end is connected to switch S 46 And the capacitor C INT1N One end of switch S 37 One end is connected to node ③, and the other end is connected to port V OP ; Switch S 38 One end is connected to node ④, and the other end is connected to port V ON ; Switch S 39 One end of the switch S 35 And the capacitor C INT1P One end of the switch S 42 And the capacitor C INT2_1 One end of switch S 40 One end is connected to node ③, and the other end is connected to switch S 41 And the capacitor C INT2_1 One end of switch S 41 One end of the switch S 40 And the capacitor C INT2_1 One end of the switch S 45 And the capacitor C INT2_2 One end of switch S 42 One end is connected to node ④, and the other end is connected to switch S 39 And the capacitor C INT2_1 One end of switch S 43 One end is connected to node ③, and the other end is connected to switch S44 And the capacitor C INT2_2 One end of switch S 44 Connect one end of the port V P , the other end is connected to the switch S 43 And the capacitor C INT2_2 One end of switch S 45 One end is connected to node ④, and the other end is connected to switch S 41 And the capacitor C INT2_2 One end of switch S 46 One end of the switch S 36 And the capacitor C INT1N One end of the switch S 47 And the capacitor C INT2_3 One end of switch S 47 One end is connected to node ③, and the other end is connected to switch S 46 And the capacitor C INT2_3 One end of switch S 48 One end of the switch S 49 And the capacitor C INT2_3 One end of the switch S 50 And the capacitor C INT2_4 One end of switch S 49 One end is connected to node ④, and the other end is connected to switch S 48 And the capacitor C INT2_3 One end of switch S 50 One end is connected to node ③, and the other end is connected to switch S 48 And the capacitor C INT2_4 One end of switch S 51 Connect one end of the port V N , the other end is connected to the switch S 52 And the capacitor C INT2_4 One end of switch S 52 One end is connected to node ④, and the other end is connected to switch S 51 And the capacitor C INT2_4 One end of the capacitor C DELN Connect one end of the port V CM , the other end is connected to one end of switch S2, switch S4 and switch S6; capacitor C DELN Connect one end of the port V CM , the other end is connected to one end of switch S1, switch S3 and switch S5; capacitor C FIR1N Connect one end of the port V CM , the other end is connected to the switch S 10 And switch S 12 One end of the capacitor C FIR1P Connect one end of the port V CM, the other end is connected to switch S9 and switch S 11 One end of the capacitor C FIR2N Connect one end of the port V CM , the other end is connected to switch S6 and one end of switch S8; capacitor C FIR2P Connect one end of the port V CM , the other end is connected to switch S5 and one end of switch S7; capacitor C EXAN Connect one end of the port V OP The other end is connected to the negative (-) input terminal of amplifier G (V IN2 ), switch S 16 And switch S 18 One end of the capacitor C EXAP Connect one end of the port V ON , and the other end is connected to the positive (+) input terminal (V IP2 ), switch S 15 And switch S 17 One end of the capacitor C SUMN Connect one end of the port V DACN , the other end is connected to node ②; capacitor C SUMP Connect one end of the port V DACP , the other end is connected to node ①; capacitor C SNCN One end of the switch S 24 And switch S 28 One end of the switch S 26 And switch S 30 One end of the capacitor C SNCP One end of the switch S 23 And switch S 27 One end of the switch S 25 And switch S 29 One end of the capacitor C INT1N One end is connected to node ②, and the other end is connected to switch S 36 And switch S 46 One end of the capacitor C INT1P One end is connected to node ①, and the other end is connected to switch S 35 And switch S 39 One end of the capacitor C RESN One end is connected to node ④, and the other end is connected to switch S 32 And switch S 34 One end of the capacitor C RESP One end is connected to node ③, and the other end is connected to switch S 31 And switch S 33 One end of the capacitor C INT2_1 One end of the switch S 39 And switch S42 One end of the switch S 40 And switch S 41 One end of the capacitor C INT2_2 One end of the switch S 41 And switch S 45 One end of the switch S 43 And switch S 44 One end of the capacitor C INT2_3 One end of the switch S 46 And switch S 47 One end of the switch S 48 And switch S 49 One end of the capacitor C INT2_4 One end of the switch S 48 And switch S 50 One end of the switch S 51 And switch S 52 One end of the amplifier G's positive (+) input (V IP2 )Connect switch S 15 , switch S 17 And the capacitor C EXAP One end, negative (-) input terminal (V IN2 )Connect switch S 16 , switch S 18 And the capacitor C EXAN One end, positive output end (V OUTP2 ) Connect port V OP , negative (-) output terminal (V OUTN2 ) Connect port V ON ; Amplifier G NC The positive (+) input terminal (V IP1 ) connects to node ①, the negative (-) input terminal (V IN1 ) connects to node ②, the positive output terminal (V OUTP1 )Connect switch S 27 One end, negative (-) output end (V OUTN1 )Connect switch S 28 one end.

[0070] The noise shaping process of the shaping architecture is as follows: First, the SAR ADC sampling noise voltage is passed through V DACP and V DACN The port is passed to the SNC circuit to be offset, and then the residual voltage of the current cycle obtained after quantization of the SAR ADC is input into the hybrid nested noise shaping architecture, amplified by the residual amplifier, and then the amplified residual voltage is input into the CIFF and EF noise shaping loops respectively; finally, the output voltages of the CIFF and EF noise shaping loops are respectively output through VP 、V N and V DACP 、V DACN The port is transmitted back to the SAR ADC to implement the noise shaping function.

[0071] The residual amplifier input voltage signal is V DACP and V DACN , the output is V OP and V ON After the input signal is quantized by the SARADC, the residual voltage of the current cycle is obtained, which is amplified by the residual amplifier and input into the CIFF and EF noise shaping loops.

[0072] The SNC circuit is independent of the rest of the hybrid nested noise shaping architecture, which includes a plurality of capacitors and switches;

[0073] In the sampling noise elimination module SNC part of the shaping architecture, if the sampling KT / C noise cannot be shaped, it will all be passed to the output end, and a large sampling capacitor will be used to reduce the sampling KT / C noise. By using SNC technology to reduce the sampling KT / C noise, a smaller sampling capacitor can be used under the same accuracy requirements, reducing the area overhead of the circuit and making the ADC easier to be driven by the previous circuit; the working process of SNC includes the extraction stage and the elimination stage.

[0074] The SNC circuit uses an amplifier G NC ( Figure 1 Indicated as G NC ) adopts an open-loop FIA architecture, and its circuit is as follows Figure 2 As shown, M N1 、M N2 、M P1 、M P2 As an input tube, it realizes the function of inverting and amplifying the input signal. RSV1 As an energy storage capacitor, it realizes the function of providing energy during the amplification stage.

[0075] Assume M N× Both represent N-type metal-oxide-semiconductor field-effect transistor MOS, M P× All represent P-type metal-oxide-semiconductor field-effect transistors MOS, where × represents any number, then in the SNC circuit, M N1 、M N2 、M P1 、M P2 As an input tube, it can realize the function of inverting and amplifying the input signal. RSV1 As an energy storage capacitor, it provides energy during the amplification stage;

[0076] Amplifier G NC The circuit consists of switch S 53 ~S 56 , capacitor C RSV1 and transistor M N1 , transistor M N2 , transistor M P1 , transistor M P2 . The switch S 53 One end is connected to the power supply V DD , the other end is connected to the switch S 55 And the capacitor C RSV1 One end of switch S 54 One end is connected to ground GND, and the other end is connected to the switch S 56 And the capacitor C RSV1 One end of switch S 55 One end of the switch S 53 And the capacitor C RSV1 One end is connected to transistor M P1 The source terminal and transistor M P2 Source end; switch S 56 One end of the switch S 54 And the capacitor C RSV1 One end is connected to transistor M N1 The source terminal and transistor M N2 Source terminal; transistor M P1 The source terminal is connected to transistor M P2 Source and switch S 55 One end of transistor M P1 The drain terminal is connected to the amplifier G NC Negative (-) output terminal (V OUTN1 ), transistor M P1 The gate terminal is connected to the amplifier G NC Positive (+) input terminal (V IP1 ); transistor M P2 The source terminal is connected to transistor M P1 Source and switch S 55 One end of transistor M P2 The drain terminal is connected to the amplifier G NC Positive (+) output terminal (V OUTP1 ), transistor M P2 The gate terminal is connected to the amplifier G NC Negative (-) input terminal (V IN1 ); transistor M N1 The source terminal is connected to transistor M N2 Source and switch S 56 One end of transistor M N1 The drain terminal is connected to the amplifier G NC Negative (-) output terminal (V OUTN1), transistor M N1 The gate terminal is connected to the amplifier G NC Positive (+) input terminal (V IP1 ); transistor M N2 The source terminal is connected to transistor M N1 Source and switch S 56 One end of transistor M N2 The drain terminal is connected to the amplifier G NC Positive (+) output terminal (V OUTP1 ), transistor M N2 The gate terminal is connected to the amplifier G NC Negative (-) input terminal (V IN1 ).

[0077] Its workflow is:

[0078] ① When it is in the reset stage, the energy storage capacitor C RSV1 Charging;

[0079] ② When it is in the amplification stage, the power supply is disconnected and supplied through the energy storage capacitor to make the open-loop FIA in a dynamic working condition, and its characteristic of no static current is used to achieve low power consumption.

[0080] During the extraction phase of the SNC noise cancellation process, the input signal and sampled noise voltage are measured by V DACP and V DACN Port passes to amplifier G NC At the input end, the input signal and the sampling noise voltage are NC Amplified and stored in capacitor C SNCN , C SNCP middle;

[0081] During the elimination phase of the SNC noise elimination process, the capacitor C SNCN , C SNCP With C SUMN , C SUMP Charge sharing is performed to transfer the sampled noise voltage to capacitor C SUMN , C SUMP and the capacitor C SUMN , C SUMP The sampling noise voltage and V DACP 、V DACN The sampling noise voltage introduced into the port has opposite polarity and can be cancelled.

[0082] The residual amplifier circuit includes a closed-loop cascode FIA, switches, and capacitors. During its operation, the circuit of the cascode FIA ​​is as follows: Figure 3 As shown, M N3 、M N4 、M P3 、MP4 As an input tube, it realizes the function of inverting and amplifying the input signal. RSV2 As an energy storage capacitor, it provides energy during the amplification stage. The cascode FIA ​​is constructed by adding a cascode transistor M N5 、M N6 、M P5 、M P6 To increase the output impedance to achieve high DC gain, the cascode FIA ​​is used as an amplifier in a closed-loop structure to reduce the static gain error. Its working process is the same as that of the open-loop FIA.

[0083] The amplifier G circuit consists of switch S 57 ~S 60 , capacitor C RSV2 , transistor M N3 、M N4 、M P3 、M P4 and transistor M N5 、M N6 、M P5 、M P6 . The switch S 57 One end is connected to the power supply V DD , the other end is connected to the switch S 59 And the capacitor C RSV2 One end of switch S 58 One end is connected to ground GND, and the other end is connected to the switch S 60 And the capacitor C RSV2 One end of switch S 59 One end of the switch S 57 And the capacitor C RSV2 One end is connected to transistor M P3 The source terminal and transistor M P4 Source end; switch S 60 One end of the switch S 58 And the capacitor C RSV2 One end is connected to transistor M N3 The source terminal and transistor M N4 Source terminal; transistor M P3 The source terminal is connected to transistor M P4 Source and switch S 59 One end of transistor M P3 The drain terminal is connected to transistor M P5 Source terminal, transistor M P3 The gate terminal is connected to the positive (+) input terminal of amplifier G (V IP2 ); transistor M P4 The source terminal is connected to transistor M P3 Source and switch S 59 One end of transistor MP4 The drain terminal is connected to transistor M P6 Source terminal, transistor M P4 The gate terminal is connected to the negative (-) input terminal of the amplifier G (V IN2 ); transistor M N3 The source terminal is connected to transistor M N4 Source and switch S 60 One end of transistor M N3 The drain terminal is connected to transistor M N5 Source terminal, transistor M N3 The gate terminal is connected to the positive (+) input terminal of amplifier G (V IP2 ); transistor M N4 The source terminal is connected to transistor M N3 Source and switch S 60 One end of transistor M N4 The drain terminal is connected to transistor M N6 Source terminal, transistor M N4 The gate terminal is connected to the negative (-) input terminal of the amplifier G (V IN2 ); transistor M P5 The source terminal is connected to transistor M P3 Drain terminal, transistor M P5 The drain terminal is connected to the negative (-) output terminal of amplifier G (V OUTN2 ), transistor M P5 Gate terminal connected to port V CM ; Transistor M P6 The source terminal is connected to transistor M P4 Drain terminal, transistor M P6 The drain terminal is connected to the positive (+) output terminal of amplifier G (V OUTP2 ), transistor M P6 Gate terminal connected to port V CM ; Transistor M N5 The source terminal is connected to transistor M N3 Drain terminal, transistor M N5 The drain terminal is connected to the negative (-) output terminal of amplifier G (V OUTN2 ), transistor M N5 Gate terminal connected to port V CM ; Transistor M N6 The source terminal is connected to transistor M N4 Drain terminal, transistor M N6 The drain terminal is connected to the positive (+) output terminal of amplifier G (V OUTP2 ), transistor M N6 Gate terminal connected to port V CM .

[0084] The voltage signal of the CIFF noise shaping loop is V OP and V ON , the output is V P and VN ;CIFF noise shaping loop is capacitor C RESN , C RESP , C INT1N , C INT1P , C INT2_1 , C INT2_2 , C INT2_3 , C INT2_4 The second-order passive IIR filter formed by each switch;

[0085] The workflow of the CIFF noise shaping loop is as follows:

[0086] ①Switch S 31 , S 32 , S 37 , S 38 Closed, switch S 31 , S 32 , S 37 , S 38 The remaining switches of the module to which it belongs are disconnected, and the amplified residual voltage is stored in the capacitor C RESN , C RESP superior;

[0087] ②Switch S 33 , S 34 , S 35 , S 36 Closed, switch S 33 , S 34 , S 35 , S 36 The remaining switches of the module to which it belongs are disconnected, and the capacitor C RESN , C RESP and C INT1N , C INT1P Charge sharing between them realizes the first level integration;

[0088] ③Switch S 31 , S 32 , S 40 , S 42 , S 43 , S 45 , S 47 , S 49 , S 50 , S 52 Closed, switch S 31 , S 32 , S 40 , S 42 , S 43 , S 45 , S 47 , S 49 , S 50 , S 52The remaining switches of the module to which it belongs are disconnected, and C INT2_1 , C INT2_2 , C INT2_3 , C INT2_4 Connect in parallel with C RESN , C RESP Charge sharing is performed in a fully differential circuit to achieve second-level integration;

[0089] ④Switch S 39 , S 41 , S 44 , S 46 , S 48 , S 51 Closed, the other switches are open, and the capacitor C INT2_1 , C INT2_2 Then connect in series to V P Terminal, capacitor C INT2_3 , C INT2_4 Then connect in series to V N terminal to amplify the second stage integrated voltage by four times, and at the same time, the capacitor C INT1P , C INT2_1 , C INT2_2 Series, capacitor C INT1N , C INT2_3 , C INT2_4 connected in series, so the first and second stage integrated voltages are both connected through V P and V N Passed back to the SAR ADC.

[0090] The voltage signal of the EF noise shaping loop is V OP and V ON , the output is V DACP and V DACN EF noise shaping loop has capacitors C with the same capacitance value FIR1N , C FIR1P , C FIR2N , C FIR2P , C DELN , C DELP It is composed of a second-order passive finite impulse response filter FIR (finite impulse response, FIR) composed of each switch;

[0091] The working process of the EF noise shaping loop is as follows:

[0092] ①Switches S1 and S2 are closed, and the other switches are open. DELN , C DELP Reset;

[0093] ②Switches S5 and S6 are closed, and the other switches are open, capacitor C FIR2N , CFIR2P The voltage stored in the previous cycle, which is the residual voltage amplified by the residual amplifier in the previous cycle, is transferred to the capacitor C through charge sharing. DELN , C DELP superior;

[0094] ③Switch S7, S8, S 11 , S 12 The remaining switches are closed and the residual voltage of the previous cycle amplified by the residual amplifier is stored in the capacitor C FIR1N , C FIR1P and C FIR2N , C FIR2P superior;

[0095] ④Switch S3, S4, S9, S 10 Close, the other switches are open, follow Figure 1 The connection relationship in part a is that the capacitor C FIR1N , C FIR1P and C DELN , C DELP The voltage on the DACP and V DACN port.

[0096] Example:

[0097] In this example, the top-level circuit of the novel hybrid nested noise shaping architecture is as follows Figure 1 As shown in part a of FIG, it is composed of a CIFF noise shaping loop (CIFF loop), an EF noise shaping loop (EF loop), a residual amplifier (ResidueAmplifier) ​​and a sampling noise cancellation module (hereinafter referred to as SNC). DACN 、V DACP and V P 、V N These are ports connected to the capacitive digital-to-analog converter (CDAC) and comparator of the SAR ADC respectively.

[0098] The working sequence of the new hybrid nested noise shaping architecture is as follows: Figure 1 As shown in part b (in this example, Φ XX is the control signal of the switch, where XX " indicates the name of any signal. When Φ XX When the switch is high, Φ XX When it is low, the switch is off. Default and Φ XXThe switch opening and closing states represented by V are opposite. The control signals of all switches in the present invention are represented in the same way as above. The overall workflow of the architecture is as follows: First, the SAR ADC sampling noise voltage is passed through V DACP and V DACN The port is passed to the SNC circuit to be offset, and then the residual voltage of the current cycle obtained after quantization of the SAR ADC is input into the hybrid nested noise shaping architecture, amplified by the residual amplifier, and then the amplified residual voltage is input into the CIFF and EF noise shaping loops respectively; the output voltages of the CIFF and EF noise shaping loops are respectively output through V P 、V N and V DACP 、V DACN The port is transmitted back to the SAR ADC to implement the noise shaping function.

[0099] The detailed description of each module in the architecture is as follows:

[0100] (1) Sampling noise cancellation module SNC (its port V DACP and V DACN Both are bidirectional input and output ports). Since the sampling KT / C noise cannot be shaped, it will all be passed to the output end, so a larger sampling capacitor is required to reduce the sampling KT / C noise. By using SNC technology to reduce the sampling KT / C noise, a smaller sampling capacitor can be tolerated under the same accuracy requirements, reducing area overhead and making the ADC easier to be driven by the front-end circuit. The working process of SNC technology is divided into two stages: "extraction" and "elimination":

[0101] ① Extract. In switch S 19 , S 20 , S 21 , S 22 , S 23 , S 24 , S 25 , S 26 , S 53 , S 54 Disconnect, switch S 27 , S 28 , S 29 , S 30 , S 55 , S 56 During the closed period, the input signal and the sampled noise voltage pass through V DACP and V DACN Port passes to amplifier G NC At the input end, the input signal and the sampling noise voltage are NC Amplified and stored in capacitor C SNCN , C SNCP middle.

[0102] ② Eliminate. When switch S 19 , S 20 , S 21 , S 22 , S 27 , S 28 , S 29 , S 30 , S 55 , S 56 Disconnect, switch S 23 , S 24 , S 25 , S 26 , S 53 , S 54 When closed, the capacitor C SNCN , C SNCP With C SUMN , C SUMP Charge sharing is performed to transfer the sampled noise voltage to capacitor C SUMN , C SUMP and the capacitor C SUMN , C SUMP The sampling noise voltage and V DACP 、V DACN The sampling noise voltage transmitted by the port has reverse polarity and can be offset.

[0103] Amplifiers used in SNC circuits ( Figure 1 Indicated as G NC ) is an open-loop FIA, such as Figure 2 As shown, M N1 、M N2 、M P1 、M P2 As an input tube, it realizes the function of inverting and amplifying the input signal. RSV1 As an energy storage capacitor, it provides energy during the amplification phase. Its working process is as follows: ① When the switch S 53 , S 54 Closed, switch S 55 , S 56 When disconnected, it is in the reset stage, at which time the energy storage capacitor C RSV1 ②When switch S 53 , S 54 Disconnect, switch S 55 , S 56 When closed, it is in the amplification stage, at which time the power supply is disconnected and supplied through the energy storage capacitor. Therefore, the open-loop FIA works dynamically, has no static current, and has low power consumption characteristics.

[0104] (2) Residual amplifier (input is V DACP and V DACN , the output is V OPand V ON ). After the input signal is quantized by the SAR ADC, the residual voltage of the current cycle is obtained. This voltage is amplified by the residual amplifier and input into the CIFF and EF noise shaping loops. The residual amplifier circuit is composed of a closed-loop common-source common-gate FIA ​​( Figure 1 The working process is divided into two stages: ① Switch S7, S8, S 11 , S 12 , S 13 , S 14 , S 17 , S 18 , S 31 , S 32 , S 37 , S 38 , S 57 , S 58 Closed, the other switches are open, and the capacitor C FIR1N , C FIR1P , C FIR2N , C FIR2P , C RESN , C RESP One end is connected to V CM (ADC common mode voltage) reset; ②Switch S7, S8, S 11 , S 12 , S 15 , S 16 , S 31 , S 32 , S 37 , S 38 , S 59 , S 60 The remaining switches are closed and the residual amplifier realizes the amplification function and stores the amplified residual voltage in the capacitor C. FIR1N , C FIR1P , C FIR2N , C FIR2P , C RESN , C RESP middle.

[0105] Among them, the cascode FIA ​​( Figure 1 The circuit represented by G in Figure 3 As shown, M N3 、M N4 、M P3 、M P4 As an input tube, it realizes the function of inverting and amplifying the input signal. RSV2 As an energy storage capacitor, it provides energy during the amplification stage. The cascode FIA ​​is constructed by adding a cascode transistor (M N5 、M N6 、MP5 、M P6 ), increasing the output impedance, thus achieving high DC gain. Therefore, using the cascode FIA ​​as an amplifier in a closed-loop structure will reduce the static gain error. Its workflow is the same as that of the open-loop FIA and will not be repeated.

[0106] (3) CIFF noise shaping loop (input is V OP and V ON , the output is V P and V N ). The CIFF noise shaping loop is composed of capacitor C RESN , C RESP , C INT1N , C INT1P , C INT21 , C INT22 , C INT23 , C INT24 The second-order passive IIR filter formed by each switch is composed of the following working process: ① Switch S 31 , S 32 , S 37 , S 38 The remaining switches are closed and the amplified residual voltage is stored in the capacitor C RESN , C RESP Up; ②Switch S 33 , S 34 , S 35 , S 36 Closed, the other switches are open, and the capacitor C RESN , C RESP and C INT1N , C INT1P Charge sharing between the switches realizes the first level of integration; ③ Switch S 31 , S 32 , S 40 , S 42 , S 43 , S 45 , S 47 , S 49 , S 50 , S 52 Close, and the other switches are open, and the capacitor C INT2_1 , C INT2_2 , C INT2_3 , C INT2_4 Connected in parallel with capacitor C RESN , C RESP Charge sharing is performed in the fully differential circuit to achieve the second level of integration; ④ Switch S 39 , S 41 , S 44 , S 46 , S 48 , S51 Closed, the other switches are open, and the capacitor C INT2_1 , C INT2_2 Then connect in series to V P Terminal, capacitor C INT2_3 , C INT2_4 Then connect in series to V N terminal to amplify the second stage integrated voltage by four times, and at the same time, the capacitor C INT1P , C INT2_1 , C INT2_2 Series, capacitor C INT1N , C INT2_3 , C INT2_4 connected in series, so the first and second stage integrated voltages are both connected through V P and V N Passed back to the SAR ADC.

[0107] (4) EF noise shaping loop (input is V OP and V ON , the output is V DACP and V DACN EF noise shaping loop has capacitors C with the same capacitance value. FIR1N , C FIR1P , C FIR2N , C FIR2P , C DELN , C DELP The second-order passive finite impulse response (FIR) filter composed of the switches is as follows: ① Switches S1 and S2 are closed, and the other switches are open, which is connected to the capacitor C DELN , C DELP Reset; ②Switches S5 and S6 are closed, and the other switches are open, and capacitor C FIR2N , C FIR2P The voltage stored in the previous cycle (the residual voltage amplified by the residual amplifier in the previous cycle) is transferred to C through charge sharing. DELN , C DELP ③Switch S7, S8, S 11 , S 12 The remaining switches are closed and the residual voltage of the previous cycle amplified by the residual amplifier is stored in the capacitor C FIR1N , C FIR1P and C FIR2N , C FIR2P 4. Switches S3, S4, S9, S 10 Close, and the other switches are open, and the capacitor C FIR1N , C DELN and C FIR1P , C DELP The voltage on the DACNand V DACP port.

Claims

1. A novel hybrid nested noise shaping architecture for noise shaping SAR ADCs, characterized by: The shaping architecture adopts a dynamically working closed-loop common-source and common-gate FIA ​​as a residual amplifier to reduce power consumption by eliminating the quiescent current of the amplifier and removing the gain calibration circuit; the shaping architecture performs fourth-order noise shaping through nested second-order CIFF and second-order EF noise shaping loops to achieve high precision when shaping noise at the same oversampling rate, and the shaping architecture reduces the capacitance of the sampling capacitor by integrating a sampling noise elimination SNC method to save chip area.

2. The novel hybrid nested noise shaping architecture for noise shaping SAR ADC according to claim 1, characterized in that: The top-level circuit of the shaping architecture includes a CIFF noise shaping loop CIFF loop, an EF noise shaping loop EFloop, a residual amplifier and a sampling noise elimination module SNC; the top-level circuit is connected through a port V DACN 、V DACP Connected to the capacitive digital-to-analog converter CDAC of SARADC through port V P 、V N Connected to the comparator of SARADC.

3. The novel hybrid nested noise shaping architecture for noise shaping SAR ADC according to claim 2, characterized in that: The noise shaping process of the shaping architecture is as follows: First, the SARADC samples the noise voltage through V DACP and V DACN The port is passed to the SNC circuit to be offset, and then the residual voltage of the current cycle obtained after quantization of the SAR ADC is input into the hybrid nested noise shaping architecture, amplified by the residual amplifier, and then the amplified residual voltage is input into the CIFF and EF noise shaping loops respectively; finally, the output voltages of the CIFF and EF noise shaping loops are respectively output through V P 、V N and V DACP 、V DACN The port is transmitted back to the SARADC to realize the noise shaping function.

4. The novel hybrid nested noise shaping architecture for noise shaping SAR ADC according to claim 3, characterized in that: The residual amplifier input voltage signal is V DACP and V DACN , the output is V OP and V ON After the input signal is quantized by the SARADC, the residual voltage of the current cycle is obtained, which is amplified by the residual amplifier and input into the CIFF and EF noise shaping loops.

5. The novel hybrid nested noise shaping architecture for noise shaping SAR ADC according to claim 4, characterized in that: The SNC circuit is independent of the rest of the hybrid nested noise shaping architecture, which includes a plurality of capacitors and switches; In the sampling noise elimination module SNC part of the shaping architecture, if the sampling KT / C noise cannot be shaped, it will all be passed to the output end, and a large sampling capacitor will be used to reduce the sampling KT / C noise. By using SNC technology to reduce the sampling KT / C noise, a smaller sampling capacitor can be used under the same accuracy requirements, reducing the area overhead of the circuit and making the ADC easier to be driven by the previous circuit; the working process of SNC includes the extraction stage and the elimination stage.

6. The novel hybrid nested noise shaping architecture for noise shaping SAR ADC according to claim 5, characterized in that: The SNC circuit uses an amplifier G NC Adopt open-loop FIA architecture, set M N× Both represent N-type metal-oxide-semiconductor field-effect transistor MOS, M P× All represent P-type metal-oxide-semiconductor field-effect transistors MOS, where × represents any number, then in the SNC circuit, M N1 、M N2 、M P1 、M P2 As an input tube, it can realize the function of inverting and amplifying the input signal. RSV1 As an energy storage capacitor, it realizes the function of providing energy in the amplification stage; its working process is as follows: ① When it is in the reset stage, the energy storage capacitor C RSV1 Charging; ② When it is in the amplification stage, the power supply is disconnected and supplied through the energy storage capacitor to make the open-loop FIA in a dynamic working condition, and its characteristic of no static current is used to achieve low power consumption.

7. The novel hybrid nested noise shaping architecture for noise shaping SAR ADC according to claim 6, characterized in that: During the extraction phase of the SNC noise cancellation process, the input signal and sampled noise voltage are measured by V DACP and V DACN Port passes to amplifier G NC At the input end, the input signal and the sampling noise voltage are NC Amplified and stored in capacitor C SNCN , C SNCP middle; During the elimination phase of the SNC noise elimination process, the capacitor C SNCN , C SNCP With C SUMN , C SUMP Charge sharing is performed to transfer the sampled noise voltage to capacitor C SUMN , C SUMP and the capacitor C SUMN , C SUMP The sampling noise voltage and V DACP 、V DACN The sampling noise voltage introduced into the port has opposite polarity and can be cancelled.

8. The novel hybrid nested noise shaping architecture for noise shaping SAR ADC according to claim 6, characterized in that: The residual amplifier circuit includes a closed-loop cascode FIA, switches, and capacitors. In the working process, in the cascode FIA ​​circuit, M N3 、M N4 、M P3 、M P4 As an input tube, it realizes the function of inverting and amplifying the input signal. RSV2 As an energy storage capacitor, it provides energy during the amplification stage. The cascode FIA ​​is constructed by adding a cascode transistor M N5 、M N6 、M P5 、M P6 To increase the output impedance to achieve high DC gain, the cascode FIA ​​is used as an amplifier in a closed-loop structure to reduce the static gain error. Its working process is the same as that of the open-loop FIA.

9. The novel hybrid nested noise shaping architecture for noise shaping SAR ADC according to claim 8, characterized in that: The voltage signal of the CIFF noise shaping loop is V OP and V ON , the output is V P and V N ;CIFF noise shaping loop is capacitor C RESN , C RESP , C INT1N , C INT1P , C INT2_1 , C INT2_2 , C INT2_3 , C INT2_4 The second-order passive IIR filter formed by each switch; The workflow of the CIFF noise shaping loop is as follows: ①Switch S 31 , S 32 , S 37 , S 38 Closed, switch S 31 , S 32 , S 37 , S 38 The remaining switches of the module to which it belongs are disconnected, and the amplified residual voltage is stored in the capacitor C RESN , C RESP superior; ②Switch S 33 , S 34 , S 35 , S 36 Closed, switch S 33 , S 34 , S 35 , S 36 The remaining switches of the module to which it belongs are disconnected, and the capacitor C RESN , C RESP and C INT1N , C INT1P Charge sharing between them realizes the first level integration; ③Switch S 31 , S 32 , S 40 , S 42 , S 43 , S 45 , S 47 , S 49 , S 50 , S 52 Closed, switch S 31 , S 32 , S 40 , S 42 , S 43 , S 45 , S 47 , S 49 , S 50 , S 52 The remaining switches of the module to which it belongs are disconnected, and the capacitor C INT2_1 , C INT2_2 , C INT2_3 , C INT2_4 Connected in parallel with capacitor C RESN , C RESP Charge sharing is performed in a fully differential circuit to achieve second-level integration; ④Switch S 39 , S 41 , S 44 , S 46 , S 48 , S 51 Closed, the other switches are open, and the capacitor C INT2_1 , C INT2_2 Then connect in series to V P Terminal, capacitor C INT2_3 , C INT2_4 Then connect in series to V N terminal to amplify the second stage integrated voltage by four times, and at the same time, the capacitor C INT1P , C INT2_1 , C INT2_2 Series, capacitor C INT1N , C INT2_3 , C INT2_4 connected in series, so the first and second stage integrated voltages are both connected through V P and V N Passed back to SARADC.

10. The novel hybrid nested noise shaping architecture for noise shaping SAR ADC according to claim 8, characterized in that: The voltage signal of the EF noise shaping loop is V OP and V ON , the output is V DACP and V DACN ; The EF noise shaping loop has the same capacitance value as the capacitor C FIR1N , C FIR1P , C FIR2N , C FIR2P , C DELN , C DELP The second-order passive finite impulse response filter FIR composed of each switch; the working process of the EF noise shaping loop is as follows: ①Switches S1 and S2 are closed, and the other switches are open. DELN , C DELP Reset; ②Switches S5 and S6 are closed, and the other switches are open, capacitor C FIR2N , C FIR2P The voltage stored in the previous cycle, which is the residual voltage amplified by the residual amplifier in the previous cycle, is transferred to the capacitor C through charge sharing. DELN , C DELP superior; ③Switch S7, S8, S 11 , S 12 The remaining switches are closed and the residual voltage of the previous cycle amplified by the residual amplifier is stored in the capacitor C FIR1N , C FIR1P and C FIR2N , C FIR2P superior; ④Switch S3, S4, S9, S 10 Close, and the other switches are open, and the capacitor C FIR1N , C FIR1P and C DELN , C DELP The voltage on the DACP and V DACN port.

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