Normalized splicing method of frame header and load suitable for multiple interconnection protocol frame generation process and multiple interconnection protocol frame generation device based on FPGA (Field Programmable Gate Array)

Abstract

The invention relates to the technical field of data processing and exchange forwarding, and provides a normalized splicing method of a frame header and a load, which is suitable for a multi-interconnection protocol frame generation process, and a multi-interconnection protocol frame generation device based on an FPGA (Field Programmable Gate Array). According to the method, generated frame header data is processed beat by beat, and the last beat of the frame header and the first beat of the load are simultaneously generated in the same beat through a set synchronous control signal, so that the frame header and the load are spliced in a seamless connection manner to form a complete data frame; and the frame header and the load in the splicing module are input in a whole-beat segmented manner. According to the splicing method provided by the invention, the requirement of generating data frames of different protocol types can be met, the complexity of a heterogeneous protocol frame generation process is remarkably reduced, the hardware resource utilization rate is improved by more than or equal to N times, the cost and power consumption advantages of the environment are enhanced, and meanwhile, new type protocol expansion can be flexibly carried out on the environment.

Description

Technical Field

[0001] The present invention relates to the technical field of data processing and switching forwarding, and in particular to a normalized splicing method for frame headers and payloads applicable to a plurality of interconnection protocol frame generation processes, and a plurality of interconnection protocol frame generation devices based on FPGA. Background Art

[0002] In various interconnection protocols, a complete data frame consists of a frame header, payload, CRC, frame header and frame tail flags, etc. The main parameters required for splicing the frame header and payload are the frame header length, frame header data, and payload data. In the traditional method of splicing the frame header and payload, since only a single protocol data frame is supported and the application scenario is simple, the frame header length is fixed, and the interception position of the frame header data is also fixed during splicing. Therefore, a set of splicing logic for a specific protocol can be used to achieve this.

[0003] When the number of supported protocol types in a hardware environment increases, the need for splicing frame headers and payloads generated by heterogeneous protocol data frames will cause the frame header interception position to become random when splicing the frame header and payload, and the splicing logic will increase dramatically. When the environment supports a small number of protocol types, the conventional processing method is to set up a separate case discussion for the splicing of frame headers and payloads for each different protocol. The processing logic of each protocol is completely independent in the code module. Since there is no "commonality" in the splicing operation, the result of redundant logic code is a large programming resource overhead, and as the number of protocol types increases, the code logic will become more complicated.

[0004] Based on the above disadvantages, since Verilog does not support dynamic bit width interception of vector data, in order to support the generation of multiple protocol data frames in one environment, the first traditional method proposed generally uses for loops to achieve splicing, such as Figure 1 As shown, the for loop implements the data interception algorithm of arbitrary frame header length.

[0005] In order to support the randomness of the frame header interception position in multi-protocol scenarios, the logic of implementing dynamic bit width interception through for loops is relatively clear. However, in hardware, for statements cannot be used too frequently. This is because each loop will copy the same circuit multiple times. That is, when N types of protocols need to be supported in the same environment, the same hardware circuit needs to be copied more than N times, and the above operation needs to be performed once each time a heterogeneous protocol is expanded.

[0006] At this time, the splicing logic is particularly complex, and it is impossible to directly and accurately obtain the splicing position of the frame header, resulting in large consumption of hardware resources and system power consumption. Since the splicing problem of the frame header and the payload is the key to the generation of frames of various protocol types, the traditional "list-style" splicing method of each protocol logic being independent of each other is not conducive to the flexible expansion of supported protocol types. Summary of the invention

[0007] In order to solve the problem of complex operation when splicing different frame header lengths and loads of different protocol types in the prior art, the present invention provides a normalized splicing method of frame headers and loads applicable to the frame generation process of multiple interconnection protocols, and a multiple interconnection protocol frame generation device based on FPGA. The frame header data generated by processing each beat is generated, and the tail beat of the frame header and the head beat of the load are simultaneously generated in the same beat by setting a synchronization control signal, so that the frame header and the load are seamlessly connected to perform splicing operations to form a complete data frame, which can effectively reduce the complexity of data splicing and reduce the waste of time and resources.

[0008] In a first aspect, the present invention provides a method for normalizing and splicing frame headers and payloads in a process of generating frames of multiple interconnection protocols, comprising:

[0009] Step 1: Obtain the frame header and payload of the protocol frame to be generated, and determine the frame header length;

[0010] Step 2: searching a lookup table based on the frame header length to see whether there is a splicing parameter matching the frame header length;

[0011] When the splicing parameters exist in the lookup table, the splicing position is directly obtained, and the frame header index is cyclically added to the splicing beat number to obtain the frame header data; wherein the splicing parameters include the splicing position, the frame header length and the splicing beat number;

[0012] When the splicing parameter does not exist in the lookup table, the frame header data is processed byte by byte, and the frame header index is recorded to determine whether the frame header length is a whole beat, and the splicing position and the splicing beat number of the protocol frame to be generated are determined according to whether the frame header length is a whole beat;

[0013] Wherein, the frame header index is used to indicate the process of processing frame header data;

[0014] Step 3: Determine whether to start the synchronization signal according to the frame header index and the splicing beat number, process the payload data when the synchronization signal is started, and record the payload index;

[0015] Step 4: performing a splicing operation on the frame header data and the payload data according to the splicing position, and completing the splicing of the protocol frame to be generated.

[0016] Furthermore, the method further comprises:

[0017] Step 5: Add the splicing parameters of the protocol frame to be generated to the lookup table, and reset the splicing parameters to prepare for the splicing operation when the next data frame is generated.

[0018] Further, in step 2, determining the splicing position and the number of splicing beats of the protocol frame to be generated according to whether the frame header length is a whole beat specifically includes:

[0019] The number of splicing beats is the frame header length / whole beat length;

[0020] Wherein, the splicing beat number is an integer value;

[0021] When the frame header length is a whole beat, the splicing position is the last data bit in the last beat of the frame header data;

[0022] When the frame header length is not a whole beat, the splicing position is a data bit of the frame header length% the whole beat length in the last beat of the frame header data.

[0023] Further, in step 4, the splicing operation of the frame header data and the payload data according to the splicing position specifically includes: when the synchronization signal is started, splicing boundary processing is performed according to whether the frame header length in step 2 is a full beat:

[0024] When the length of the frame header is a whole beat, the synchronization signal ends at the end of the last beat of the frame header data, and the first beat of the payload data is generated, and splicing is performed directly;

[0025] When the frame header length is not a whole beat, the last beat of the frame header data and the first beat of the payload data are generated simultaneously. After splicing, the remaining data of the last beat of the payload data is spliced ​​into a subsequent payload splicing process until the arrival of the tlast indication signal is recognized.

[0026] In a second aspect, the present invention provides a device for generating multiple interconnection protocol frames based on FPGA, on which a preset FPGA is arranged, and the FPGA includes a multi-protocol SerDes module, a multi-protocol controller module, a protocol frame generation module and a protocol frame splicing module;

[0027] The multi-protocol SerDes module is used to implement a serializer / deserializer for multiple communication protocols, and adapts to different communication standards by configuring different protocols;

[0028] The multi-protocol controller module is used to configure the multi-protocol SerDes module to support a specific communication protocol according to the requirement of generating a protocol frame, and pass the information of the specified protocol to the protocol frame generation module;

[0029] The protocol frame generation module is used to generate a frame header that conforms to a specified protocol frame format, and a payload of a specified length and content;

[0030] The protocol frame splicing module is used to splice the frame header and payload generated by the protocol frame generation module to form complete data frames of different protocols.

[0031] Furthermore, the protocol frame splicing module includes:

[0032] A frame header length determination unit, used to obtain a frame header and a payload of a protocol frame to be generated, and determine a frame header length;

[0033] A splicing position determining unit, configured to search a lookup table based on the frame header length to determine whether there is a splicing parameter matching the frame header length;

[0034] When the splicing parameters exist in the lookup table, the splicing position is directly obtained, and the frame header index is cyclically added to the splicing beat number to obtain the frame header data; wherein the splicing parameters include the splicing position, the frame header length and the splicing beat number;

[0035] When the splicing parameter does not exist in the lookup table, the frame header data is processed byte by byte, and the frame header index is recorded to determine whether the frame header length is a whole beat, and the splicing position and the splicing beat number of the protocol frame to be generated are determined according to whether the frame header length is a whole beat;

[0036] Wherein, the frame header index is used to indicate the process of processing frame header data;

[0037] A dynamic synchronization signal unit, used to determine whether to start the synchronization signal according to the frame header index and the splicing beat number, process the load data when the synchronization signal is started, and record the load index;

[0038] The frame header and payload splicing unit is used to perform a splicing operation on the frame header data and the payload data according to the splicing position, and the protocol frame to be generated completes the splicing.

[0039] Furthermore, the frame header payload splicing unit is also used for:

[0040] When the to-be-generated protocol frame completes splicing, the splicing parameters of the to-be-generated protocol frame are added to the lookup table, and the splicing parameters in the protocol frame splicing module are reset to prepare for the splicing operation when the next data frame is generated.

[0041] Furthermore, the splicing position determination unit is specifically used to:

[0042] The number of splicing beats is the frame header length / whole beat length;

[0043] Wherein, the splicing position determination unit is specifically used for:

[0044] The number of splicing beats is the frame header length / whole beat length;

[0045] Wherein, the splicing beat number is an integer value;

[0046] When the frame header length is a whole beat, the splicing position is the last data bit in the last beat of the frame header data;

[0047] When the frame header length is not a whole beat, the splicing position is a data bit of the frame header length% the whole beat length in the last beat of the frame header data.

[0048] Furthermore, the frame header payload splicing unit is specifically used for:

[0049] When the synchronization signal is started, splicing boundary processing is performed according to the judgment result of whether the frame header length is a whole beat in the splicing position determination unit:

[0050] When the length of the frame header is a whole beat, the synchronization signal ends at the end of the last beat of the frame header data, and the first beat of the payload data is generated, and splicing is performed directly;

[0051] When the frame header length is not a whole beat, the last beat of the frame header data and the first beat of the payload data are generated simultaneously. After splicing, the remaining data of the last beat of the payload data is spliced ​​into a subsequent payload splicing process until the arrival of the tlast indication signal is recognized.

[0052] Beneficial effects of the present invention:

[0053] The method proposed by the present invention for controlling the splicing of frame headers and payloads by dynamically acquiring the frame header length and adopting a synchronization mechanism can realize the normalization of the splicing process of any frame header length and payload. In a hardware environment supporting N heterogeneous protocols, the splicing logic of frame headers and payloads originally required for N types of protocols is reduced to 1 set, and the implemented logical structure is clear and simple, without the cumbersome operation of accumulating multiple calculations to cause waste of time and resources.

[0054] The splicing logic provided by the present invention can meet the needs of generating data frames of different protocol types, significantly reduce the complexity of the heterogeneous protocol frame generation process, increase the hardware resource utilization by greater than or equal to N times, enhance the cost and power consumption advantages of the environment, and facilitate flexible expansion of the environment with new types of protocols.

[0055] In addition, the present invention records the frame header length of each splicing by utilizing a lookup table, and directly searches for and uses the relevant parameters used for splicing during the next splicing (under the same protocol, there will not be too many types of frame header lengths), thereby avoiding repeated calculation of splicing positions and comparison operations, reducing resource consumption and thus improving utilization. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Figure 1A logic diagram of a method for implementing arbitrary frame header length data in a for loop in the prior art;

[0057] Figure 2 It is a physical layer frame header field format diagram of the prior art PCIe protocol;

[0058] Figure 3 A schematic flow chart of a method for normalizing and splicing frame headers and payloads applicable to a plurality of interconnection protocol frame generation processes provided by an embodiment of the present invention;

[0059] Figure 4 A schematic diagram of the structure of a device for generating multiple interconnection protocol frames based on FPGA provided by an embodiment of the present invention;

[0060] Figure 5 A schematic diagram of an FPGA workflow provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0061] In the communication of various interconnection protocols, the data frame (packet) is the basic unit of data transmission, which contains control information and user data and is used for communication between interconnection protocols. Different network layers and protocols use different types of data frames, but their basic structure and functions are similar. A complete data frame consists of a frame header, payload, CRC, frame header and frame tail flags, etc. The main parameters needed for splicing the frame header and payload are the frame header length, frame header data, and payload data. It can be seen that the splicing problem of the frame header and payload is the key to the generation of frames of various protocol types. Taking the communication of the PCIe protocol as an example, the format of the physical layer frame header field is as follows: Figure 2 As shown, during the communication process, it is first necessary to generate a PCIe data frame as the basic unit of communication. According to the format of the data frame specified by PCIe, it is divided into a frame header field and a payload field. These two parts of information are not generated as a whole, but after the frame header and payload are generated separately, they need to be spliced ​​one by one in the corresponding order to form a complete data frame for communication.

[0062] Similarly, communication protocols such as RapidIO, Ethernet, and FC will also face similar data frame splicing operation problems when generating data frames. Only after the splicing of the frame header and the payload can a complete data frame (packet) be formed. It should be noted that the lengths of the frame header and the payload under the same protocol or between different protocols may be inconsistent. Therefore, when facing the splicing of different frame header lengths and payloads of different protocol types in the same hardware environment, certain means need to be adopted to handle it. The present invention is to deal with such a dilemma, that is, how to support multi-protocol data frame generation in a set of hardware environment and reduce the complexity of splicing operations during frame generation.

[0063] The design idea of ​​the present invention is as follows: first, the frame header data generated is processed beat by beat, and the last beat of the frame header and the first beat of the payload are generated simultaneously in the same beat through the set synchronization control signal, so as to seamlessly connect the frame header and the payload for splicing operation to form a complete data frame. In the splicing module, both the frame header and the payload are implemented in the form of whole-beat segmented input. The lookup table records the splicing position corresponding to different frame header lengths, the number of beats of the splicing beats, and other parameters. Each time splicing is performed, the lookup table is searched first. If the same frame header length is matched, the splicing position is directly obtained without calculation, and there is no need to cyclically compare the size of the frame header index and the frame header length / whole beat length. After adding it directly to the specific splicing beat number, the splicing data is assigned and then spliced; if there is no record of matching the same frame header length, splicing is performed according to the unknown length, and the specific parameters are recorded in the lookup table. The technical scheme in the embodiment of the present invention will be clearly described below in conjunction with the drawings in the embodiment of the present invention.

[0064] like Figure 3 As shown, an embodiment of the present invention provides a normalized splicing method for frame headers and payloads applicable to a plurality of interconnection protocol frame generation processes, comprising:

[0065] Step 1: Determine the dynamic frame header length.

[0066] Obtain the frame header and payload of the protocol frame to be generated, and determine the frame header length;

[0067] When facing the generation of arbitrary frame header length data of different protocol types, the frame header length is temporarily stored through the configuration register. Each time the frame header data is generated, the specific length of the frame header is dynamically read from the configuration register to generate the frame header data.

[0068] Step 2: Process the frame header to determine the splicing position.

[0069] Based on the frame header length, the lookup table is searched to see if there is a splicing parameter that matches the frame header length. The splicing parameters in the lookup table are as follows: Figure 4 As shown;

[0070] When the lookup table contains splicing parameters, the splicing position is directly obtained, and the frame header index is cyclically added to the splicing beat number to obtain the frame header data; wherein the splicing parameters include the splicing position, the frame header length and the splicing beat number;

[0071] Specifically, when the same frame header length type is retrieved in the lookup table, the splicing parameters are directly obtained to obtain the splicing position, and the frame header index header_index is cyclically added to the splicing beat number to directly obtain the frame header data header_data.

[0072] When the lookup table does not contain splicing parameters, the frame header data is processed byte by byte and the frame header index is recorded to determine whether the frame header length is a full beat. The splicing position and number of splicing beats of the protocol frame to be generated are determined based on whether the frame header length is a full beat. The frame header index is used to indicate the process of processing the frame header data.

[0073] Specifically, when the lookup table does not contain splicing parameters, the frame header data header_data is processed byte by byte, and the frame header index header_index is recorded in real time. When the frame header index header_index does not reach the splicing beat number, the value of the frame header data header_data is continuously updated, and the frame header index header_index is incremented by 1 according to the beat number.

[0074] Whether the frame header is a whole beat is determined by the frame header length. When the frame header is a whole beat data, that is, the last beat data is all valid data; when the frame header is not a whole beat data, that is, only part of the last beat data is valid data. The whole beat data in this embodiment is 128 bits, and it can be judged by the following logic:

[0075] if(header_length%128!=0)

[0076] Specifically, the splicing position and the number of splicing beats of the protocol frame to be generated are determined according to whether the frame header length is a full beat, including:

[0077] The number of splicing beats is the frame header length / the whole beat length, that is, the number of splicing beats = header_length / 128.

[0078] Among them, the number of splicing beats is an integer value, and the decimal value is directly truncated to get the integer.

[0079] When the frame header length is a whole beat, the splicing position is the last data bit in the last beat of the frame header data;

[0080] When the frame header length is not a whole beat, the data bits of the frame header length% the whole beat length in the last beat of the frame header data at the splicing position, that is, the splicing position is the position of header_length%128 in the last beat, and the value in the frame header data header_data is assigned to the valid data bits in the last beat of the frame header.

[0081] Step 3: Dynamic sync signal settings.

[0082] Determine whether to start the synchronization signal according to the frame header index and the number of splicing beats, process the payload data when the synchronization signal is started, and record the payload index;

[0083] Specifically, when the frame header index header_index reaches the number of splicing beats header_length / 128, the synchronization signal is started and the payload begins to be generated:

[0084] if(header_index==header_length / 128)begin

[0085] sync_signal<=1'b1.

[0086] Step 4: Frame header payload splicing operation.

[0087] The frame header data and the payload data are spliced ​​according to the splicing position, and the splicing is completed after the protocol frame is generated.

[0088] Specifically, when the synchronization signal is started, the splicing boundary processing is performed according to whether the frame header length in step 2 is a whole beat: that is, the splicing boundary processing needs to be performed according to whether the last beat of the frame header is a whole beat.

[0089] When the frame header length is a full beat, the synchronization signal ends at the end of the last beat of the frame header data, and the first beat of the payload data is generated, and splicing is performed directly;

[0090] Specifically, the synchronization signal is generated when the last beat of the frame header data ends, and the first beat of the payload data is generated, that is, the first beat of the payload data payload_data arrives just at the end of the frame header. After the splicing is completed, it can be continuously output. At this time, the following simple splicing operation can be used:

[0091] if(payload_index==1&&sync_signal==1)begin

[0092] Data_out<={header_data,payload_data};

[0093] When the frame header length is not a full beat, the last beat of the frame header data and the first beat of the payload data are generated at the same time. After splicing, the remaining data of the last beat of the payload data is spliced ​​and incorporated into the subsequent payload splicing process until the arrival of the tlast indication signal is recognized.

[0094] Specifically, the last beat data of the frame header is not a full beat, but the last beat data of the frame header and the first beat data of the payload are still generated in the same beat. After splicing through the same splicing logic, the remaining last beat data of the payload is beat and incorporated into the subsequent payload splicing process until the arrival of the tlast indication signal is recognized.

[0095] Step 5: Continue processing logic.

[0096] The splicing parameters of the protocol frame to be generated are added to the lookup table, and the splicing parameters are reset to prepare for the splicing operation when the next data frame is generated.

[0097] Specifically, if the splicing parameters are not obtained from the lookup table, the relevant splicing parameters are added to the lookup table to facilitate the generation of the protocol frame with the same frame header length next time. Since the frame header and payload are continuously generated, it is necessary to generate a certain amount of data according to actual needs. Therefore, it is necessary to continuously process the splicing operation of the frame header and payload of the next frame, so it is necessary to reset the corresponding signal and prepare for the next splicing operation. The example logic is as follows:

[0098] If(tlast==1&&sync_signal==1)begin

[0099] header_index <= 0;

[0100] payload_index<=0;

[0101] sync_signal<=1'b0;

[0102] header_length <= 0;

[0103] tlast<=0;

[0104] The splicing logic provided by the present invention can meet the needs of generating data frames of different protocol types, significantly reduce the complexity of the heterogeneous protocol frame generation process, and apply the splicing method provided by the present invention to hardware. Compared with the prior art, the hardware resource utilization rate is significantly improved, the cost and power consumption advantages of the environment are enhanced, and the environment can be flexibly expanded with new types of protocols.

[0105] Examples of splicing methods:

[0106] 1) The header length header_length is read from the configuration register as 480 bits. The lookup table is searched and no splicing parameters with the same header length are found.

[0107] 2) The frame header data is input in segments of 128 bits per frame, and the header index header_index increases by 1 for each segment input;

[0108] 3) When inputting to the third segment, the frame header index header_index = frame header length header_length / whole beat 128 = 3, at this time, the synchronization signal sync_signal is set to 1 and valid, and the payload generation is started. When the payload generates the first beat, the payload index payload_index is incremented by 1, and the frame header continues to generate the remaining 96-bit data and input it into header_data;

[0109] 4) Perform a splicing operation, add header_data to the frame header data payload_data of the first beat, and put the remaining 32-bit data in the last beat of payload into the next splicing process until the splicing ends when the payload recognizes the tlast indicator bit.

[0110] 5) After the splicing operation is completed and the protocol frame is output, the splicing signals such as the above-mentioned frame header length header_length, frame header index header_index, synchronization signal sync_signal and payload index payload_index should be reset to facilitate the next splicing.

[0111] The embodiment of the present invention also provides a device for generating multiple interconnection protocol frames based on FPGA, which is configured with a preset FPGA, such as Figure 4 As shown, the FPGA includes a multi-protocol SerDes module, a multi-protocol controller module, a protocol frame generation module and a protocol frame splicing module;

[0112] Multi-protocol SerDes module, used to implement serialization / deserialization of multiple communication protocols, adapting to different communication standards by configuring different protocols;

[0113] The multi-protocol controller module is used to configure the multi-protocol SerDes module to support a specific communication protocol according to the requirements of generating a protocol frame, and pass the information of the specified protocol to the protocol frame generation module;

[0114] The protocol frame generation module is used to generate a frame header that conforms to the specified protocol frame format, as well as a payload of a specified length and content;

[0115] The protocol frame splicing module is used to splice the frame header and payload generated by the protocol frame generation module to form complete data frames of different protocols.

[0116] It can be understood that the protocol frame splicing module is the splicing operation of this design, which is used to splice the frame header and payload generated by the protocol frame generation module to form a complete data frame of different protocols. The FPGA workflow diagram is as follows: Figure 5 As shown in the figure, FPGA completes the configuration of the multi-protocol controller register according to the command. Under the action of the multi-protocol control module whose output is determined by the configuration register, the protocol frame generation module generates a frame header that conforms to the specified protocol frame format, as well as a payload of specified length and content.

[0117] Specifically, the protocol frame splicing module includes:

[0118] A frame header length determination unit, used to obtain a frame header and a payload of a protocol frame to be generated, and determine a frame header length;

[0119] A splicing position determining unit, used for searching a lookup table based on the frame header length to see whether there is a splicing parameter matching the frame header length;

[0120] When the lookup table contains splicing parameters, the splicing position is directly obtained, and the frame header index is cyclically added to the splicing beat number to obtain the frame header data; wherein the splicing parameters include the splicing position, the frame header length and the splicing beat number;

[0121] When the lookup table does not contain splicing parameters, the frame header data is processed byte by byte, and the frame header index is recorded to determine whether the frame header length is a whole beat, and the splicing position and splicing beat number of the protocol frame to be generated are determined according to whether the frame header length is a whole beat;

[0122] Among them, the frame header index is used to indicate the process of processing the frame header data;

[0123] A dynamic synchronization signal unit is used to determine whether to start the synchronization signal according to the frame header index and the number of splicing beats, process the load data when the synchronization signal is started, and record the load index;

[0124] The frame header and payload splicing unit is used to perform a splicing operation on the frame header data and the payload data according to the splicing position, and complete the splicing after the protocol frame is generated.

[0125] Furthermore, the frame header payload splicing unit is also used for:

[0126] When the protocol frame to be generated is completed, the splicing parameters of the protocol frame to be generated are added to the lookup table, and the splicing parameters in the protocol frame splicing module are reset to prepare for the splicing operation when the next data frame is generated.

[0127] Specifically, the splicing position determination unit is specifically used to:

[0128] The number of splicing beats is the frame header length / whole beat length;

[0129] Among them, the number of splicing beats takes an integer value;

[0130] When the frame header length is a whole beat, the splicing position is the last data bit in the last beat of the frame header data;

[0131] When the frame header length is not a whole beat, the splicing position is the data bit of the frame header length% whole beat length in the last beat of the frame header data;

[0132] Specifically, the frame header payload splicing unit is specifically used for:

[0133] When the synchronization signal starts, the splicing boundary processing is performed based on the judgment result of whether the frame header length in the splicing position determination unit is a full beat:

[0134] When the frame header length is a full beat, the synchronization signal ends at the end of the last beat of the frame header data, and the first beat of the payload data is generated, and splicing is performed directly;

[0135] When the frame header length is not a full beat, the last beat of the frame header data and the first beat of the payload data are generated at the same time. After splicing, the remaining data of the last beat of the payload data is spliced ​​and incorporated into the subsequent payload splicing process until the arrival of the tlast indication signal is recognized.

[0136] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A normalized splicing method for frame headers and payloads applicable to the generation process of frames of various interconnection protocols, characterized in that: include: Step 1: Obtain the frame header and payload of the protocol frame to be generated, and determine the frame header length; Step 2: searching a lookup table based on the frame header length to see whether there is a splicing parameter matching the frame header length; When the splicing parameters exist in the lookup table, the splicing position is directly obtained, and the frame header index is cyclically added to the splicing beat number to obtain the frame header data; wherein the splicing parameters include the splicing position, the frame header length and the splicing beat number; When the splicing parameter does not exist in the lookup table, the frame header data is processed byte by byte, and the frame header index is recorded to determine whether the frame header length is a whole beat, and the splicing position and the splicing beat number of the protocol frame to be generated are determined according to whether the frame header length is a whole beat; Wherein, the frame header index is used to indicate the process of processing frame header data; Step 3: Determine whether to start the synchronization signal according to the frame header index and the splicing beat number, process the payload data when the synchronization signal is started, and record the payload index; Step 4: performing a splicing operation on the frame header data and the payload data according to the splicing position, and completing the splicing of the protocol frame to be generated.

2. According to claim 1, a normalized splicing method for frame headers and payloads applicable to the generation process of frames of multiple interconnection protocols, characterized in that: The method further comprises: Step 5: Add the splicing parameters of the protocol frame to be generated to the lookup table, and reset the splicing parameters to prepare for the splicing operation when the next data frame is generated.

3. According to claim 1, a normalized splicing method for frame headers and payloads applicable to the generation process of frames of multiple interconnection protocols, characterized in that: In step 2, determining the splicing position and the number of splicing beats of the protocol frame to be generated according to whether the frame header length is a whole beat specifically includes: The number of splicing beats is the frame header length / whole beat length; Wherein, the splicing beat number is an integer value; When the frame header length is a whole beat, the splicing position is the last data bit in the last beat of the frame header data; When the frame header length is not a whole beat, the splicing position is a data bit of the frame header length% the whole beat length in the last beat of the frame header data.

4. According to claim 1, a normalized splicing method for frame headers and payloads applicable to the generation process of frames of multiple interconnection protocols, characterized in that: In step 4, the splicing operation is performed on the frame header data and the payload data according to the splicing position, specifically including: when the synchronization signal is started, splicing boundary processing is performed according to whether the frame header length in step 2 is a full beat: When the length of the frame header is a whole beat, the synchronization signal ends at the end of the last beat of the frame header data, and the first beat of the payload data is generated, and splicing is performed directly; When the frame header length is not a whole beat, the last beat of the frame header data and the first beat of the payload data are generated simultaneously. After splicing, the remaining data of the last beat of the payload data is spliced ​​into a subsequent payload splicing process until the arrival of the tlast indication signal is recognized.

5. A device for generating multiple interconnection protocol frames based on FPGA, on which a preset FPGA is arranged, characterized in that: The FPGA includes a multi-protocol SerDes module, a multi-protocol controller module, a protocol frame generation module and a protocol frame splicing module; The multi-protocol SerDes module is used to implement a serializer / deserializer for multiple communication protocols, and adapts to different communication standards by configuring different protocols; The multi-protocol controller module is used to configure the multi-protocol SerDes module to support a specific communication protocol according to the requirement of generating a protocol frame, and pass the information of the specified protocol to the protocol frame generation module; The protocol frame generation module is used to generate a frame header that conforms to a specified protocol frame format, and a payload of a specified length and content; The protocol frame splicing module is used to splice the frame header and payload generated by the protocol frame generation module to form complete data frames of different protocols.

6. The device for generating multiple interconnection protocol frames based on FPGA according to claim 5, characterized in that: The protocol frame splicing module includes: A frame header length determination unit, used to obtain a frame header and a payload of a protocol frame to be generated, and determine a frame header length; A splicing position determining unit, configured to search a lookup table based on the frame header length to determine whether there is a splicing parameter matching the frame header length; When the splicing parameters exist in the lookup table, the splicing position is directly obtained, and the frame header index is cyclically added to the splicing beat number to obtain the frame header data; wherein the splicing parameters include the splicing position, the frame header length and the splicing beat number; When the splicing parameter does not exist in the lookup table, the frame header data is processed byte by byte, and the frame header index is recorded to determine whether the frame header length is a whole beat, and the splicing position and the splicing beat number of the protocol frame to be generated are determined according to whether the frame header length is a whole beat; Wherein, the frame header index is used to indicate the process of processing frame header data; A dynamic synchronization signal unit, used to determine whether to start the synchronization signal according to the frame header index and the splicing beat number, process the load data when the synchronization signal is started, and record the load index; The frame header and payload splicing unit is used to perform a splicing operation on the frame header data and the payload data according to the splicing position, and the protocol frame to be generated completes the splicing.

7. The device for generating multiple interconnection protocol frames based on FPGA according to claim 6, characterized in that: The frame header payload splicing unit is also used for: When the to-be-generated protocol frame completes splicing, the splicing parameters of the to-be-generated protocol frame are added to the lookup table, and the splicing parameters in the protocol frame splicing module are reset to prepare for the splicing operation when the next data frame is generated.

8. The device for generating multiple interconnection protocol frames based on FPGA according to claim 6, characterized in that: The splicing position determination unit is specifically used for: The number of splicing beats is the frame header length / whole beat length; Wherein, the splicing beat number is an integer value; When the frame header length is a whole beat, the splicing position is the last data bit in the last beat of the frame header data; When the frame header length is not a whole beat, the splicing position is a data bit of the frame header length% the whole beat length in the last beat of the frame header data.

9. The device for generating multiple interconnection protocol frames based on FPGA according to claim 6, characterized in that: The frame header payload splicing unit is specifically used for: When the synchronization signal is started, splicing boundary processing is performed according to the judgment result of whether the frame header length is a whole beat in the splicing position determination unit: When the length of the frame header is a whole beat, the synchronization signal ends at the end of the last beat of the frame header data, and the first beat of the payload data is generated, and splicing is performed directly; When the frame header length is not a whole beat, the last beat of the frame header data and the first beat of the payload data are generated simultaneously. After splicing, the remaining data of the last beat of the payload data is spliced ​​into a subsequent payload splicing process until the arrival of the tlast indication signal is recognized.

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