Multi-target high-speed image acquisition system

Abstract

The invention provides a multi-target high-speed image acquisition system, and belongs to the field of multi-target high-speed image data acquisition. And data transmission is carried out after an image compression algorithm, so that certain effective data loss is caused, and a single chip microcomputer or a DSP (Digital Signal Processor) is used as a main control chip, so that the overall system complexity is high. After a plurality of detector cores in the detector are used for collecting images and converting the images into digital images, an image collecting and sending / instruction receiving and sending module in an image collecting and sending / instruction receiving and sending unit is used for transmitting graphic data to complete the collection of multi-target data, and a first DDR4 is used for storing the data to avoid the loss of the data. The first FPGA and the second FPGA transmit the image data to the image acquisition application module and the detector instruction control module, so that the design of the multi-target high-speed image data acquisition system is simplified, the maintenance of the system is facilitated, and the reliability of the multi-target high-speed image data acquisition system is improved.

Description

Technical Field

[0001] The invention belongs to the field of multi-target high-speed image data acquisition, and in particular relates to a multi-target high-speed image acquisition system. Background Art

[0002] Due to the limitations of large image data volume and long transmission distance, multi-target high-speed image data transmission is usually transmitted after compression, and is completed on the equipment using microprocessor chips such as single-chip microcomputers or DSPs. This will cause a certain loss of useful information on the image, and the system design is complex and the cost is high. A multi-target high-speed image acquisition system transmits image data through the high-speed interface of FPGA, transmits and acquires multi-target images through gigabit optical fiber, and packages and organizes multi-target image data into a single FPGA through 10-gigabit optical fiber, and transmits it to the PC side through the PCIE interface to complete image acquisition, which not only reduces the complexity and cost of the system, but also increases the reliability and stability of the system. At the same time, it completes multi-target image acquisition and long-distance transmission, completes multi-channel to single-channel reception of multi-target images, and transfers multi-target images to the PC side through PCIE, etc., which improves the ease of implementation and reliability of the system.

[0003] In summary, a multi-target high-speed image acquisition system is proposed. Summary of the invention

[0004] In view of this, the present invention aims to propose a multi-target high-speed image acquisition system to solve the technical problems of data transmission after image compression algorithm, resulting in certain effective data loss, and the overall system complexity is high when using a single-chip microcomputer or DSP as the main control chip.

[0005] To achieve the above object, the present invention adopts the following technical solution: a multi-target high-speed image acquisition system, comprising: The first FPGA receives data transmitted by the image acquisition transmission / instruction transceiver unit and caches the data into the first DDR4, and packages the instructions transmitted by the image acquisition transmission / instruction transceiver unit; The second FPGA receives the compressed instruction transmitted by the image acquisition sending / instruction transceiver unit received by the first FPGA, sends the instruction to the image acquisition sending / instruction transceiver unit through the first FPGA, and is connected to the second DDR4 for storing image data; The image acquisition application and the detector command control module send control commands to the second FPGA and receive the data packaged by the second FPGA; The detector is used to convert the external image into a digital image and transmit the digital image to the image acquisition sending / instruction transceiver unit, receive the instruction of the image acquisition sending / instruction transceiver unit and transmit the reply instruction back to the image acquisition sending / instruction transceiver unit; Among them, the detector includes several detector movements for converting external images into digital images, the image acquisition sending / command transceiver unit includes several image acquisition sending / command transceiver modules, all of the detector movements and all of the image acquisition sending / command transceiver modules are connected one-to-one, and the image acquisition sending / command transceiver modules are connected to the first FPGA.

[0006] Furthermore, the first FPGA is a Gigabit fiber optic acquisition and 10 Gigabit fiber optic transmission module, and the Gigabit fiber optic acquisition and 10 Gigabit fiber optic transmission module is connected to all the image acquisition and transmission / command transceiver modules through optical fiber lines.

[0007] Furthermore, the Gigabit fiber acquisition and 10 Gigabit fiber transmission modules receive data transmitted from the image acquisition transmission / command transceiver module according to different ports and cache the data into the first DDR4, package the multi-port data image according to the 10 Gigabit fiber transmission protocol and send the data to the second FPGA through the 10 Gigabit fiber high-speed port, receive instructions transmitted from the image acquisition transmission / command transceiver module according to different ports, package them and send them to the second FPGA, receive control instructions from the second FPGA, unpack them and send the corresponding control instructions to the several image acquisition transmission / command transceiver modules according to different Gigabit ports.

[0008] Furthermore, the second FPGA includes a 10 Gigabit instruction transceiver module and a 10 Gigabit fiber acquisition module, a DDR4 read-write control module, an image data protocol packaging module and a PCIE data read-write control module connected in sequence. The 10 Gigabit fiber acquisition module receives the image data transmitted by the 1 Gigabit fiber acquisition and 10 Gigabit fiber transmission modules and decompresses the compressed image data and transmits it to the DDR4 read-write control module. The DDR4 read-write control module caches the decompressed image data to the second DDR4 after writing. The DDR4 read-write control module reads the image data inside the second DDR4 and transmits it to the image data protocol packaging module. The image data protocol packaging module packages the received image data and transmits it to the image acquisition application and the detector instruction control module through the PCIE data read-write control module. The detector instruction control module packages the control instruction through the PCIE data read-write control module and sends it to the 10 Gigabit instruction transceiver module. The 10 Gigabit instruction transceiver module packages the received control instruction according to the protocol and sends it to the first FPGA. The 10 Gigabit instruction transceiver module receives the response instruction sent by the first FPGA and transmits the instruction to the PCIE data read-write control module.

[0009] Furthermore, the 10 Gigabit optical fiber acquisition module receives and unpacks the image data transmitted by the first FPGA through the 10 Gigabit high-speed interface.

[0010] Furthermore, the 10 Gigabit optical fiber acquisition module transmits the decompressed image data to the DDR4 read-write control module through several write ports, and the DDR4 read-write control module writes the image data according to the addresses of different write ports. The written image data is accessed at different addresses of the second DDR4 according to the control timing of the DDR4 read-write control module.

[0011] Furthermore, the DDR4 read-write control module transmits the image data to the image data protocol packaging module through several read ports, and the DDR4 read-write control module reads the image data at different addresses of the second DDR4 according to the sending timing of the image data protocol packaging module and sends it to the image data protocol packaging module.

[0012] Furthermore, the image acquisition sending / command transceiving module of the image acquisition sending / command transceiving unit is connected to the first FPGA via a gigabit optical fiber.

[0013] Furthermore, the length of the gigabit optical fiber is selected according to actual conditions.

[0014] Furthermore, the image acquisition application, the detector command control module and the host computer are connected.

[0015] Beneficial effects: After the images are collected by multiple detector movements inside the detector and converted into digital images, the image acquisition sending / command transceiver module inside the image acquisition sending / command transceiver unit transmits the graphic data to complete the collection of multi-target data, and then stores it in the first DDR4 to avoid data loss. The first FPGA and the second FPGA transmit the image data to the image acquisition application and the detector command control module to achieve 2. Simplify the design of the multi-target high-speed image data acquisition system, facilitate system maintenance, and improve the reliability of the multi-target high-speed image data acquisition system. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings constituting a part of the present invention are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the accompanying drawings: Figure 1 The figure is a schematic diagram of the overall structure of a multi-target high-speed image acquisition system according to the present invention.

[0017] Detector 1; receiving image acquisition sending / command transceiver unit 2; first FPGA 3; 10G optical fiber acquisition module 4; DDR4 read-write control module 5; second DDR4 6; image data protocol packaging module 7; PCIE data read-write control module 8; 10G command transceiver module 9; image acquisition application, detector command control module 10; first DDR4 11. DETAILED DESCRIPTION

[0018] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely explain the technical solutions in the embodiments of the present invention. It should be noted that the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict, and the described embodiments are only part of the embodiments of the present invention, not all of the embodiments.

[0019] It should be noted that the descriptions of the present invention regarding directions such as "left", "right", "left side", "right side", "upper", "lower", "top", and "bottom" are all defined based on the relationship between the orientations or positions shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the structure must be constructed and operated in a specific orientation. Therefore, it cannot be understood as a limitation on the present invention. In the description of the present invention, the meaning of "multiple" is more than two, unless otherwise clearly and specifically defined.

[0020] In the description of the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0021] Referring to the accompanying drawings, this embodiment is described, providing a multi-target high-speed image acquisition system, comprising: The first FPGA3 receives the data transmitted by the image acquisition sending / instruction transceiver unit 2 and caches it in the first DDR411, and packages the instructions transmitted by the image acquisition sending / instruction transceiver unit 2; The second FPGA receives the compressed instruction transmitted by the image acquisition sending / instruction transceiver unit 2 received by the first FPGA3, sends the instruction to the image acquisition sending / instruction transceiver unit 2 through the first FPGA3, and is connected to the second DDR46 for storing image data; The image acquisition application and detector command control module 10 sends control commands to the second FPGA and receives data packaged by the second FPGA; The detector 1 is used to convert the external image into a digital image and transmit the digital image to the image acquisition sending / command transceiver unit 2, and transmit the reply command back to the image acquisition sending / command transceiver unit 2 after receiving the command from the image acquisition sending / command transceiver unit 2; Among them, the detector 1 includes several detector movements for converting external images into digital images, the image acquisition sending / command transceiver unit 2 includes several image acquisition sending / command transceiver modules, all of the detector movements and all of the image acquisition sending / command transceiver modules are connected one-to-one, and the image acquisition sending / command transceiver modules are connected to the first FPGA3.

[0022] The detector movement of the detector 1 receives the control instruction of the image acquisition sending / instruction transceiver module of the image acquisition sending / instruction transceiver unit 2 for control, and the detector movement feeds back the instruction to the image acquisition sending / instruction transceiver module, and the detector movement sends the image data to the image acquisition sending / instruction transceiver module, and the image acquisition sending / instruction transceiver module unpacks the control instruction transmitted by the first FPGA3 and transmits it to the detector movement, and the image acquisition sending / instruction transceiver module receives the instruction reply from the detector movement and sends it to the first FPGA3 after packaging, and the image acquisition sending / instruction transceiver module packages the digital image data sent by the detector movement according to the corresponding port protocol and sends it to the first FPGA 3. The first FPGA3 unpacks the image data transmitted by the image acquisition sending / instruction transceiver module, and packs the data of different ports according to the protocol and sends them to the second FPGA. The image acquisition sending / instruction transceiver module sends the control instructions received by the second FPGA to the image acquisition sending / instruction transceiver module according to the corresponding port protocol. The first FPGA3 sends the response instructions fed back by the image acquisition sending / instruction transceiver module to the second FPGA. The second FPGA passes the data to the image acquisition application and the detector command control module 10, which reduces the volume of the multi-target high-speed image data acquisition system and completes the acquisition of long-distance image data and the working control of the detector movement.

[0023] Among them, DDR4 is a high-bandwidth computer memory, and FPGA is a programmable semiconductor device that allows users to configure hardware logic as needed.

[0024] In this embodiment, the first FPGA3 is a Gigabit fiber acquisition and 10 Gigabit fiber transmission module, which is connected to all the image acquisition and transmission / command transceiver modules through optical fiber lines. The Gigabit fiber acquisition and 10 Gigabit fiber transmission modules receive data transmitted from the image acquisition and transmission / command transceiver modules according to different ports and cache them to the first DDR411, package the multi-port data image according to the 10 Gigabit fiber transmission protocol and send the data to the second FPGA through the 10 Gigabit fiber high-speed port, receive the instructions transmitted from the image acquisition and transmission / command transceiver modules according to different ports, package them and send them to the second FPGA, receive the control instructions of the second FPGA, unpack them and send the corresponding control instructions to the several image acquisition and transmission / command transceiver modules according to different Gigabit ports, and the Gigabit fiber acquisition and 10 Gigabit fiber transmission modules complete the multi-port long-distance acquisition of image data and the protocol packaging, reception and transmission.

[0025] In this embodiment, the second FPGA includes a 10 Gigabit instruction transceiver module 9 and a 10 Gigabit fiber acquisition module 4, a DDR4 read-write control module 5, an image data protocol packaging module 7 and a PCIE data read-write control module 8 connected in sequence. The 10 Gigabit fiber acquisition module 4 receives the image data transmitted by the 1 Gigabit fiber acquisition and 10 Gigabit fiber transmission modules 3 and decompresses and transmits the compressed image data to the DDR4 read-write control module 5. The DDR4 read-write control module 5 writes and caches the decompressed image data to the second DDR46. The DDR4 read-write control module 5 reads the image data inside the second DDR46 and transmits it to the image data protocol packaging module 7. The image data protocol packaging module The module 7 packages the received image data and transmits it to the image acquisition application and the detector instruction control module 10 through the PCIE data read-write control module 8. The detector instruction control module 10 packages the control instructions through the PCIE data read-write control module 8 and sends them to the 10 Gigabit instruction transceiver module 9. The 10 Gigabit instruction transceiver module 9 packages the received control instructions according to the protocol and sends them to the first FPGA3. The 10 Gigabit instruction transceiver module 9 receives the response instructions sent by the first FPGA3 and transmits the instructions to the PCIE data read-write control module 8. The 10 Gigabit optical fiber acquisition module 4 receives and unpacks the image data transmitted by the first FPGA3 through the 10 Gigabit high-speed interface. Block 4 transmits the decompressed image data to the DDR4 read-write control module 5 through several write ports. The DDR4 read-write control module 5 writes the image data according to the addresses of different write ports. The written image data is accessed at different addresses of the second DDR46 according to the control timing of the DDR4 read-write control module 5. The DDR4 read-write control module 5 transmits the image data to the image data protocol packaging module 7 through several read ports. The DDR4 read-write control module 5 reads the image data at different addresses of the second DDR46 according to the sending timing of the image data protocol packaging module 7 and sends it to the image data protocol packaging module 7. The 10 Gigabit optical fiber acquisition module 4 acquires the image data at different addresses of the second DDR46 according to the sending timing of the image data protocol packaging module 7. The image data input by the fiber transmission module is received and unpacked through the 10G high-speed interface, and the data of the corresponding port protocol is transmitted to the port corresponding to the DDR4 read-write control module 5. The DDR4 read-write control module 5 performs data write cache work on the data transmitted by the 10G fiber acquisition module 4 according to the addresses of different write ports. The DDR4 read-write control module 5 reads the image data of different addresses 6 and sends them to 7 according to the sending timing of the image data protocol packaging module 7. The second DDR4 6 accesses the image data of different addresses according to the control timing of the DDR4 read-write control module 5. The image data protocol packaging module 7 packages and sends the data of different ports according to the read-write timing of the PCIE data read-write control module 8 and the DDR4 read-write control module 5.The PCIE data read-write control module 8 packages the data of different DDR4 addresses transmitted by the image data protocol packaging module 7 according to the transmission protocol, and sends the packaged data to 10. The PCIE data read-write control module 8 packages the control instructions sent by 10 and sends them to the 10G instruction transceiver module 9. The PCIE data read-write control module 8 receives the instructions fed back by the 10G instruction transceiver module 9 and packages the data according to the protocol and sends it to the image acquisition application and detector instruction control module 10. The 10G instruction transceiver module 9 receives the control instructions transmitted by 8 and packages them according to the protocol and sends them to 3. 9 receives the instructions sent by 3. The response instruction is sent to 8. The image acquisition application and detector instruction control module 10 receives the image data sent by the PCIE data read and write control module 8, and restores the data of different detector movements according to the protocol, and performs image restoration and subsequent applications. The image acquisition application and detector instruction control module 10 sends different target instructions to control the detector movement according to the needs, and receives the feedback of the corresponding detector movement, which simplifies the design of the multi-target high-speed image data acquisition system, facilitates the maintenance of the system, and improves the reliability of the multi-target high-speed image data acquisition system. The cost of the multi-target high-speed image data acquisition system is greatly reduced to meet the various usage environments of users.

[0026] In this embodiment, the image acquisition sending / command transceiving module of the image acquisition sending / command transceiving unit 2 is connected to the first FPGA 3 via a gigabit optical fiber. The length of the gigabit optical fiber is selected according to actual conditions, and optical fiber propagation is more stable.

[0027] In this embodiment, the image acquisition application, the detector command control module 10 and the host computer are connected.

[0028] Working principle: The detector movement of the detector 1 operates by means of the control instructions transmitted by the image acquisition sending / command transceiver module of the image acquisition sending / command transceiver unit 2 and feeds back the corresponding instruction response to the image acquisition sending / command transceiver module. The detector movement converts the collected external image data into a digital image and transmits it to the image acquisition sending / command transceiver module. The image acquisition sending / command transceiver module receives the long-distance control instructions transmitted by the Gigabit optical fiber acquisition and 10 Gigabit optical fiber transmission modules of the first FPGA3, and unpacks the control instructions according to the protocol and sends them to the corresponding detector movement. The image acquisition sending / command transceiver module receives the instruction reply sent by the detector movement and sends it to the Gigabit optical fiber acquisition and 10 Gigabit optical fiber transmission modules after packaging according to the protocol. The command transceiver module packages the digital image data sent from the detector movement according to the corresponding port protocol and sends it to the gigabit fiber acquisition and 10 gigabit fiber sending module through the gigabit fiber optic cable. The gigabit fiber optic acquisition and 10 gigabit fiber optic sending module unpacks the image data transmitted from the image acquisition and sending / command transceiver module, and packages the data of different ports according to the protocol and sends them to the 10 gigabit fiber optic acquisition module 4 through the 10 gigabit fiber optic cable. The gigabit fiber optic acquisition and 10 gigabit fiber optic sending module packages the commands for controlling different detector movements received by the 10 gigabit command transceiver module 9 according to the corresponding port protocol and sends them to the image acquisition and sending / command transceiver module. The gigabit fiber optic acquisition and 10 gigabit fiber optic sending module sends the response commands of different ports fed back by the image acquisition and sending / command transceiver module to the 10 gigabit command transceiver module 9.The 10 Gigabit fiber acquisition module 4 unpacks the data transmitted by the 1 Gigabit fiber acquisition and 10 Gigabit fiber transmission modules, and transmits the unpacked port data of different detector movements to the corresponding write ports of the first DDR411 read-write control module. The first DDR411 read-write control module writes the data transmitted from different write ports into different addresses of the second DDR46 for data caching according to the logic control. The image data protocol packaging module reads out the data in different addresses of the second DDR46 through different read ports according to the required timing of the PCIE data read-write control module and packages them according to different port data protocols, and sends them to the PCIE data read-write control module 8 after packaging. The PCIE data read-write control module 8 writes the image data protocol packaging module according to the PCIE protocol. The data sent by block 7 is sent to the detector command control module. The 10G command transceiver module 9 packages the command data sent by the PCIE data read-write control module 8 and sends it to the Gigabit fiber acquisition and 10G fiber transmission module. The 10G command transceiver module 9 receives the response command data fed back by the Gigabit fiber acquisition and 10G fiber transmission modules and packages them and sends them to the PCIE data read-write control module 8. The detector command control module 10 sends the movement control command to the control module 8 through the host computer according to the demand. The detector command control module 10 decodes the response command fed back by the control module 8 and solves the feedback state of the corresponding detector movement. The detector command control module 10 restores the image data sent by the control module 8 to different targets and completes the multi-target image acquisition for subsequent applications. ;

[0029] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific implementation methods described. According to the content of this specification, many modifications and changes can be made. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well.

Claims

1. A multi-target high-speed image acquisition system, characterized in that: include: A first FPGA (3) receives data transmitted by the image acquisition transmission / instruction transceiver unit (2), caches the data in a first DDR4 (11), and packages the instructions transmitted by the image acquisition transmission / instruction transceiver unit (2); The second FPGA receives a compressed instruction transmitted by the image acquisition sending / instruction transceiver unit (2) received by the first FPGA (3), sends the instruction to the image acquisition sending / instruction transceiver unit (2) through the first FPGA (3), and is connected to the second DDR4 (6) for storing image data; An image acquisition application and detector command control module (10) sends a control command to the second FPGA and receives data packaged by the second FPGA; The detector (1) is used to convert an external image into a digital image and transmit the digital image to an image acquisition transmission / instruction transceiver unit (2), and transmit a reply command back to the image acquisition transmission / instruction transceiver unit (2) after receiving an instruction from the image acquisition transmission / instruction transceiver unit (2); The detector (1) comprises a plurality of detector cores for converting external images into digital images, the image acquisition transmission / command transceiver unit (2) comprises a plurality of image acquisition transmission / command transceiver modules, all of the detector cores and all of the image acquisition transmission / command transceiver modules are connected in a one-to-one correspondence, and the image acquisition transmission / command transceiver modules are connected to the first FPGA (3).

2. A multi-target high-speed image acquisition system according to claim 1, characterized in that: The first FPGA (3) is a Gigabit optical fiber acquisition and 10 Gigabit optical fiber transmission module, which is connected to all the image acquisition and transmission / command transceiver modules via optical fiber lines.

3. A multi-target high-speed image acquisition system according to claim 2, characterized in that: The Gigabit optical fiber acquisition and 10 Gigabit optical fiber transmission modules receive data transmitted from the image acquisition transmission / instruction transceiver module according to different ports and cache the data in the first DDR4 (11), package the multi-port data image according to the 10 Gigabit optical fiber transmission protocol and send the data to the second FPGA through the 10 Gigabit optical fiber high-speed port, receive instructions transmitted from the image acquisition transmission / instruction transceiver module according to different ports, package them and send them to the second FPGA, receive control instructions from the second FPGA, unpack them and send the corresponding control instructions to the multiple image acquisition transmission / instruction transceiver modules according to different Gigabit ports.

4. A multi-target high-speed image acquisition system according to claim 3, characterized in that: The second FPGA comprises a 10 Gigabit instruction transceiver module (9) and a 10 Gigabit optical fiber acquisition module (4), a DDR4 read / write control module (5), an image data protocol packaging module (7) and a PCIE data read / write control module (8) connected in sequence, the 10 Gigabit optical fiber acquisition module (4) receiving the image data transmitted by the 1 Gigabit optical fiber acquisition and 10 Gigabit optical fiber transmission modules, decompressing and transmitting the compressed image data to the DDR4 read / write control module (5), the DDR4 read / write control module (5) writing and caching the decompressed image data to the second DDR4 (6), and the DDR4 read / write control module (5) reading the image data inside the second DDR4 (6) and transmitting it to the image data According to the protocol packaging module (7), the image data protocol packaging module (7) packages the received image data and transmits it to the image acquisition application and the detector instruction control module (10) through the PCIE data read-write control module (8); the detector instruction control module (10) packages the control instructions through the PCIE data read-write control module (8) and transmits them to the 10 Gigabit instruction transceiver module (9); the 10 Gigabit instruction transceiver module (9) packages the received control instructions according to the protocol and transmits them to the first FPGA (3); the 10 Gigabit instruction transceiver module (9) receives the response instructions sent by the first FPGA (3) and transmits the instructions to the PCIE data read-write control module (8).

5. A multi-target high-speed image acquisition system according to claim 4, characterized in that: The 10 Gigabit optical fiber acquisition module (4) receives and unpacks the image data transmitted by the first FPGA (3) via the 10 Gigabit high-speed interface.

6. A multi-target high-speed image acquisition system according to claim 5, characterized in that: The 10 Gigabit optical fiber acquisition module (4) transmits the decompressed image data to the DDR4 read-write control module (5) through a plurality of write ports, and the DDR4 read-write control module (5) writes the image data according to the addresses of different write ports. The written image data is accessed at different addresses of the second DDR4 (6) according to the control timing of the DDR4 read-write control module (5).

7. A multi-target high-speed image acquisition system according to claim 6, characterized in that: The DDR4 read / write control module (5) transmits the image data to the image data protocol packaging module (7) via a plurality of read ports. The DDR4 read / write control module (5) reads the image data at different addresses of the second DDR4 (6) according to the sending timing of the image data protocol packaging module (7) and sends the reads to the image data protocol packaging module (7).

8. A multi-target high-speed image acquisition system according to claims 1-7, characterized in that: The image acquisition sending / command sending / receiving module of the image acquisition sending / command sending / receiving unit (2) is connected to the first FPGA (3) via a gigabit optical fiber.

9. The multi-target high-speed image acquisition system according to claim 8, characterized in that: The length of the gigabit optical fiber is selected according to actual conditions.

10. The multi-target high-speed image acquisition system according to claim 9, characterized in that: The image acquisition application, the detector command control module (10) and the host computer are connected.

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