Diamond-integrated GaN HEMT and preparation method thereof

Abstract

The invention discloses a GaN HEMT (High Electron Mobility Transistor) integrated with diamond and a preparation method of the GaN HEMT. The GaN HEMT structurally comprises a substrate, a GaN layer, a barrier layer, a metal electrode, a dielectric layer and a diamond heat dissipation layer from bottom to top, the metal electrode comprises a first metal region and a second metal region, and a source electrode, a drain electrode and a gate electrode are arranged in the first metal region; the metal in the second metal region is responsible for leading out the source electrode, the drain electrode and the gate electrode in the first metal region; the dielectric layer and the diamond heat dissipation layer directly grow on the surface of the barrier layer containing the metal electrode; according to the method, the GaN HEMT metal electrode is prepared firstly, then the diamond heat dissipation layer is grown, and meanwhile, the electrode is etched after being led out, so that the electrode of a functional area is prevented from being damaged due to impact of etching gas in the etching process, grid control instability or transistor failure of the GaN HEMT is avoided, the compatibility of diamond integration and the GaN HEMT process is enhanced, and the yield of the GaN HEMT is improved. Meanwhile, the heat dissipation capability and reliability of the device are improved.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular to a diamond-integrated GaN HEMT and a preparation method thereof. Background Art

[0002] GaN HEMT devices have the advantages of high electron mobility and large output current. However, in the actual development and application of GaN HEMT power devices, due to the increasing integration and smaller size of devices, the heat generated by the devices is increasingly concentrated, and the temperature rise inside the devices increases sharply, resulting in severe challenges to the reliability of GaN HEMT devices. The performance advantages of GaN-based power devices under high power output are far from being fully utilized.

[0003] Diamond has a very high thermal conductivity. The thermal conductivity of single crystal diamond at room temperature is as high as 2000W / (m·K). Integrating diamond with GaN helps dissipate heat in GaN HEMT devices and alleviates the performance degradation caused by heat accumulation under high power. The existing technology for integrating diamond on the top of GaN devices is to first grow a diamond heat dissipation layer on the barrier layer, and then expose the source, drain, and gate electrode reserved areas on the barrier layer by etching to prepare source, drain, and gate electrodes. This method will etch the source, drain, and gate functional areas. If over-etched, the barrier layer in the electrode area is likely to be damaged under the bombardment of the etching gas, affecting the reliability of the subsequent device preparation; if the etching is insufficient, the dielectric layer and diamond heat dissipation layer above the barrier layer are not etched cleanly, and there will be residues, which will affect the subsequent electrode preparation. This preparation method of growing diamond first and then preparing metal electrodes has extremely high requirements for the etching process and is uncontrollable in the actual process, resulting in unreliable performance of the prepared GaN HMET device. Summary of the invention

[0004] Technical issues solved:

[0005] The technical problems to be solved in this application are the heat dissipation capability of GaN HEMT in high-power scenarios and the need to improve the reliability of electrode preparation under the diamond heat dissipation layer. Provided are a diamond-integrated GaN HEMT and a preparation method thereof.

[0006] Technical solution:

[0007] A diamond-integrated GaN HEMT, wherein the diamond-integrated GaN HEMT comprises, from bottom to top, a substrate, a GaN layer, a barrier layer, a metal electrode, a dielectric layer and a diamond heat dissipation layer;

[0008] The metal electrode includes a first metal region and a second metal region. The first metal region includes source, drain and gate electrodes. The gate is located between the source electrode and the drain electrode. The source, drain and gate electrodes and the underlying barrier layer form a GaN HEMT. The metal in the second metal region is responsible for leading out the source, drain and gate electrodes in the first metal region respectively.

[0009] The source, drain, gate electrodes of the first metal region and the area between the electrodes are wrapped and covered by a dielectric layer and a diamond heat dissipation layer. The process sequence of the metal electrode, the dielectric layer and the diamond heat dissipation layer is: first prepare the metal electrode, then grow and prepare the dielectric layer, and then grow and prepare the diamond heat dissipation layer;

[0010] The area outside the first metal area is an electrical isolation area, and the electrical isolation area is prepared by ion implantation;

[0011] The dielectric layer and the diamond heat dissipation layer above the metal electrode in the second metal region are etched away to expose the electrode pins;

[0012] The dielectric layer and the diamond heat dissipation layer are located above the barrier layer with the metal electrode and are in close contact with the barrier layer.

[0013] As a preferred technical solution of the present application: the source, drain and gate electrodes in the first metal area are prepared twice, wherein the first preparation method of the source and drain electrodes is to evaporate four layers of metal, namely titanium, aluminum, nickel and gold, from bottom to top, and then anneal to form an alloy to form an ohmic contact with the barrier layer; the first preparation method of the gate electrode is to evaporate two layers of metal, namely nickel and gold, from bottom to top to form a Schottky contact with the barrier layer; the second preparation method of the source, drain and gate electrodes in the first metal area is to prepare them together with the source, drain and gate electrode pins in the second metal area, and evaporate two layers of metal, namely titanium and gold, from bottom to top.

[0014] As a preferred technical solution of the present application: the substrate material is silicon, sapphire or silicon carbide; the barrier layer material is AlGaN.

[0015] As a preferred technical solution of the present application: the material of the diamond heat dissipation layer is polycrystalline diamond, the thickness of the diamond heat dissipation layer is 0.5 μm-2 μm, and the growth temperature of the diamond heat dissipation layer is lower than 600°C.

[0016] As a preferred technical solution of the present application: the material of the dielectric layer is SiN or AlN, and the thickness of the dielectric layer is 10-30 nm.

[0017] As a preferred technical solution of the present application: the thicknesses of the four layers of metal titanium, aluminum, nickel and gold prepared for the first time for the source and drain electrodes in the first metal region are 20nm, 135nm, 40nm and 45nm respectively.

[0018] As a preferred technical solution of the present application: the thicknesses of the two layers of metal nickel and gold prepared for the first time for the gate electrode in the first metal region are 20nm and 200nm respectively.

[0019] As a preferred technical solution of the present application: the second preparation of source, drain and gate electrodes in the first metal area is prepared together with the source, drain and gate electrode pins in the second metal area, and two layers of titanium and gold are evaporated from bottom to top with thicknesses of 20nm and 400nm respectively.

[0020] The present application also discloses a method for preparing any of the above-mentioned diamond-integrated GaN HEMTs, the steps of which are as follows:

[0021] Step 1. Growing a GaN layer on a substrate, and then growing a barrier layer on the GaN layer, placing the sample including the substrate, the GaN layer, and the barrier layer in acetone, anhydrous ethanol, and deionized water in turn, cleaning and drying;

[0022] Step 2. Using photolithography and metal evaporation deposition processes in sequence, source and drain metals are evaporated in the first metal region, and the types of evaporated metals are Ti, Al, Ni and Au from bottom to top; after stripping and cleaning, the sample is placed in an annealing furnace for annealing, so that the four metals form an alloy and form an ohmic contact with the underlying barrier layer;

[0023] Step 3. Using an ion implantation process, electrically isolating the device in the area outside the first metal region;

[0024] Step 4. Using photolithography and metal evaporation deposition processes in sequence, gate metal is evaporated in the first metal region, and the types of evaporated metals are Ni and Au from bottom to top, forming a Schottky contact with the barrier layer;

[0025] Step 5. Using photolithography and metal evaporation deposition processes in sequence, evaporate two layers of titanium and gold metal at the source, drain, and gate electrode pin positions of the first metal region and the second metal region;

[0026] Step 6. Using a PECVD process, a dielectric layer is grown on the barrier layer including the metal electrode;

[0027] Step 7. Using MPCVD process, grow a diamond heat dissipation layer on the dielectric layer;

[0028] Step 8. Continue to grow a mask layer on the diamond heat dissipation layer, use photolithography to pattern the diamond heat dissipation layer, expose the location of the source, drain, and gate electrode pins of the second metal area, and etch the diamond heat dissipation layer and dielectric layer in this area to expose the source, drain, and gate electrode pins.

[0029] Beneficial effects:

[0030] The diamond-integrated GaN HEMT and its preparation method described in this application adopt the above technical solution and have the following technical effects compared with the prior art:

[0031] 1. The present invention provides a method for preparing a diamond-integrated GaN HEMT, in which a diamond heat dissipation layer with high thermal conductivity is arranged on the top of the GaN HEMT. The heat generated by the GaN HEMT in a high-power working scenario can be dissipated from the top high-thermal conductivity diamond heat dissipation layer, thereby achieving effective heat dissipation;

[0032] 2. By preparing the electrode first and then growing the diamond heat dissipation layer, the electrode preparation process is advanced, avoiding the influence of the subsequent diamond etching process on the electrode preparation, and improving the reliability of GaN HEMT electrode preparation. At the same time, the second metal area is set to avoid the barrier layer of the first metal area from being destroyed during the etching process, further improving the stability of the GaN HEMT electrode;

[0033] 3. The present invention provides a method for preparing a diamond-integrated GaN HEMT, which enhances the compatibility of diamond integration and GaN HEMT processes, while improving the heat dissipation capability and reliability of GaN HEMT devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 This is a schematic diagram of the structure of the diamond-integrated GaN HEMT of this application;

[0035] Figure 2 A top view of a diamond-integrated GaN HEMT for this application;

[0036] Figure 3 This is a flow chart of the preparation method of the diamond-integrated GaN HEMT of this application.

[0037] Explanation of the reference numerals: 1. substrate, 2. GaN layer, 3. barrier layer, 4. metal electrode, 5. dielectric layer, 6. diamond heat dissipation layer. DETAILED DESCRIPTION

[0038] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0039] The PECVD in this application is plasma enhanced chemical vapor deposition, plasma enhanced chemical vapor deposition;

[0040] MPCVD stands for microwave plasma enhanced chemical vapor deposition.

[0041] Embodiment 1:

[0042] like Figure 1 and Figure 2 As shown, a diamond-integrated GaN HEMT is shown, wherein the diamond-integrated GaN HEMT comprises, from bottom to top, a substrate 1, a GaN layer 2, a barrier layer 3, a metal electrode 4, a dielectric layer 5 and a diamond heat dissipation layer 6; the barrier layer 3 is made of AlGaN, the diamond heat dissipation layer 6 is made of polycrystalline diamond, the thickness of the diamond heat dissipation layer 6 is 0.5 μm-2 μm, and the thicker the diamond heat dissipation layer is, the better the heat dissipation effect is. In the present invention, the electrode is prepared first, and then the diamond heat dissipation layer is grown, so the process compatibility is high, the thickness of the diamond heat dissipation layer can be higher, the growth temperature of the diamond heat dissipation layer 6 is lower than 600° C., the diamond growth temperature is controlled below 600° C., and the thermal conductivity diamond heat dissipation layer is grown without destroying the barrier layer below. The substrate 1 is made of silicon, sapphire or silicon carbide; the dielectric layer 5 is made of SiN or AlN, and the thickness of the dielectric layer 5 is 10-30 nm.

[0043] The metal electrode 4 includes a first metal region and a second metal region. The first metal region contains source, drain and gate electrodes, which correspond to S, D and G in the figure respectively. The gate is located between the source electrode and the drain electrode. The source, drain and gate electrodes form a GaN HEMT with the underlying barrier layer 3. The metal in the second metal region is responsible for leading out the source, drain and gate electrodes in the first metal region respectively, which correspond to S in the figure respectively. PAD , D PAD , G PAD ;

[0044] The source, drain and gate electrodes in the first metal region are prepared twice, wherein the first preparation method of the source and drain electrodes is to evaporate four layers of metals of titanium, aluminum, nickel and gold from bottom to top, and then anneal to form an alloy to form an ohmic contact with the barrier layer 3, and the thicknesses of the prepared four layers of metals of titanium, aluminum, nickel and gold are 20nm, 135nm, 40nm and 45nm respectively; the first preparation method of the gate electrode is to evaporate two layers of metals of nickel and gold from bottom to top to form a Schottky contact with the barrier layer 3, and the thicknesses of the two layers of metals of nickel and gold prepared for the gate electrode in the first metal region are 20nm and 200nm respectively; the second preparation method of the source, drain and gate electrodes in the first metal region is to prepare them together with the source, drain and gate electrode pins in the second metal region, and evaporate two layers of metals of titanium and gold from bottom to top, and the thicknesses are 20nm and 400nm respectively;

[0045] The source, drain, gate electrodes of the first metal region and the area between the electrodes are wrapped and covered by a dielectric layer 5 and a diamond heat dissipation layer 6. The process sequence of the metal electrode, the dielectric layer and the diamond heat dissipation layer is: first prepare the metal electrode, then grow and prepare the dielectric layer, and then grow and prepare the diamond heat dissipation layer;

[0046] The area outside the first metal area is an electrical isolation area, and the preparation method of the electrical isolation area is ion implantation. Specifically, boron ion implantation can be carried out in two steps. The first step is to implant a beam energy of 30 keV and a boron ion dose of 3×10 14 cm -2 ; The second step is to inject beam energy of 110keV and boron ion dose of 3×10 14 cm -2 ;

[0047] The dielectric layer 5 and the diamond heat dissipation layer 6 above the metal electrode in the second metal region are etched away to expose the electrode pins;

[0048] The dielectric layer 5 and the diamond heat dissipation layer 6 are located above the barrier layer 3 with the metal electrode and are in close contact with it.

[0049] It should be noted that the existing technology for integrating diamond on the top of GaN devices is to first grow a diamond heat dissipation layer on the barrier layer, and then expose the reserved areas for source, drain, and gate electrodes on the barrier layer by etching to prepare source, drain, and gate electrodes. This method will etch the source, drain, and gate functional areas. If over-etched, the barrier layer in the electrode area is likely to be damaged under the bombardment of the etching gas, affecting the reliability of the subsequent device preparation; if the etching is insufficient, the dielectric layer and the diamond heat dissipation layer above the barrier layer are not etched cleanly, and there will be residues, which will affect the subsequent preparation of electrodes. This preparation method of growing diamonds first and then preparing metal electrodes has extremely high requirements for the etching process and is uncontrollable in the actual process, resulting in unreliable performance of the prepared GaN HMET device. In addition, in the method of integrating diamonds on the top, the diamond growth temperature cannot be too high to avoid damage to the barrier layer below.

[0050] In view of this, in the embodiment of the present invention, a high thermal conductivity diamond heat dissipation layer is provided on the top of the GaN HEMT, and the heat generated by the GaN HEMT in a high-power working scenario can be dissipated from the top high thermal conductivity diamond heat dissipation layer, thereby achieving effective heat dissipation. In addition, by preparing the electrode first and then growing the diamond heat dissipation layer, the electrode preparation process is brought forward, avoiding the influence of the subsequent diamond etching process on the electrode preparation, and improving the reliability of the GaN HEMT electrode preparation. At the same time, the second metal region is provided to avoid the first metal region barrier layer from being destroyed during the etching process, further improving the stability of the GaN HEMT electrode. Therefore, the present invention provides a GaN HEMT and a preparation method with an electrode first and a diamond heat dissipation layer later, which enhances the compatibility of diamond integration and GaN HEMT processes, and improves the heat dissipation capacity and reliability of the GaN HEMT device. In addition, in the embodiment of the present invention, the diamond growth temperature is controlled below 600°C, and the thermal conductivity diamond heat dissipation layer is grown without destroying the underlying barrier layer.

[0051] like Figure 3 As shown, a method for preparing a diamond-integrated GaN HEMT comprises the following steps:

[0052] Step 1. A GaN layer 2 is grown on a substrate 1, and then a barrier layer 3 is grown on the GaN layer 2. Specifically, the substrate 1 is a SiC substrate. The sample comprising the SiC substrate, the GaN layer 2, and the barrier layer 3 is sequentially placed in an acetone solution for ultrasonic cleaning for 5 minutes, and then placed in an anhydrous ethanol solution for cleaning for 5 minutes, and finally rinsed with deionized water and dried with a nitrogen gun;

[0053] Step 2. Use photolithography and metal evaporation deposition processes in sequence to evaporate source and drain metals in the first metal region. The types of evaporated metals are Ti, Al, Ni and Au from bottom to top. After stripping and cleaning, place the sample in an annealing furnace for annealing so that the four metals form an alloy and form an ohmic contact with the underlying barrier layer 3. Specifically:

[0054] S21, photolithography of source electrode patterns and drain electrode patterns on the source and drain electrode areas of the first metal region respectively: first bake the sample at 110°C for 2 minutes, then place the sample on a coating table and spin-coat AZ7908 photoresist at a speed of 3000rpm for 30s, and bake the sample at 110°C for 2 minutes; then, place the well-coated sample into a photolithography machine, and expose the source and drain positions of the first metal region; finally, soak the sample in RZX-3038 developer for 30s, then soak it in ultrapure water for 10s, and blow dry it with a nitrogen gun to complete the development;

[0055] S22, evaporation of ohmic metal: first put the developed sample into a plasma degumming machine for base film treatment, with a power of 200W and a treatment time of 2 minutes. Then, put the sample into an electron beam evaporation table. The crystal oscillator in the electron beam evaporation table cavity is greater than 95%. When the vacuum degree of the reaction chamber of the electron beam evaporation table reaches 1×10 6 After Torr, four metals, titanium, aluminum, nickel, and gold, were evaporated in sequence, with thicknesses of 20nm, 135nm, 40nm, and 45nm, respectively. The samples after metal evaporation were then placed in an acetone solution for stripping to remove the ohmic metal, photoresist, and stripping glue outside the source and drain electrode patterns. Finally, the samples were rinsed with anhydrous ethanol solution and ultrapure water, and then dried with nitrogen.

[0056] S23, annealing the peeled sample: placing the peeled sample in a rapid annealing furnace for annealing, the annealing atmosphere is nitrogen, the annealing temperature is 840° C., the annealing time is 30 seconds, and the annealing treatment allows the metal to react with the underlying barrier layer to form an alloy, thereby forming an ohmic contact;

[0057] Step 3. Use the ion implantation process to electrically isolate the device in the area outside the first metal area. Specifically, first bake the sample at 110°C for 2 minutes, then place the sample on the coating table and spin-coat AZ701 photoresist at a speed of 3000rpm for 30s. Bake the sample at 110°C for 2 minutes. Then, place the well-coated sample into the photolithography machine and expose the area outside the first metal area. Finally, soak the sample in RZX-3038 developer for 30s, then soak it in ultrapure water for 10s, and blow it dry with a nitrogen gun to complete the development. Then, place the sample into the implantation machine and implant it in two steps. The first step is to inject a beam energy of 30keV and a boron ion dose of 3×10 14 cm -2 ; The second step is to inject beam energy of 110keV and boron ion dose of 3×10 14 cm -2 ;

[0058] Step 4. Using photolithography and metal evaporation deposition processes in sequence, evaporate gate metal in the first metal region. The types of evaporated metals are Ni and Au from bottom to top, forming a Schottky contact with the barrier layer 3. Specifically:

[0059] S41, photolithography of the gate electrode pattern on the gate electrode area of ​​the first metal region: first bake the sample at 110°C for 2 minutes, then place the sample on a coating table and spin-coat AZ7908 photoresist at a speed of 3000rpm for 30 seconds, and bake the sample at 110°C for 2 minutes; then, place the well-coated sample into a photolithography machine, and expose the source and drain positions of the first metal region; finally, soak the sample in RZX-3038 developer for 30 seconds, then soak it in ultrapure water for 10 seconds, and blow dry it with a nitrogen gun to complete the development;

[0060] S42, evaporation of gate metal: first, place the developed sample in a plasma degumming machine for base film treatment, with a power of 200 W and a treatment time of 2 minutes; then, place the sample in an electron beam evaporation table, with the crystal oscillator in the electron beam evaporation table cavity greater than 95%, and wait until the vacuum degree of the reaction chamber of the electron beam evaporation table reaches 1×10 6 After 1000 Torr, nickel and gold were evaporated in turn, with thicknesses of 20nm and 200nm respectively. The samples after metal evaporation were then placed in an acetone solution for stripping to remove the ohmic metal, photoresist and stripping glue outside the source electrode pattern and drain electrode pattern. Finally, the samples were rinsed with anhydrous ethanol solution and ultrapure water in turn, and then dried with nitrogen.

[0061] Step 5. Using photolithography and metal evaporation deposition process in sequence, evaporate titanium and gold metal layers at the source, drain and gate electrode pin positions of the first metal area and the second metal area. Specifically, refer to step 4, except that the pattern to be photolithographically produced is the source, drain and gate electrode region of the first metal area and the source, drain and gate electrode pin region of the second metal area, and the evaporated metal types are titanium and gold metal layers from bottom to top, with thicknesses of 20nm and 200nm respectively. In addition, the other processes are the same as step 4;

[0062] Step 6. Using the PECVD process, a dielectric layer 5 is grown on the barrier layer 3 including the metal electrode 4, specifically: ammonia and silane are used as reaction gases, the temperature of the epitaxial substrate is 200°C, the pressure of the reaction chamber is 500mTorr, the RF power is 20W, and 30nm SiN is grown;

[0063] Step 7. Using the MPCVD process, a diamond heat dissipation layer 6 is grown on the dielectric layer 5, specifically: a growth temperature of 550°C, a hydrogen flow rate of 200 sccm, a methane flow rate of 22 sccm, an oxygen flow rate of 0.2 sccm, and a 2 μm thick diamond heat dissipation layer is grown;

[0064] Step 8. A mask layer continues to grow on the diamond heat dissipation layer 6, and the diamond heat dissipation layer 6 is patterned by a photolithography process to expose the location of the source, drain, and gate electrode pins of the second metal region, and the diamond heat dissipation layer 6 and the dielectric layer 5 in the region are etched to expose the source, drain, and gate electrode pins: the mask here can be SiN, and 200nm SiN is grown by PECVD, and then the source, drain, and gate electrode pin patterns in the second metal region are photoetched by a photolithography process; then the exposed SiN area is ICP etched, and the detailed process of SiN mask etching can refer to the existing mature technology, and the embodiment of the present invention will not be repeated; after cleaning and removing the photoresist, the SiN mask layer exposes the source, drain, and gate electrode pin areas of the second metal region, and then the exposed diamond heat dissipation layer is etched by an ICP process, and the etching process may include: ICP source power 500W, bias power 50W, oxygen flow rate 80sccm; finally, the 30nmSiN dielectric layer above the barrier layer is etched.

[0065] The above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit the same. There are many practical production methods that can be adopted. All equivalent changes and decorations made according to the claims of the present invention are within the scope of the present invention.

Claims

1. A diamond-integrated GaN HEMT, characterized in that: The diamond-integrated GaN HEMT comprises, from bottom to top, a substrate (1), a GaN layer (2), a barrier layer (3), a metal electrode (4), a dielectric layer (5) and a diamond heat dissipation layer (6); wherein the metal electrode (4) comprises a first metal region and a second metal region, the first metal region contains a source, a drain and a gate electrode, the gate is located between the source electrode and the drain electrode, and the source, drain and gate electrodes and the barrier layer (3) below form a GaN HEMT; the metal in the second metal region is responsible for respectively leading out the source, drain and gate electrodes in the first metal region; The source, drain, gate electrodes of the first metal region and the region between the electrodes are wrapped and covered by a dielectric layer (5) and a diamond heat dissipation layer (6), and the process sequence of the metal electrode, the dielectric layer and the diamond heat dissipation layer is: first prepare the metal electrode, then grow and prepare the dielectric layer, and then grow and prepare the diamond heat dissipation layer; The area outside the first metal area is an electrical isolation area, and the electrical isolation area is prepared by ion implantation; The dielectric layer (5) and the diamond heat dissipation layer (6) above the metal electrode in the second metal region are etched away to expose the electrode pins; The dielectric layer (5) and the diamond heat dissipation layer (6) are located above the barrier layer (3) with the metal electrode and are in close contact with it.

2. The diamond-integrated GaN HEMT according to claim 1, characterized in that: The source, drain and gate electrodes in the first metal region are prepared twice, wherein the first preparation method of the source and drain electrodes is to evaporate four layers of metal, titanium, aluminum, nickel and gold from bottom to top, and then anneal to form an alloy to form an ohmic contact with the barrier layer (3); the first preparation method of the gate electrode is to evaporate two layers of metal, nickel and gold, from bottom to top to form a Schottky contact with the barrier layer (3); the second preparation method of the source, drain and gate electrodes in the first metal region is to prepare them together with the source, drain and gate electrode pins in the second metal region, and evaporate two layers of metal, titanium and gold, from bottom to top.

3. The diamond-integrated GaN HEMT according to claim 1, characterized in that: The material of the substrate (1) is silicon, sapphire or silicon carbide; the material of the barrier layer (3) is AlGaN.

4. The diamond-integrated GaN HEMT according to claim 1, characterized in that: The material of the diamond heat dissipation layer (6) is polycrystalline diamond, the thickness of the diamond heat dissipation layer (6) is 0.5 μm-2 μm, and the growth temperature of the diamond heat dissipation layer (6) is lower than 600° C.

5. The diamond-integrated GaN HEMT according to claim 1, characterized in that: The material of the dielectric layer (5) is SiN or AlN, and the thickness of the dielectric layer (5) is 10-30 nm.

6. The diamond-integrated GaN HEMT according to claim 2, characterized in that: The thicknesses of the four layers of metal titanium, aluminum, nickel and gold prepared for the first time for the source and drain electrodes in the first metal region are 20nm, 135nm, 40nm and 45nm respectively.

7. The diamond-integrated GaN HEMT according to claim 2, characterized in that: The thicknesses of the two layers of nickel and gold prepared for the first time for the gate electrode in the first metal region are 20nm and 200nm respectively.

8. The diamond-integrated GaN HEMT according to claim 2, characterized in that: The second preparation of the source, drain and gate electrodes in the first metal region is prepared together with the source, drain and gate electrode pins in the second metal region, and two layers of titanium and gold are evaporated from bottom to top with thicknesses of 20nm and 400nm respectively.

9. A method for preparing a diamond-integrated GaN HEMT according to any one of claims 1 to 8, characterized in that: Here are the steps: Step 1. Growing a GaN layer (2) on a substrate (1), then growing a barrier layer (3) on the GaN layer (2), and placing a sample comprising the substrate (1), the GaN layer (2), and the barrier layer (3) in acetone, anhydrous ethanol, and deionized water in turn, cleaning and drying; Step 2. Using photolithography and metal evaporation deposition processes in sequence, source and drain metals are evaporated in the first metal region, and the types of evaporated metals are Ti, Al, Ni and Au from bottom to top; after stripping and cleaning, the sample is placed in an annealing furnace for annealing, so that the four metals form an alloy and form an ohmic contact with the underlying barrier layer (3); Step 3. Using an ion implantation process, electrically isolating the device in the area outside the first metal region; Step 4. Sequentially using photolithography and metal evaporation deposition processes, evaporating gate metal in the first metal region, the types of evaporated metals are Ni and Au from bottom to top, forming a Schottky contact with the barrier layer (3); Step 5. Using photolithography and metal evaporation deposition processes in sequence, evaporate two layers of titanium and gold metal at the source, drain, and gate electrode pin positions of the first metal region and the second metal region; Step 6. Using a PECVD process, a dielectric layer (5) is grown on the barrier layer (3) including the metal electrode (4); Step 7. Using the MPCVD process, a diamond heat dissipation layer (6) is grown on the dielectric layer (5); Step 8. A mask layer is further grown on the diamond heat dissipation layer (6), and the diamond heat dissipation layer (6) is patterned using a photolithography process to expose the locations of the source, drain, and gate electrode pins of the second metal region, and the diamond heat dissipation layer (6) and the dielectric layer (5) in this region are etched to expose the source, drain, and gate electrode pins.

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