High-linearity three-dimensional nanowire channel device and preparation method thereof
By introducing nanowire channels and source-drain electrode structures into the polarized doped HEMT, the problem of insufficient linearity of HEMT at high frequency and high power is solved, and high linearity and good gate control capabilities are achieved, which are suitable for high frequency and high power operations.
Patent Information
- Application Number
- CN202411852923.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-16
- Publication Date
- 2025-03-21
AI Technical Summary
Existing GaN high-electron mobility transistors (HEMTs) have insufficient linearity problems under high frequency and high power operation, resulting in signal gain compression, intensified thermal effects and degraded system performance.
By introducing nanowire channels into polarized doped high electron mobility transistors (polFETs) and deeply penetrate the source and drain electrodes into the GaN buffer layer, the contact area is increased to improve source driving capability, suppress the increase in source driving resistance, and improve gate control capability.
It realizes high linearity, wide gate voltage swing and good gate control capabilities, improves the output current and ohmic contact mass of the device, reduces the self-heating effect, and is suitable for high-frequency and high-power operations.
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Figure CN119677129A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the field of microelectronic technology, and in particular relates to a high-linearity three-dimensional nanowire channel device and a preparation method thereof. Background Art
[0002] High electron mobility transistors (HEMTs) have been widely used in high-frequency applications due to their high-density two-dimensional electron gas (2DEG) formed by gallium nitride (GaN)-based heterojunctions. In the radio frequency (RF) front end, gallium nitride (GaN) HEMTs have gradually replaced traditional silicon-based devices due to their excellent performance. In order to ensure the quality of communication, linearity has become a critical parameter in the design of RF systems. Nonlinear effects will lead to saturation of output power at high input power, limit the power handling capacity of the device, and affect the signal gain and efficiency of the RF system. It will also increase the error vector amplitude, worsen the intermodulation distortion, interfere with the main signal, and seriously affect the quality of signal transmission. In addition, nonlinearity will lead to aggravated gain compression and thermal effects under high input signal conditions, which will not only affect the signal amplification capability, but also reduce the dynamic range of the output signal, impairing the performance and service life of the system.
[0003] Device-level linearization is more important than circuit-level linearization technology, because improving linearity from the device itself can reduce dependence on complex circuit compensation and reduce system power consumption and cost. At the same time, device-level linearization directly improves the inherent characteristics of the device, making the entire system more stable and reliable under high-frequency and high-power operation. Circuit-level linearization usually requires additional design and components, which increases system complexity and may introduce more losses. Therefore, optimizing device-level linearity has become the key in RF system design. Therefore, starting from the nonlinear physical mechanism at the device level, it has become a new research hotspot today. At present, a variety of physical mechanisms have been proposed to explain HEMT nonlinearity, such as source starvation, increased source drive resistance, photophonon scattering, interface scattering, trap effect, and self-heating effect. According to different physical mechanisms, researchers have successively proposed different optimization methods.
[0004] Lee et al. first proposed the nanowire channel technology (Lee DS, Wang H, Hsu A, et al. Nanowire channel InAlN / GaN HEMTs with high linearity of gm and fT. IEEE Electron Device Lett, 2013, 34, 969). The core idea is to divide the channel into many small nanowire channels. During the device startup process, the electrons in the nanochannel come from all directions on the source side. Even if the scattering reduces the saturation velocity of electrons between the gate and source, making the electron velocity reach quasi-saturation, the source side can still provide sufficient electrons to the nanochannel. Under a certain current range, the source drive resistance remains basically unchanged, which greatly increases the gate voltage swing (GVS) and improves the linearity of the device.
[0005] In addition, researchers have developed a polarization doped field effect transistor (polFET) (Bajaj S, Yang ZC, Akyol F, et al. Graded AlGaN channel transistors for improved current and power gain linearity. IEEE Trans Electron Devices, 2017, 64, 3114), which expands the two-dimensional electron gas (2DEG) into a three-dimensional electron gas (3DEG) in the vertical direction. Due to the three-dimensional channel, its DC transmission and frequency characteristics show bias insensitivity under the entire low-voltage and high-voltage operating conditions, showing its potential in high-linearity applications. PolFET also has lower current collapse and shows stability to surface states. However, due to the thick barrier layer and the fact that the gate mainly controls the channel on the top layer, the channel on the bottom layer is more difficult to turn off and the gate control capability is poor. Summary of the invention
[0006] In order to overcome the deficiencies of the above-mentioned prior art, the object of the present invention is to provide a high-linearity three-dimensional nanowire channel device and a method for preparing the same, by introducing a nanowire channel into a polarization-doped high electron mobility transistor polFET, and extending the source and drain electrodes from the device surface into the GaN buffer layer, directly contacting the three-dimensional channel while increasing the contact area, so as to enhance the source drive capability, suppress the increase of the source drive resistance, and easily shut down the device, so that the device not only has a wide gate voltage swing (GVS), but also has relatively excellent gate control capability.
[0007] In order to achieve the above object, the technical solution adopted by the present invention is:
[0008] A high linearity three-dimensional nanowire channel device comprises a substrate layer 1, a GaN buffer layer 2 and an AlGaN graded barrier layer 3 which are stacked in sequence from bottom to top, a source electrode 4 and a drain electrode 5 are deposited at both ends of the AlGaN graded barrier layer 3, a Fin gate 6 is deposited on one side of the AlGaN graded barrier layer 3 close to the source electrode 4, a plurality of nanowire channels 7 are arranged on the AlGaN graded barrier layer 3 along the gate width direction, and the Fin gate 6 surrounds the nanowire channel 7.
[0009] The Fin gate 6 is a Ni-AuFin gate of a Fin-HEMT structure with a gate length of 150-250nm.
[0010] A total of 50-70 nanowire channels 7 are arranged under the Fin gate 6, and each nanowire channel 7 is spaced 15-25 nm apart.
[0011] The nanowire channel 7 is a three-dimensional nanowire channel.
[0012] The source electrode 4 and the drain electrode 5 respectively penetrate the AlGaN graded barrier layer 3 and reach the GaN buffer layer 2 .
[0013] A method for preparing a high-linearity three-dimensional nanowire channel device comprises the following steps:
[0014] Step 1, preparing a source electrode 4 at one end of an AlGaN graded barrier layer 3 of an epitaxial substrate, and preparing a drain electrode 5 at the other end of the AlGaN graded barrier layer 3; the epitaxial substrate comprises a substrate layer 1, a GaN buffer layer 2 and an AlGaN graded barrier layer 3 stacked in sequence;
[0015] Step 2, depositing a SiN temporary barrier layer 8 on the device surface, and forming a plurality of strip-shaped SiN temporary barrier layers 8 arranged at intervals between the source electrode 4 and the drain electrode 5 by etching;
[0016] Step 3, developing the outline of the Fin gate after photolithography, and etching away the AlGaN graded barrier layer 3 in the Fin gate region that is not covered by the SiN temporary barrier layer 8;
[0017] Step 4, removing all SiN temporary barrier layers 8, leaving a jagged nanowire channel 7 in the Fin gate region;
[0018] Step 5: deposit metal in the Fin gate region to form a Fin gate 6.
[0019] The specific method of step 1 is:
[0020] Step 1.1, photolithography a source electrode region and a drain electrode region on the AlGaN graded barrier layer 3;
[0021] Step 1.2, etching away the AlGaN graded barrier layer 3 in the source electrode region and the drain electrode region;
[0022] Step 1.3, evaporating ohmic metal on the AlGaN graded barrier layer 3 in the source electrode region and the drain electrode region and on the photoresist outside the source electrode region and the drain electrode region to form a source electrode 4 and a drain electrode 5, stripping the device after the ohmic metal evaporation to remove the ohmic metal and photoresist outside the source electrode 4 and the drain electrode 5, and then rinsing the device with ultrapure water and blowing it dry with nitrogen;
[0023] Step 1.4, placing the device after ohmic metal evaporation and stripping into a rapid thermal annealing furnace for annealing to form an ohmic contact between the ohmic metal and the heterojunction channel.
[0024] The specific method of step 2 is:
[0025] Step 2.1, depositing a 50-60 nm SiN temporary barrier layer 8 on the device surface;
[0026] Step 2.2, except for the source electrode region and the drain electrode region, photolithography is performed to form strip-shaped SiN grooves with different intervals in the SiN temporary barrier layer 8;
[0027] Step 2.3, etching the SiN temporary barrier layer 8 in the source electrode region and the drain electrode region by using an ICP etching process to form a plurality of strip-shaped SiN temporary barrier layers 8 arranged at intervals.
[0028] Compared with the prior art, the present invention has the following advantages:
[0029] 1. The present invention has a gradually changing barrier structure. Since the gate is a Fin structure, the three-dimensional electron gas (3DEG) can be better controlled, and the bottom channel can be easily turned off, so that the threshold voltage will not shift too much negatively.
[0030] 2. The present invention replaces the traditional potential barrier structure with a slowly varying potential barrier structure to transform the traditional two-dimensional nanowire channel into a three-dimensional nanowire channel. More electrons can enter the channel vertically from the source electrode, further improving the source driving capability and suppressing the increase of the source driving resistance.
[0031] 3. The source electrode and the drain electrode of the present invention both penetrate into the GaN buffer layer, and the contact area with the channel is larger. Compared with the traditional surface electrode gradual barrier structure, the present invention has a larger output current and better ohmic contact, and the self-heating effect can also be reduced.
[0032] 4. The method for preparing the high-linearity three-dimensional nanowire channel device of the present invention, combined with the specific structure of the high-linearity three-dimensional nanowire channel device of the present invention, comprehensively utilizes processes such as lithography, evaporation, annealing, and vapor deposition, and selects specific parameters. It has the characteristics of being suitable for large-scale production while comprehensively improving device performance.
[0033] In summary, the present invention has the advantages of high linearity, high output current and better ohmic contact by inserting the source electrode deep into the GaN buffer layer and applying the nanowire channel to the gradual barrier structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0034] FIG1 is a schematic diagram of the structure of the present invention; wherein FIG1(a) is a cross-sectional view of the nanowire channel 7 in the gate width direction of the present invention, and FIG1(b) and FIG1(c) are cross-sectional views in the gate length direction of the present invention.
[0035] Figure 2 It is a preparation process flow chart of the present invention.
[0036] Among them, 1. substrate layer; 2. GaN buffer layer; 3. AlGaN graded barrier layer; 4. source electrode; 5. drain electrode; 6. Fin gate; 7. nanowire channel; 8. SiN temporary barrier layer. DETAILED DESCRIPTION
[0037] 1 , a high linearity three-dimensional nanowire channel device of the present invention comprises: a substrate layer 1, a GaN buffer layer 2, an AlGaN graded barrier layer 3, a source electrode 4, a drain electrode 5, a Fin gate 6, and a nanowire channel 7; wherein the substrate layer 1, the GaN buffer layer 2, and the AlGaN graded barrier layer 3 are stacked in sequence from bottom to top, the source electrode 4 and the drain electrode 5 are deposited at both ends of the AlGaN graded barrier layer 3, respectively, a Fin gate 6 is deposited on one side of the AlGaN graded barrier layer 3 close to the source electrode 4, a plurality of nanowire channels 7 are arranged on the AlGaN graded barrier layer 3 along the gate width direction, and the Fin gate 6 surrounds the nanowire channel 7.
[0038] Among them, the GaN buffer layer 2 is unintentionally doped with 1.7 to 2 μm; the AlGaN graded barrier layer 3 is 70 to 80 nm AlGaN with an Al component of 0 to 35%; the Fin gate 6 is a Ni-Au Fin gate with a Fin-HEMT structure with a gate length of 150 to 250 nm, and the gate in the non-nanowire channel region just cuts off the three-dimensional electron gas (3DEG). A total of 50-70 nanowire channels 7 are arranged under the Fin gate 6, and each nanowire channel 7 is spaced 15 to 25 nm apart; the gate-source spacing is 1 to 1.5 μm, and the gate-drain spacing is 2 to 3 μm.
[0039] The nanowire channel 7 is a three-dimensional nanowire channel.
[0040] The source electrode 4 and the drain electrode 5 respectively penetrate the AlGaN graded barrier layer 3 and reach the GaN buffer layer 2 .
[0041] Reference Figure 2 The preparation method of the present invention is described by the following examples.
[0042] Example 1
[0043] A method for preparing a high-linearity three-dimensional nanowire channel device comprises the following steps:
[0044] Step 1: Obtain an epitaxial substrate, which includes a substrate layer 1, a GaN buffer layer 2 and an AlGaN graded barrier layer 3 stacked in sequence, wherein the substrate layer 1 is a Si substrate.
[0045] Step 2, preparing a source electrode 4 on one end of the AlGaN graded barrier layer 3, and preparing a drain electrode 5 on the other end of the AlGaN graded barrier layer 3;
[0046] Step 2.1, photolithography a source electrode region and a drain electrode region on the AlGaN graded barrier layer 3;
[0047] The epitaxial substrate obtained in step 1 is placed on a hot plate at 180°C and baked for 3 minutes to remove moisture on the epitaxial substrate; then, the AlGaN graded barrier layer 3 is coated with glue, the spinning speed is 4000 rpm, the spinning time is 20s, the spinning thickness is 0.35μm, and the device is placed on a hot plate at 100°C and baked for 2 minutes; the device after the coating and spinning is placed in a photolithography machine for exposure, and the exposed device is placed in a developer to remove the photoresist, and after ultrapure water washing and nitrogen drying, only the photoresist exists outside the source electrode area and the drain electrode area; after development, the device is placed on a hot plate at 110°C and baked for 2 minutes;
[0048] Step 2.2, etching the AlGaN graded barrier layer 3 in the source electrode region and the drain electrode region until the GaN buffer layer 2;
[0049] Step 2.3, evaporating the source electrode 4 and the drain electrode 5 on the AlGaN graded barrier layer 3 in the source electrode region and the drain electrode region and on the photoresist outside the source electrode region and the drain electrode region;
[0050] Place the device in the electron beam evaporation station and wait until the vacuum degree of the reaction chamber of the electron beam evaporation station reaches 2×10 -6After 1000 MHz and 500 MHz, ohmic metal is evaporated on the source electrode region and the drain electrode region and on the photoresist outside the source electrode region and the drain electrode region to form the source electrode 4 and the drain electrode 5. The ohmic metal is Ti / Al / Ni / Au from bottom to top. Then, the device after the ohmic metal evaporation is stripped to remove the ohmic metal and photoresist outside the source electrode 4 and the drain electrode 5. The device is then rinsed with isopropyl alcohol and blown dry with nitrogen.
[0051] Step 2.4, annealing treatment;
[0052] The device after ohmic metal evaporation and stripping is placed in a rapid thermal annealing furnace for annealing to form an ohmic contact between the ohmic metal and the heterojunction channel. The annealing process conditions are: annealing atmosphere is N2, annealing temperature is 810°C, and annealing time is 30s.
[0053] Step 3, depositing a SiN temporary barrier layer 8 on the device surface, and forming a plurality of strip-shaped SiN temporary barrier layers 8 arranged at intervals between the source electrode 4 and the drain electrode 5 by etching;
[0054] Step 3.1, a 50nm SiN temporary barrier layer 8 is deposited on the device surface by plasma enhanced chemical vapor deposition (PECVD), and the growth process conditions are: using N2O and SiH4 as reaction gases, substrate temperature is 250°C, reaction chamber pressure is 600mTorr, and RF power is 22W;
[0055] Step 3.2, except for the source electrode region and the drain electrode region, photolithography is performed to form strip-shaped SiN grooves with different intervals in the SiN temporary barrier layer 8;
[0056] First, bake the device on a hot plate at 180°C for 3 minutes; then, apply and spin the photoresist at a spinning speed of 4000 rpm, and bake the device on a hot plate at 100°C for 2 minutes; then, place the device in an EBL lithography machine for exposure; after exposure, place the device in a developer for 40 seconds, rinse it with isopropanol and blow it dry with nitrogen;
[0057] Step 3.3, using ICP etching process to remove part of the SiN temporary barrier layer 8 in the source electrode area and the drain electrode area, forming a plurality of spaced strip SiN temporary barrier layers 8; the etching conditions are: the reaction gas is CF4 and O2, the reaction chamber pressure is 100mTorr, the RF power of the upper electrode and the lower electrode is 100W and 10W respectively, and the etching depth is 100nm, until the AlGaN graded barrier layer 3 is exposed.
[0058] Step 4, developing the outline of the Fin gate after photolithography, and etching away the AlGaN graded barrier layer 3 in the Fin gate region that is not covered by the SiN temporary barrier layer 8;
[0059] Step 4.1, photolithography and developing the Fin gate area on the device surface;
[0060] The device was placed on a hot plate at 180°C and baked for 3 minutes; then, photoresist was coated and spun, with a spinning speed of 4000 rpm, a spinning time of 20 seconds, and a spinning thickness of 0.35 μm, and the device was placed on a hot plate at 100°C and baked for 2 minutes; the device after coating and spinning was placed in a photolithography machine for exposure, and the exposed device was placed in a developer for development, and after development, the device was placed on a hot plate at 110°C and baked for 2 minutes to form a pattern in which there was no photoresist on the Fin gate area and there was photoresist in other areas;
[0061] Step 4.2, etching away the AlGaN graded barrier layer 3 in the Fin gate region that is not covered by the SiN temporary barrier layer 8;
[0062] The AlGaN graded barrier layer 3 in the Fin gate region not covered by the SiN temporary barrier layer 8 is etched using the ICP process; the process conditions are: the reaction gases are Cl2 and BCl3, the reaction chamber pressure is 100mTorr, the RF powers of the upper and lower electrodes are 100W and 10W respectively, and the etching depth is 80nm.
[0063] Step 5, using BOE solution to etch away the SiN temporary barrier layer 8 in the gate region, leaving a jagged nanowire channel 7 in the Fin gate region;
[0064] Step 6: depositing metal in the Fin gate region to form a Fin gate 6.
[0065] Step 6.1, bake the device on a hot plate at 180°C for 3 minutes; then, apply and spin the photoresist at a spinning speed of 4000 rpm, and bake the device on a hot plate at 100°C for 2 minutes; then, place the device in an EBL lithography machine for exposure; finally, place the exposed device in a developer for 40 seconds, rinse it with isopropanol and blow it dry with nitrogen, and after drying, bake the device on a hot plate at 110°C for 2 minutes to form a pattern in which there is no photoresist on the Fin gate area and there is photoresist in other areas;
[0066] Step 6.2: Place the device in the electron beam evaporation station and wait until the vacuum degree of the reaction chamber of the electron beam evaporation station reaches 2×10 -6 After Torr, gate metal is evaporated on the photoresist in the gate area and outside the gate area, and the metal is Ni / Au from bottom to top; then, the device after the gate metal evaporation is stripped, and then the device is rinsed with isopropyl alcohol and blown dry with nitrogen to form a Fin gate 6.
[0067] The high-linearity three-dimensional nanowire channel device prepared in this embodiment 1 has a barrier structure with a 70nm Al component gradient, 50 three-dimensional nanowire channels, a gate length of 150nm, a source electrode 4 and a drain electrode 5 deep into the GaN buffer layer 2, a gate voltage swing (GVS) of more than 4V, and a threshold voltage of more than -4.5V.
[0068] Example 2
[0069] A method for preparing a high-linearity three-dimensional nanowire channel device comprises the following steps:
[0070] Step 1: Obtain an epitaxial substrate, which includes a substrate layer 1, a GaN buffer layer 2 and an AlGaN graded barrier layer 3 stacked in sequence, wherein the substrate layer 1 is a GaN substrate.
[0071] Step 2, preparing a source electrode 4 on one end of the AlGaN graded barrier layer 3, and preparing a drain electrode 5 on the other end of the AlGaN graded barrier layer 3;
[0072] Step 2.1, photolithography a source electrode region and a drain electrode region on the AlGaN graded barrier layer 3;
[0073] The epitaxial substrate obtained in step 1 is placed on a hot plate at 200° C. and baked for 2 minutes to remove moisture on the epitaxial substrate; then, the AlGaN graded barrier layer 3 is coated with glue, and the spinning speed is 2000 rpm, the spinning time is 40 seconds, the spinning thickness is 0.35 μm, and the device is placed on a hot plate at 100° C. and baked for 3 minutes; the device after the coating and spinning is placed in a photolithography machine for exposure, and the exposed device is placed in a developer to remove the photoresist, and after ultrapure water washing and nitrogen drying, only the photoresist exists outside the source electrode area and the drain electrode area, and after development, the device is placed on a hot plate at 110° C. and baked for 2 minutes;
[0074] Step 2.2, etching the AlGaN graded barrier layer 3 in the source electrode region and the drain electrode region until the GaN buffer layer 2;
[0075] Step 2.3, evaporating the source electrode 4 and the drain electrode 5 on the AlGaN graded barrier layer 3 in the source electrode region and the drain electrode region and on the photoresist outside the source electrode region and the drain electrode region;
[0076] Place the device in the electron beam evaporation station and wait until the vacuum degree of the reaction chamber of the electron beam evaporation station reaches 2×10 -6After 1000 MHz and 500 MHz, ohmic metal is evaporated on the source electrode region and the drain electrode region and on the photoresist outside the source electrode region and the drain electrode region to form the source electrode 4 and the drain electrode 5. The ohmic metal is Ti / Al / Ni / Au from bottom to top. Then, the device after the ohmic metal evaporation is stripped to remove the ohmic metal and photoresist outside the source electrode 4 and the drain electrode 5. The device is then rinsed with isopropyl alcohol and blown dry with nitrogen.
[0077] Step 2.4, annealing treatment;
[0078] The device after ohmic metal evaporation and stripping is placed in a rapid thermal annealing furnace for annealing to form an ohmic contact between the ohmic metal and the heterojunction channel. The annealing process conditions are: annealing atmosphere is N2, annealing temperature is 820°C, and annealing time is 30s.
[0079] Step 3, depositing a SiN temporary barrier layer 8 on the device surface, and forming a plurality of strip-shaped SiN temporary barrier layers 8 arranged at intervals between the source electrode 4 and the drain electrode 5 by etching;
[0080] Step 3.1, a 60nm SiN temporary barrier layer 8 is deposited on the device surface by plasma enhanced chemical vapor deposition (PECVD), and the growth process conditions are: using N2O and SiH4 as reaction gases, substrate temperature is 250°C, reaction chamber pressure is 600mTorr, and RF power is 22W;
[0081] Step 3.2, except for the source electrode region and the drain electrode region, photolithography is performed to form strip-shaped SiN grooves with different intervals in the SiN temporary barrier layer 8;
[0082] First, bake the device on a hot plate at 200°C for 2 minutes; then, apply and spin the photoresist at a spinning speed of 2000 rpm, and bake the device on a hot plate at 100°C for 3 minutes; then, place the device in an EBL lithography machine for exposure; after exposure, place the device in a developer for 40 seconds, rinse it with isopropanol and blow it dry with nitrogen;
[0083] Step 3.3, using ICP etching process to remove part of the SiN temporary barrier layer 8 in the source electrode area and the drain electrode area, forming a plurality of spaced strip SiN temporary barrier layers 8; the etching conditions are: the reaction gas is CF4 and O2, the reaction chamber pressure is 100mTorr, the RF power of the upper electrode and the lower electrode is 100W and 10W respectively, and the etching depth is 120nm, until the AlGaN graded barrier layer 3 is exposed.
[0084] Step 4, developing the outline of the Fin gate after photolithography, and etching away the AlGaN graded barrier layer 3 in the Fin gate region that is not covered by the SiN temporary barrier layer 8;
[0085] Step 4.1, photolithography and developing the Fin gate area on the device surface;
[0086] The device was placed on a hot plate at 200°C and baked for 2 minutes; then, photoresist was coated and spun, with a spinning speed of 2000 rpm, a spinning time of 40 seconds, and a spinning thickness of 0.35 μm, and the device was placed on a hot plate at 100°C and baked for 3 minutes; the device after coating and spun was placed in a photolithography machine for exposure, and the exposed device was placed in a developer for development, and after development, the device was placed on a hot plate at 110°C and baked for 2 minutes to form a pattern in which there was no photoresist on the Fin gate area and there was photoresist in other areas;
[0087] Step 4.2, etching away the AlGaN graded barrier layer 3 in the Fin gate region that is not covered by the SiN temporary barrier layer 8;
[0088] The AlGaN graded barrier layer 3 in the Fin gate region not covered by the SiN temporary barrier layer 8 is etched using the ICP process; the process conditions are: the reaction gases are Cl2 and BCl3, the reaction chamber pressure is 100mTorr, the RF powers of the upper and lower electrodes are 100W and 10W respectively, and the etching depth is 90nm.
[0089] Step 5, using BOE solution to etch away the SiN temporary barrier layer 8 in the gate region, leaving a jagged nanowire channel 7 in the Fin gate region;
[0090] Step 6: depositing metal in the Fin gate region to form a Fin gate 6.
[0091] Step 6.1, bake the device on a hot plate at 200°C for 2 minutes; then, apply and spin the photoresist at a spinning speed of 2000 rpm, and bake the device on a hot plate at 100°C for 2 minutes; then, place the device in an EBL lithography machine for exposure; finally, place the exposed device in a developer for 40 seconds, rinse it with isopropanol and blow it dry with nitrogen, and after drying, bake the device on a hot plate at 110°C for 2 minutes to form a pattern in which there is no photoresist on the Fin gate area and there is photoresist in other areas;
[0092] Step 6.2: Place the device in the electron beam evaporation station and wait until the vacuum degree of the reaction chamber of the electron beam evaporation station reaches 2×10 -6 After Torr, gate metal is evaporated on the photoresist in the gate area and outside the gate area, and the metal is Ni / Au from bottom to top; then, the device after the gate metal evaporation is stripped, and then the device is rinsed with isopropyl alcohol and blown dry with nitrogen to form a Fin gate 6.
[0093] The high-linearity three-dimensional nanowire channel device prepared in this embodiment 2 has a barrier structure with a 75nm Al component gradient, 60 three-dimensional nanowire channels, a gate length of 200nm, a source electrode 4 and a drain electrode 5 deep into the GaN buffer layer 2, a gate voltage swing (GVS) of more than 4V, and a threshold voltage of more than -4.5V.
[0094] Example 3
[0095] A method for preparing a high-linearity three-dimensional nanowire channel device comprises the following steps:
[0096] Step 1: Obtain an epitaxial substrate, which includes a substrate layer 1, a GaN buffer layer 2 and an AlGaN graded barrier layer 3 stacked in sequence, wherein the substrate layer 1 is a SiC substrate.
[0097] Step 2, preparing a source electrode 4 on one end of the AlGaN graded barrier layer 3, and preparing a drain electrode 5 on the other end of the AlGaN graded barrier layer 3;
[0098] Step 2.1, photolithography a source electrode region and a drain electrode region on the AlGaN graded barrier layer 3;
[0099] The epitaxial substrate obtained in step 1 is placed on a hot plate at 180° C. and baked for 3 minutes to remove moisture on the epitaxial substrate; then, the AlGaN graded barrier layer 3 is coated with glue, and the spinning speed is 4000 rpm, the spinning time is 20 seconds, the spinning thickness is 0.35 μm, and the device is placed on a hot plate at 100° C. and baked for 2 minutes; the device after the coating and spinning is placed in a photolithography machine for exposure, and the exposed device is placed in a developer to remove the photoresist, and after ultrapure water washing and nitrogen drying, only the photoresist exists outside the source electrode area and the drain electrode area, and after development, the device is placed on a hot plate at 110° C. and baked for 2 minutes;
[0100] Step 2.2, etching the AlGaN graded barrier layer 3 in the source electrode region and the drain electrode region until the GaN buffer layer 2;
[0101] Step 2.3, evaporating the source electrode 4 and the drain electrode 5 on the AlGaN graded barrier layer 3 in the source electrode region and the drain electrode region and on the photoresist outside the source electrode region and the drain electrode region;
[0102] Place the device in the electron beam evaporation station and wait until the vacuum degree of the reaction chamber of the electron beam evaporation station reaches 2×10 -6After 1000 Å, ohmic metal is evaporated on the source electrode region and the drain electrode region and on the photoresist outside the source electrode region and the drain electrode region to form a source electrode 4 and a drain electrode 5, and the ohmic metal is Ti / Al from bottom to top; then, the device after the ohmic metal evaporation is stripped to remove the ohmic metal and photoresist outside the source electrode 4 and the drain electrode 5, and then the device is rinsed with isopropyl alcohol and blown dry with nitrogen;
[0103] Step 2.4, annealing treatment;
[0104] The device after ohmic metal evaporation and stripping is placed in a rapid thermal annealing furnace for annealing to form an ohmic contact between the ohmic metal and the heterojunction channel. The annealing process conditions are: annealing atmosphere is N2, annealing temperature is 580°C, and annealing time is 30s.
[0105] Step 3, depositing a SiN temporary barrier layer 8 on the device surface, and forming a plurality of strip-shaped SiN temporary barrier layers 8 arranged at intervals between the source electrode 4 and the drain electrode 5 by etching;
[0106] Step 3.1, a 60nm SiN temporary barrier layer 8 is deposited on the device surface by plasma enhanced chemical vapor deposition (PECVD), and the growth process conditions are: using N2O and SiH4 as reaction gases, substrate temperature is 250°C, reaction chamber pressure is 600mTorr, and RF power is 22W;
[0107] Step 3.2, except for the source electrode region and the drain electrode region, photolithography is performed to form strip-shaped SiN grooves with different intervals in the SiN temporary barrier layer 8;
[0108] First, bake the device on a hot plate at 180°C for 3 minutes; then, apply and spin the photoresist at a spinning speed of 4000 rpm, and bake the device on a hot plate at 100°C for 3 minutes; then, place the device in an EBL lithography machine for exposure; after exposure, place the device in a developer for 40 seconds, rinse it with isopropanol and blow it dry with nitrogen;
[0109] Step 3.3, using ICP etching process to remove part of the SiN temporary barrier layer 8 in the source electrode area and the drain electrode area, forming a plurality of spaced strip-shaped SiN temporary barrier layers 8; the etching conditions are: the reaction gas is CF4 and O2, the reaction chamber pressure is 100mTorr, the RF power of the upper electrode and the lower electrode is 100W and 10W respectively, and the etching depth is 70nm, until the AlGaN graded barrier layer 3 is exposed.
[0110] Step 4, developing the outline of the Fin gate after photolithography, and etching away the AlGaN graded barrier layer 3 in the Fin gate region that is not covered by the SiN temporary barrier layer 8;
[0111] Step 4.1, photolithography and developing the Fin gate area on the device surface;
[0112] The device was placed on a hot plate at 180°C and baked for 3 minutes; then, photoresist was coated and spun, with a spinning speed of 4000 rpm, a spinning time of 20 seconds, and a spinning thickness of 0.35 μm, and the device was placed on a hot plate at 100°C and baked for 3 minutes; the device after coating and spinning was placed in a photolithography machine for exposure, and the exposed device was placed in a developer for development, and after development, the device was placed on a hot plate at 110°C and baked for 2 minutes to form a pattern in which there was no photoresist on the Fin gate area and there was photoresist in other areas;
[0113] Step 4.2, etching away the AlGaN graded barrier layer 3 in the Fin gate region that is not covered by the SiN temporary barrier layer 8;
[0114] The AlGaN graded barrier layer 3 in the Fin gate region not covered by the SiN temporary barrier layer 8 is etched using the ICP process; the process conditions are: the reaction gases are Cl2 and BCl3, the reaction chamber pressure is 100mTorr, the RF powers of the upper and lower electrodes are 100W and 10W respectively, and the etching depth is 80nm.
[0115] Step 5, using BOE solution to etch away the SiN temporary barrier layer 8 in the gate region, leaving a jagged nanowire channel 7 in the Fin gate region;
[0116] Step 6: depositing metal in the Fin gate region to form a Fin gate 6.
[0117] Step 6.1, bake the device on a hot plate at 180°C for 3 minutes; then, apply and spin the photoresist at a spinning speed of 4000 rpm, and bake the device on a hot plate at 100°C for 2 minutes; then, place the device in an EBL lithography machine for exposure; finally, place the exposed device in a developer for 40 seconds, rinse it with isopropanol and blow it dry with nitrogen, and after drying, bake the device on a hot plate at 110°C for 2 minutes to form a pattern in which there is no photoresist on the Fin gate area and there is photoresist in other areas;
[0118] Step 6.2: Place the device in the electron beam evaporation station and wait until the vacuum degree of the reaction chamber of the electron beam evaporation station reaches 2×10 -6 After Torr, gate metal is evaporated on the photoresist in the gate area and outside the gate area, and the metal is Ni / Au from bottom to top; then, the device after the gate metal evaporation is stripped, and then the device is rinsed with isopropyl alcohol and blown dry with nitrogen to form a Fin gate 6.
[0119] The device manufactured by the process steps of the present invention has a high gate voltage swing (GVS), excellent dual-tone performance, high linearity and a relatively positive threshold voltage.
[0120] The high linearity three-dimensional nanowire channel device prepared in this embodiment has a barrier structure with a gradually changing Al component of 80nm, 70 three-dimensional nanowire channels, a gate length of 250nm, a source electrode 4 and a drain electrode 5 deep into the GaN buffer layer 2 manufactured by low temperature annealing, a gate voltage swing (GVS) of more than 4V, and a threshold voltage of more than -4.5V.
Claims
1. A high linearity three-dimensional nanowire channel device, characterized in that: The invention comprises a substrate layer (1), a GaN buffer layer (2) and an AlGaN gradual barrier layer (3) which are stacked in sequence from bottom to top; a source electrode (4) and a drain electrode (5) are deposited at two ends of the AlGaN gradual barrier layer (3), a Fin gate (6) is deposited on one side of the AlGaN gradual barrier layer (3) close to the source electrode (4); a plurality of nanowire channels (7) are arranged on the AlGaN gradual barrier layer (3) along a gate width direction, and the Fin gate (6) surrounds the nanowire channels (7).
2. A high linearity three-dimensional nanowire channel device according to claim 1, characterized in that: The Fin gate (6) is a Ni-Au Fin gate of a Fin-HEMT structure with a gate length of 150-250nm.
3. A high linearity three-dimensional nanowire channel device according to claim 1 or 2, characterized in that: A total of 50 to 70 nanowire channels (7) are arranged under the Fin gate (6), and the interval between each nanowire channel (7) is 15 to 25 nm.
4. The high linearity three-dimensional nanowire channel device according to claim 1, characterized in that: The nanowire channel (7) is a three-dimensional nanowire channel.
5. The high linearity three-dimensional nanowire channel device according to claim 1, characterized in that: The source electrode (4) and the drain electrode (5) respectively penetrate the AlGaN graded potential barrier layer (3) to the GaN buffer layer (2).
6. A method for preparing a high linearity three-dimensional nanowire channel device, characterized in that: The following steps are involved: Step 1, preparing a source electrode 4 at one end of an AlGaN graded barrier layer (3) of an epitaxial substrate, and preparing a drain electrode (5) at the other end of the AlGaN graded barrier layer (3); the epitaxial substrate comprises a substrate layer (1), a GaN buffer layer (2) and an AlGaN graded barrier layer (3) stacked in sequence; Step 2, depositing a SiN temporary barrier layer (8) on the device surface, and forming a plurality of strip-shaped SiN temporary barrier layers (8) arranged at intervals between the source electrode (4) and the drain electrode (5) by etching; Step 3, developing the outline of the Fin gate after photolithography, and etching away the AlGaN graded barrier layer (3) in the Fin gate region that is not covered by the SiN temporary barrier layer (8); Step 4, removing all SiN temporary barrier layers (8), leaving a jagged nanowire channel (7) in the Fin gate region; Step 5: depositing metal in the Fin gate region to form a Fin gate (6).
7. The method for preparing a high linearity three-dimensional nanowire channel device according to claim 6, characterized in that: The specific method of step 1 is: Step 1.1, photolithography a source electrode region and a drain electrode region on the AlGaN graded barrier layer (3); Step 1.2, etching away the AlGaN graded barrier layer (3) in the source electrode region and the drain electrode region; Step 1.3, evaporating an ohmic metal on the AlGaN graded barrier layer (3) in the source electrode region and the drain electrode region and on the photoresist outside the source electrode region and the drain electrode region to form a source electrode (4) and a drain electrode (5); stripping the device after the ohmic metal evaporation to remove the ohmic metal and the photoresist outside the source electrode (4) and the drain electrode (5), and then rinsing the device with ultrapure water and blowing it dry with nitrogen; Step 1.4, placing the device after ohmic metal evaporation and stripping into a rapid thermal annealing furnace for annealing; forming an ohmic contact between the ohmic metal and the heterojunction channel.
8. The method for preparing a high linearity three-dimensional nanowire channel device according to claim 6, characterized in that: The specific method of step 2 is: Step 2.1, depositing a 50-60 nm SiN temporary barrier layer (8) on the device surface; Step 2.2, except for the source electrode region and the drain electrode region, photolithography is performed to form strip-shaped SiN grooves with different intervals in the SiN temporary barrier layer (8); Step 2.3, etching the SiN temporary barrier layer (8) in the source electrode region and the drain electrode region using an ICP etching process to form a plurality of strip-shaped SiN temporary barrier layers (8) arranged at intervals.
9. The method for preparing a high linearity three-dimensional nanowire channel device according to claim 6, characterized in that: The following steps are involved: Step 1, preparing a source electrode (4) at one end of an AlGaN graded barrier layer (3) of an epitaxial substrate, and preparing a drain electrode (5) at the other end of the AlGaN graded barrier layer (3); the epitaxial substrate comprises a substrate layer (1), a GaN buffer layer (2) and an AlGaN graded barrier layer (3) stacked in sequence; specifically: Step 1.1, photolithography a source electrode region and a drain electrode region on the AlGaN graded barrier layer (3); The epitaxial substrate is placed on a hot plate at 180° C. and baked for 3 minutes to remove moisture on the epitaxial substrate; then, a glue is applied on the AlGaN graded barrier layer (3), the glue spinning speed is 4000 rpm, the glue spinning time is 20 seconds, the glue spinning thickness is 0.35 μm, and the device is placed on a hot plate at 100° C. and baked for 2 minutes; the device after the glue coating and glue spinning is placed in a photolithography machine for exposure, and the device after the exposure is placed in a developer to remove the photoresist, and after the device is rinsed with ultrapure water and blown dry with nitrogen, the photoresist is only present outside the source electrode region and the drain electrode region; After development, the device was placed on a hot plate and baked at 110°C for 2 min; Step 1.2, etching the AlGaN graded barrier layer (3) in the source electrode region and the drain electrode region until the GaN buffer layer (2); Step 1.3, evaporating a source electrode (4) and a drain electrode (5) on the AlGaN graded barrier layer (3) in the source electrode region and the drain electrode region and on the photoresist outside the source electrode region and the drain electrode region; Place the device in the electron beam evaporation station and wait until the vacuum degree of the reaction chamber of the electron beam evaporation station reaches 2×10 -6 After evaporating 1000 Ω / min at 400 MHz, 100 MHz and 80 MHz, 100 MHz and 80 MHz respectively, evaporating ohmic metal on the source electrode region and the drain electrode region and on the photoresist outside the source electrode region and the drain electrode region to form a source electrode (4) and a drain electrode (5), wherein the ohmic metal is Ti / Al / Ni / Au from bottom to top; then, stripping the device after the ohmic metal evaporation is completed to remove the ohmic metal and the photoresist outside the source electrode (4) and the drain electrode (5), and then washing the device with isopropyl alcohol and drying it with nitrogen; Step 1.4, annealing treatment; The device after ohmic metal evaporation and stripping is placed in a rapid thermal annealing furnace for annealing to form an ohmic contact between the ohmic metal and the heterojunction channel. The annealing process conditions are: annealing atmosphere is N2, annealing temperature is 810°C, and annealing time is 30s; Step 2, depositing a SiN temporary barrier layer (8) on the device surface, and etching to form a plurality of spaced-apart strip-shaped SiN temporary barrier layers 8 between the source electrode (4) and the drain electrode (5); specifically: Step 2.1, depositing a 50 nm SiN temporary barrier layer (8) on the device surface by plasma enhanced chemical vapor deposition (PECVD), wherein the growth process conditions are: using N2O and SiH4 as reaction gases, substrate temperature of 250°C, reaction chamber pressure of 600 mTorr, and RF power of 22 W; Step 2.2, except for the source electrode region and the drain electrode region, photolithography is performed to form strip-shaped SiN grooves with different intervals in the SiN temporary barrier layer (8); First, bake the device on a hot plate at 180°C for 3 minutes; then, apply and spin the photoresist at a spinning speed of 4000 rpm, and bake the device on a hot plate at 100°C for 2 minutes; then, place the device in an EBL lithography machine for exposure; after exposure, place the device in a developer for 40 seconds, rinse it with isopropanol and blow it dry with nitrogen; Step 2.3, using an ICP etching process to remove part of the SiN temporary barrier layer (8) in the source electrode region and the drain electrode region, to form a plurality of strip-shaped SiN temporary barrier layers (8) arranged at intervals; the etching conditions are: the reaction gases are CF4 and O2, the reaction chamber pressure is 100 mTorr, the RF power of the upper electrode and the lower electrode are 100 W and 10 W respectively, and the etching depth is 100 nm, until the AlGaN graded barrier layer (3) is exposed; Step 3, developing the outline of the Fin gate after photolithography, and etching away the AlGaN graded barrier layer (3) in the Fin gate region that is not covered by the SiN temporary barrier layer (8); specifically, Step 3.1, photolithography and developing the Fin gate area on the device surface; The device was placed on a hot plate at 180°C and baked for 3 minutes; then, photoresist was coated and spun, with a spinning speed of 4000 rpm, a spinning time of 20 seconds, and a spinning thickness of 0.35 μm, and the device was placed on a hot plate at 100°C and baked for 2 minutes; the device after coating and spinning was placed in a photolithography machine for exposure, and the exposed device was placed in a developer for development, and after development, the device was placed on a hot plate at 110°C and baked for 2 minutes to form a pattern in which there was no photoresist on the Fin gate area and there was photoresist in other areas; Step 3.2, etching away the AlGaN graded barrier layer (3) in the Fin gate region that is not covered by the SiN temporary barrier layer (8); The AlGaN graded barrier layer (3) in the Fin gate region which is not covered by the SiN temporary barrier layer (8) is etched using an ICP process; the process conditions are: the reaction gases are Cl2 and BCl3, the reaction chamber pressure is 100 mTorr, the radio frequency powers of the upper electrode and the lower electrode are 100 W and 10 W respectively, and the etching depth is 80 nm; Step 4, using BOE solution to etch away the SiN temporary barrier layer (8) in the gate region, leaving a jagged nanowire channel (7) in the Fin gate region; Step 5, depositing metal in the Fin gate region to form a Fin gate (6); specifically: Step 5.1, bake the device on a hot plate at 180°C for 3 minutes; then, apply and spin the photoresist at a spinning speed of 4000 rpm, and bake the device on a hot plate at 100°C for 2 minutes; then, place the device in an EBL lithography machine for exposure; finally, place the exposed device in a developer for 40 seconds, rinse it with isopropanol and blow it dry with nitrogen, and after drying, bake the device on a hot plate at 110°C for 2 minutes to form a pattern in which there is no photoresist on the Fin gate area and there is photoresist in other areas; Step 5.2: Place the device in the electron beam evaporation station and wait until the vacuum degree of the reaction chamber of the electron beam evaporation station reaches 2×10 - 6 After Torr, gate metal is evaporated on the photoresist in the gate area and outside the gate area, and the metal is Ni / Au from bottom to top; then, the device after the gate metal evaporation is stripped, and then the device is rinsed with isopropyl alcohol and blown dry with nitrogen to form a Fin gate (6).
10. The method for preparing a high linearity three-dimensional nanowire channel device according to claim 6, characterized in that: The following steps are involved: Step 1, preparing a source electrode (4) at one end of an AlGaN graded barrier layer (3) of an epitaxial substrate, and preparing a drain electrode (5) at the other end of the AlGaN graded barrier layer (3); the epitaxial substrate comprises a substrate layer (1), a GaN buffer layer (2) and an AlGaN graded barrier layer (3) stacked in sequence; specifically: Step 1.1, photolithography a source electrode region and a drain electrode region on the AlGaN graded barrier layer (3); The epitaxial substrate is placed on a hot plate at 200° C. and baked for 2 minutes to remove moisture on the epitaxial substrate; then, a glue is applied on the AlGaN graded barrier layer (3), the glue spinning speed is 2000 rpm, the glue spinning time is 40 seconds, the glue spinning thickness is 0.35 μm, and the device is placed on a hot plate at 100° C. and baked for 3 minutes; the device after the glue coating and glue spinning is placed in a photolithography machine for exposure, and the device after the exposure is placed in a developer to remove the photoresist, and after the device is rinsed with ultrapure water and blown dry with nitrogen, only the photoresist is left outside the source electrode region and the drain electrode region, and after development, the device is placed on a hot plate at 110° C. and baked for 2 minutes; Step 1.2, etching the AlGaN graded barrier layer (3) in the source electrode region and the drain electrode region until the GaN buffer layer (2); Step 1.3, evaporating a source electrode (4) and a drain electrode (5) on the AlGaN graded barrier layer (3) in the source electrode region and the drain electrode region and on the photoresist outside the source electrode region and the drain electrode region; Place the device in the electron beam evaporation station and wait until the vacuum degree of the reaction chamber of the electron beam evaporation station reaches 2×10 -6 After evaporating 1000 Ω / min at 400 MHz, 100 MHz and 80 MHz, 100 MHz and 80 MHz respectively, evaporating ohmic metal on the source electrode region and the drain electrode region and on the photoresist outside the source electrode region and the drain electrode region to form a source electrode (4) and a drain electrode (5), wherein the ohmic metal is Ti / Al / Ni / Au from bottom to top; then, stripping the device after the ohmic metal evaporation is completed to remove the ohmic metal and the photoresist outside the source electrode (4) and the drain electrode (5), and then washing the device with isopropyl alcohol and drying it with nitrogen; Step 1.4, annealing treatment; The device after ohmic metal evaporation and stripping is placed in a rapid thermal annealing furnace for annealing to form an ohmic contact between the ohmic metal and the heterojunction channel. The annealing process conditions are: annealing atmosphere is N2, annealing temperature is 820°C, and annealing time is 30s; Step 2, depositing a SiN temporary barrier layer (8) on the device surface, and etching to form a plurality of strip-shaped SiN temporary barrier layers (8) arranged at intervals between the source electrode (4) and the drain electrode (5); specifically: Step 2.1, depositing a 60 nm SiN temporary barrier layer (8) on the device surface by plasma enhanced chemical vapor deposition (PECVD), the growth process conditions of which are: using N2O and SiH4 as reaction gases, substrate temperature of 250°C, reaction chamber pressure of 600 mTorr, and RF power of 22 W; Step 2.2, except for the source electrode region and the drain electrode region, photolithography is performed to form strip-shaped SiN grooves with different intervals in the SiN temporary barrier layer (8); First, bake the device on a hot plate at 200°C for 2 minutes; then, apply and spin the photoresist at a spinning speed of 2000 rpm, and bake the device on a hot plate at 100°C for 3 minutes; then, place the device in an EBL lithography machine for exposure; after exposure, place the device in a developer for 40 seconds, rinse it with isopropanol and blow it dry with nitrogen; Step 2.3, using an ICP etching process to remove part of the SiN temporary barrier layer (8) in the source electrode region and the drain electrode region, to form a plurality of strip-shaped SiN temporary barrier layers (8) arranged at intervals; the etching conditions are: the reaction gases are CF4 and O2, the reaction chamber pressure is 100 mTorr, the RF power of the upper electrode and the lower electrode are 100 W and 10 W respectively, and the etching depth is 120 nm, until the AlGaN graded barrier layer (3) is exposed; Step 3, developing the outline of the Fin gate after photolithography, and etching away the AlGaN graded barrier layer (3) in the Fin gate region that is not covered by the SiN temporary barrier layer (8); specifically, Step 3.1, photolithography and developing the Fin gate area on the device surface; The device was placed on a hot plate at 200°C and baked for 2 minutes; then, photoresist was coated and spun, with a spinning speed of 2000 rpm, a spinning time of 40 seconds, and a spinning thickness of 0.35 μm, and the device was placed on a hot plate at 100°C and baked for 3 minutes; the device after coating and spun was placed in a photolithography machine for exposure, and the exposed device was placed in a developer for development, and after development, the device was placed on a hot plate at 110°C and baked for 2 minutes to form a pattern in which there was no photoresist on the Fin gate area and there was photoresist in other areas; Step 3.2, etching away the AlGaN graded barrier layer (3) in the Fin gate region that is not covered by the SiN temporary barrier layer (8); The AlGaN graded barrier layer (3) in the Fin gate region which is not covered by the SiN temporary barrier layer (8) is etched using an ICP process; the process conditions are: the reaction gases are Cl2 and BCl3, the reaction chamber pressure is 100 mTorr, the radio frequency powers of the upper electrode and the lower electrode are 100 W and 10 W respectively, and the etching depth is 90 nm; Step 4, using BOE solution to etch away the SiN temporary barrier layer (8) in the gate region, leaving a jagged nanowire channel (7) in the Fin gate region; Step 5, depositing metal in the Fin gate region to form a Fin gate (6); specifically: Step 5.1, bake the device on a hot plate at 200°C for 2 minutes; then, apply and spin the photoresist at a spinning speed of 2000 rpm, and bake the device on a hot plate at 100°C for 2 minutes; then, place the device in an EBL lithography machine for exposure; finally, place the exposed device in a developer for 40 seconds, rinse it with isopropanol and blow it dry with nitrogen, and after drying, bake the device on a hot plate at 110°C for 2 minutes to form a pattern in which there is no photoresist on the Fin gate area and there is photoresist in other areas; Step 5.2: Place the device in the electron beam evaporation station and wait until the vacuum degree of the reaction chamber of the electron beam evaporation station reaches 2×10 - 6 After Torr, gate metal is evaporated on the photoresist in the gate area and outside the gate area, and the metal is Ni / Au from bottom to top; then, the device after the gate metal evaporation is stripped, and then the device is rinsed with isopropyl alcohol and blown dry with nitrogen to form a Fin gate (6).