Single-layer graphene field effect transistor with conductive copper adhesive tape as back gate and preparation method of single-layer graphene field effect transistor

Abstract

The invention discloses a preparation method of a single-layer graphene field effect transistor with a conductive copper adhesive tape as a back gate. The method comprises the following steps: carrying out thermal oxidation on a silicon wafer, spin-coating photoresist, exposing and developing to obtain an electrode pattern; preparing a metal electrode through etching and thermal evaporation; transferring the graphene film to a prefabricated structure through wet transfer, and performing critical drying; and etching the back silicon dioxide, and taking the conductive copper adhesive tape as a back gate to obtain the graphene field effect transistor taking the conductive copper adhesive tape as the back gate. A method of transferring and prefabricating an electrode in advance is adopted in the preparation process of the device, so that the transferring quality of the graphene is effectively improved; in addition, a test result shows that the conductive copper adhesive tape is used as the back grid electrode, good contact is achieved by increasing the contact area with substrate silicon, good regulation and control on graphene can be achieved within a small grid electrode voltage range, and meanwhile the device shows a large conduction current value.

Description

Technical Field

[0001] The invention belongs to the technical field of graphene field effect transistors, and in particular relates to a single-layer graphene field effect transistor with a conductive copper tape as a back gate and a preparation method thereof. Background Art

[0002] In the past few decades, transistors have been at the core of the development of electronic technology. As the most basic component in integrated circuits, the miniaturization and performance improvement of transistors have promoted the progress of the entire electronics industry and have been widely used in computers, communication equipment, consumer electronics and industrial fields. With the development of transistors, the industry has higher and higher performance requirements for transistors, including higher switching speeds, lower power consumption and higher integration. However, existing silicon-based transistors have encountered many limitations in size reduction and performance improvement: severe carrier scattering, high leakage current, etc. Even the most advanced gate-all-around structure (GAA) cannot mitigate the impact of short channel effects. Therefore, in recent years, the industry has been exploring new materials to replace silicon, and graphene has gained widespread attention due to its unique band structure, atomic-level thickness, and the fact that carrier migration and heat diffusion are confined to a two-dimensional plane. It is expected to break through the physical limitations of existing silicon materials and become a new generation of channel materials.

[0003] Currently, wet transfer based on PMMA is one of the methods for preparing two-dimensional material transistors including graphene. However, the quality of the film obtained by wet transfer during the preparation of transistors will greatly affect the device characteristics. During the wet transfer process, the graphene film will inevitably come into contact with the solution. When the surface solution changes from liquid to gas during the drying process of the graphene, the surface tension of the solution may cause wrinkles and damage to the graphene, which will seriously affect the electrical characteristics of the subsequent devices. Therefore, a method is needed to solve the problem of film wrinkles and damage during the wet transfer process.

[0004] At the same time, the gate application method of the back-gate transistor will affect the voltage regulation ability of the device. At present, many researchers use diamond knives to scratch the silicon dioxide on the surface of the device, and use probes to directly contact or drip conductive silver paste to apply the gate voltage. Although the process steps are simplified, it will lead to the problem of poor contact between the gate and the probe. The method of using a conductive copper tape as a back gate provided by the present invention can simplify the preparation process as much as possible while ensuring good contact between the gate and the substrate. Summary of the invention

[0005] The purpose of the present invention is to provide a low-cost, high-quality single-layer graphene field effect transistor with a conductive copper tape as a back gate.

[0006] On the one hand, the present invention aims to solve the technical problems existing in the wet transfer process. For this purpose, an optimized transfer step is provided, in which a concave watch glass is used in the transfer process, and the contactless transfer of graphene can be achieved based on the surface tension of the solution during the scooping process, thereby avoiding contact contamination between graphene and other substrates; in the drying process, a critical drying method is adopted, and the pressure and temperature are controlled to make the solvent such as acetone reach the critical point, so that its surface tension is 0, thereby avoiding wrinkles and damage of graphene during the drying process as much as possible.

[0007] Another aspect of the present invention is to provide a gate voltage through a conductive copper tape in close contact with the silicon substrate, thereby increasing the contact area between the bottom copper gate and the silicon substrate to improve the contact between the gate and the substrate.

[0008] The present invention provides a single-layer graphene field effect transistor with a conductive copper tape as a back gate, and the transistor structure comprises: (1) Conductive copper tape; (2) Silicon substrate, tightly attached to the conductive copper tape; (3) A silicon dioxide layer is grown on the surface of the silicon substrate by thermal oxidation, and grooves of a metal electrode array are formed on the surface of the silicon dioxide layer by RIE.

[0009] (4) A metal electrode array, wherein the electrode array materials Ti and Au are located in grooves on the surface of silicon dioxide, and the overall electrode is higher than the silicon dioxide layer.

[0010] (5) A single-layer graphene thin film material, wherein the single-layer graphene thin film material is covered on a metal electrode array, so that the graphene is connected to each group of electrodes to form a channel region.

[0011] The method for preparing a single-layer graphene field effect transistor based on a conductive copper tape as a back gate provided by the present invention specifically comprises the following steps: Step 1: The highly doped silicon wafer is cleaned, placed in a heat treatment furnace and oxygen is introduced for thermal oxidation. After sufficient reaction, a layer of SiO2 film is formed.

[0012] Step 2: A layer of positive photoresist is spin-coated on the thermally oxidized silicon wafer, and the Si wafer is exposed using a double-sided aligned UV photolithography machine based on the drawn mask. After development, the electrode pattern is exposed; then it is heated at 110°C.

[0013] Step 3: The substrate obtained in step 2 is etched using RIE to obtain electrode grooves; then placed in an electron beam evaporation coating machine, and after setting appropriate evaporation conditions, Ti and Au are evaporated as electrodes respectively; the evaporated substrate is placed in an acetone solution for ultrasonic oscillation to remove photoresist and excess electrode materials to obtain an Au / Ti / SiO2 / Si / SiO2 structure.

[0014] Step 4: The SiO2 on the back of the step three structure is etched using gas phase HF to obtain an Au / Ti / SiO2 / Si structure, which is then cleaned.

[0015] Step 5: Wet transfer of single-layer graphene was performed, the copper-based graphene material was cut and flattened with a weight for 10 minutes, and PI tape was used to seal the "four sides" of the copper-based graphene and fixed on the PET substrate to prevent the PMMA solution from penetrating into the back of the copper substrate and hindering subsequent etching treatment.

[0016] Step 6: Place the sample in step 5 in a glue spreader, and spin-coat acetone and anhydrous ethanol solutions in a multi-step spin coating method to clean the dust and impurities on the graphene surface; spin-coat the cleaned sample with PMMA A4 solution, place it on a heating table and bake it at 90°C for 10 minutes; cut and flatten it again.

[0017] Step 7: The flattened PMMA / graphene / Cu was placed in an 8% FeCl3 solution and etched for 25 minutes. The PMMA / graphene / Cu was picked up with plastic tweezers and rinsed with deionized water (DI) to remove the graphene on the back. The rinsed PMMA / graphene / Cu was placed in a new 8% FeCl3 solution and etched for 2 hours to remove the Cu substrate. A small portion of the FeCl3 solution and the PMMA / graphene film were transferred to DI for rinsing using a concave glass. The rinsed sample was transferred to the device prepared in step 4. The PMMA / graphene / Au / Ti / SiO2 / Si was naturally dried at a 45° angle for 2 hours. It was placed on a heating table and gradient heated at 50, 70, 90, and 110°C for 5 minutes each to increase the fit between the graphene and the device.

[0018] Step 8: The device PMMA / graphene / Au / Ti / SiO2 / Si was placed in an acetone solution, the acetone was replaced every 0.5 h, repeated 6 times, and dried using a carbon dioxide (CO2) critical dryer; the dried graphene / Au / Ti / SiO2 / Si was placed in a tube furnace and thermally annealed at 300°C for 1 h to further remove PMMA residues and make the graphene fit more closely to the substrate.

[0019] Step 9: The photoresist is spin-coated again on the graphene / Au / Ti / SiO2 / Si surface, and the channel region is prepared by exposure and development, and the graphene portion outside the channel region is etched; the photoresist is removed and the graphene film is dried by soaking in acetone through critical drying.

[0020] Step 10: Stick the conductive copper tape tightly to the back of the graphene / Au / Ti / SiO2 / Si structure to obtain graphene / Au / Ti / SiO2 / Si / conductive copper tape, completing the sample preparation.

[0021] Compared with the prior art, the advantages of the present invention are: The single-layer graphene field effect transistor with a conductive copper tape as a back gate provided by the present invention has a wide contact area between the silicon substrate and the conductive copper tape in the device structure, which can effectively control the carrier type and concentration of the graphene in the channel region and improve the on-current of the transistor device; in addition, the electrode to be prepared is first integrated into the silicon wafer structure and then the film is transferred, which can effectively avoid the influence of subsequent multiple complex micro-nano processing processes on the material film and device performance; in addition, by designing the mask pattern, the present invention can also prepare a four-inch device array, that is, prepare a plurality of device electrode structures on a four-inch silicon wafer, greatly improving the preparation efficiency of the graphene transistor device.

[0022] The single-layer graphene preparation scheme provided by the present invention optimizes and improves the original PMMA wet transfer process, including contactless film transfer and critical drying, which can effectively deal with the problems of film contamination, damage and wrinkles during the wet transfer process, and greatly improve the material transfer quality and subsequent device characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 The present invention is a flow chart for preparing a single-layer graphene field effect transistor using a conductive copper tape as a back gate.

[0024] Figure 2 This is a probe connection diagram of the source, drain and gate when the conductive copper tape in the present invention is used to measure the back-gate graphene field effect transistor.

[0025] Figure 3 This is an optical picture of a single-layer graphene field effect transistor prepared after transferring graphene in the present invention.

[0026] Figure 4 The invention discloses a Raman spectrum of a graphene material using a conductive copper tape as a back-gate graphene field effect transistor.

[0027] Figure 5The graph is a transfer characteristic curve of a single-layer graphene field effect transistor using a conductive copper tape as a back gate prepared by the present invention, wherein the source-drain voltage is 0.7V. DETAILED DESCRIPTION In order to more clearly describe the solution of the present invention, the present invention is further supplemented with reference to the accompanying drawings.

[0029] The present invention provides a single-layer graphene field effect transistor structure with a conductive copper tape as a back gate. Figure 1 As shown in (h), from top to bottom, they are: graphene, Au, Ti, SiO2, Si, and conductive copper tape. The specific preparation process is as follows Figure 1 (ah) shown: Figure (a) shows a highly doped silicon wafer, which was cleaned in a water bath with DI:H2O2:NH4OH=5:1:1 at 70°C, and then in a water bath with DI:H2O2:HCl=5:1:1 at 70°C to remove impurities on the wafer surface.

[0030] As shown in Figure (b), the cleaned highly doped silicon wafer is placed in a heat treatment furnace and O2 is introduced for thermal oxidation. After sufficient reaction, a layer of SiO2 film is formed, in which the Si thickness is 500±25 μm and the SiO2 thickness is 100±10 nm.

[0031] The substrate obtained after oxidation was subjected to RIE etching to prepare electrode grooves as shown in Figure (c), and the groove depth was 50nm; Figure (d) shows the use of an electron beam evaporation coating machine to sequentially evaporate Ti and Au as electrodes on the surface of a substrate, with 40 nm of titanium and 30 nm of gold. The evaporated substrate is then placed in an acetone solution for ultrasonic vibration to remove excess electrode material.

[0032] Figure (e) uses gaseous hydrofluoric acid to etch the bottom silicon dioxide, the HF concentration is HF:H2O=1:3, and the time required to etch 100nm SiO2 is 5 minutes.

[0033] Figure (f) transfers a single layer of graphene and PMMA film to the device in Figure (e) based on wet PMMA transfer. The structure in Figure (g) is obtained by removing PMMA and critical drying.

[0034] A layer of conductive copper tape is tightly attached to the substrate of the structure shown in Figure (g) to obtain the final device structure (h).

[0035] Figure 2 The connection diagram of the source, drain and gate when the conductive copper tape is used as the back-gate graphene field effect transistor in the present invention is shown, wherein the source is grounded as the common ground terminal of the two groups of voltage signals.

[0036] Figure 3The single-layer graphene field effect transistor prepared according to the method of the present invention is shown. The Raman spectrum test results of the graphene material are as follows Figure 4 shown.

[0037] According to the present invention Figure 2 The transfer characteristics of the single-layer graphene field effect transistor with conductive copper tape as the back gate tested by the connection method are shown in the figure below. Figure 5 As shown, the Dirac point of the single-layer graphene field-effect transistor device is located near 0 V, indicating that it is not significantly doped during the film transfer process; at the same time, the device exhibits a large on-current value.

Claims

1. A single-layer graphene field effect transistor with a conductive copper tape as a back gate, characterized in that: The transistor structure includes: the gate of the transistor is a layer of conductive copper tape, which is located at the bottom of the overall device; the substrate of the transistor is a silicon material, which is tightly attached to the conductive copper tape; the upper surface of the silicon material substrate is a silicon dioxide layer, and the upper surface of the silicon dioxide layer is etched to form grooves of a metal electrode array; the metal electrode array is arranged in the grooves on the silicon dioxide surface, and the overall electrode array is higher than the silicon dioxide layer; the metal electrode array is covered with a single layer of graphene film material, so that the graphene is connected to each group of electrodes to form a channel region of the transistor.

2. A method for preparing a single-layer graphene field effect transistor with a conductive copper tape as a back gate, characterized in that: The preparation method comprises: Step 1: Clean the silicon (Si) wafer and form a silicon dioxide film (SiO2) by thermal oxidation to produce Si / SiO2 / Si; Step 2: Spin-coat a layer of photoresist on the Si / SiO2 / Si obtained in step 1, perform photolithography using a photolithography machine based on the drawn mask, and obtain an electrode pattern after development; Step 3: The structure in step 2 is etched and thermally evaporated to prepare a metal electrode, and excess electrode material is removed to obtain a metal electrode / SiO2 / Si / SiO2; Step 4: Etching the back of the structure obtained in step 3 to remove SiO2 to obtain a metal electrode / SiO2 / Si; Step 5: Clean the copper-based graphene, cut and flatten it, and then use tape to seal the copper-based graphene around it and fix it on the substrate; Step 6: Spin-coating a polymethyl methacrylate (PMMA) solution on the copper-based graphene material in step 5 and heating the solution to prepare PMMA / graphene / Cu; Step 7: Etch the copper substrate of the structure in step six, transfer and rinse the film based on the concave glass, attach it to the structure obtained in step four, and heat it to obtain PMMA / graphene / metal electrode / SiO2 / Si; Step 8: The structure obtained in step 7 is placed in an acetone solution, dried by a critical dryer, and then placed in a tube furnace for thermal annealing; Step 9: Spin-coating photoresist on the surface of the structure obtained in step eight, preparing a channel region by photolithography, and etching the graphene portion outside the channel region; Step 10: In step nine, a layer of conductive copper tape is tightly attached to the back of the structure as the gate of the back-gate field effect transistor to obtain graphene / metal electrode / SiO2 / Si / conductive copper tape.

3. The method for preparing a single-layer graphene field effect transistor with a conductive copper tape as a back gate according to claim 2, characterized in that: The etching in step three adopts reactive ion etching (RIE), and the obtained groove depth is 50nm; the metal electrode materials are titanium (Ti) and gold (Au), wherein Ti is 40nm and Au is 30nm; the method for removing excess electrode material is to place the evaporated substrate in an acetone solution, seal it and place it in an ultrasonic oscillator for ultrasonic oscillation at 35°C for 0.5h.

4. The method for preparing a single-layer graphene field effect transistor with a conductive copper tape as a back gate according to claim 2, characterized in that: In step 4, gas phase hydrofluoric acid (HF) is used to etch silicon dioxide, the solution concentration is HF:H2O=1:3, and the etching rate of silicon dioxide is 20nm / min.

5. The method for preparing a single-layer graphene field effect transistor with a conductive copper tape as a back gate according to claim 2, characterized in that: In the step 5, the base material is polyethylene terephthalate (PET).

6. The method for preparing a single-layer graphene field effect transistor with a conductive copper tape as a back gate according to claim 2, characterized in that: The speed and time of spin coating PMMA in step 6 are 1000 r / min 10s + 3000 r / min 30s.

7. The method for preparing a single-layer graphene field effect transistor with a conductive copper tape as a back gate according to claim 2, characterized in that: In the step 7, 8% ferric chloride (FeCl3) solution is used to etch the copper substrate; the concave glass used is a watch glass, and in the process of transferring and rinsing the film, contactless transfer of the film can be achieved based on the surface tension of the liquid.

8. The method for preparing a single-layer graphene field effect transistor with a conductive copper tape as a back gate according to claim 2, characterized in that: The process of drying in the critical dryer in step eight is as follows: placing the graphene sample in a cavity of the critical dryer filled with acetone solution, introducing CO2, controlling the temperature to 38°C and the pressure to 10 MPa, so that acetone and CO2 reach a critical point, and slowly extracting acetone and CO2 to achieve sample drying.

9. The single-layer graphene field effect transistor with a conductive copper tape as a back gate and a preparation method thereof according to claim 2, characterized in that: The method for etching graphene in step nine is to place the photolithographic substrate in a plasma cleaning machine, introduce oxygen, and etch for 300 seconds at a power of 100W.

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