High-reliability solar cell and preparation method thereof

Abstract

The invention discloses a solar cell piece with high reliability and a preparation method, and belongs to the technical field of photovoltaic solar panel production, and the solar cell piece comprises a suede structure layer, an intrinsic amorphous silicon layer, a doped microcrystalline or amorphous silicon layer, a transparent conductive film layer, a metal auxiliary grid line layer, a protective film layer and a confluence body which are sequentially prepared on the surface of a monocrystalline silicon piece layer, therefore, impurities are prevented from entering the solar cell from the surface of the solar cell. The protective film layer can effectively prevent water vapor or other impurities from invading the solar cell. The metal grid line layer is protected from water vapor corrosion, and the service life of the metal grid line layer is prolonged. And meanwhile, the transparent conductive film layer and the interior of the silicon wafer are protected, impurities are prevented from entering to influence light transmission and further influence the light conversion efficiency of the solar cell, and the attenuation rate of the solar cell is reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of photovoltaic solar cell production, and in particular relates to a solar cell sheet with high reliability and a preparation method thereof. Background Art

[0002] In the development of silicon-based batteries, engineers in the photovoltaic field have done a lot of research on the high attenuation rate of photovoltaic cell light conversion efficiency. For example, in order to improve the conversion efficiency of heterojunction battery technology, silver-copper paste is introduced in the metallization process. This operation can effectively improve the light conversion efficiency, but this process will make photovoltaic cells more sensitive to changes in environmental conditions such as humidity and heat, especially at the component end, which will reduce the reliability of photovoltaic cells. For example, the metal grid lines of silicon wafers are often invaded by water vapor or other impurities, which affects the normal conductivity of the metal grid, and impurities will reduce the light transmittance of the silicon wafer, thereby affecting the light conversion rate of the silicon wafer, increasing the attenuation rate of the cell light conversion efficiency, and affecting the battery life.

[0003] The existing technology further improves the efficiency and reliability of solar cells in the following steps: texturing and cleaning, preparation of passivation layer and doping layer, preparation of TCO layer, screen printing electrodes to obtain solar cells, and then coating the solar cells with a protective film layer, the main component of which is an oxide layer (such as SiOx), or a nitride layer (such as SiNx), or other protective film layer structures (such as MgF2). However, in the subsequent process of processing the solar cells into photovoltaic modules, it is necessary to weld the various collectors (such as the main grid) of the solar cells with welding ribbons. Because of the protective film layer, the welding tension between the welding ribbon and the solar cell is very small, which does not meet the production process requirements. In order to solve this problem, the existing practices are generally:

[0004] 1. Before plating the protective film layer, a mask is set at the location of the confluence body so that the location of the confluence body is not covered by the protective film layer, thereby not affecting the subsequent welding effect; this method requires high mask preparation accuracy, is difficult to prepare, and has complex production and processing technology;

[0005] 2. After the protective film layer is plated, the etching slurry is printed at the location of the confluence line to corrode and remove the protective film layer at the location of the confluence line; on the one hand, this method cannot completely remove the protective film layer at the location of the confluence line and reduce the welding tension. On the other hand, it may damage the grid line and reduce the efficiency of the battery cell.

[0006] However, the above methods will increase production costs, and the process is relatively complicated, and the working efficiency after the battery cell and the welding ribbon are welded will also be reduced. Summary of the invention

[0007] 1. Problems to be solved

[0008] In order to solve or partially solve the shortcoming of high attenuation rate of cell light conversion efficiency in heterojunction cell technology, the present invention provides a highly reliable solar cell and a preparation method thereof, by covering the metal secondary grid line layer of the solar cell with a protective film layer, the tension between the collector and the soldering ribbon is ensured while maintaining efficiency and reliability.

[0009] 2. Technical solution

[0010] To solve the above problems, the present invention adopts the following technical solutions:

[0011] A highly reliable solar cell comprising a single crystal silicon layer,

[0012] A velvet structure layer, an intrinsic amorphous silicon layer, a doped microcrystalline or amorphous silicon layer, a transparent conductive film layer, a metal sub-grid layer, a protective film layer and a concentrator are prepared on the surface of the single crystal silicon layer; wherein the protective film layer covers between the metal sub-grid layer and the concentrator to prevent impurities from entering the interior of the solar cell from the surface of the solar cell.

[0013] The protective film layer covers the metal secondary grid line layer, which can effectively prevent water vapor or other impurities from invading the interior of the solar cell. It protects the metal secondary grid line layer and the silicon wafer film layer below from water vapor corrosion, and increases the service life of the metal secondary grid line layer. At the same time, it protects the silicon wafer film layer to prevent impurities from entering and affecting light transmission, thereby affecting the light conversion efficiency of the solar cell and reducing the attenuation rate of the solar cell.

[0014] In the highly reliable solar cell provided in the present application, further, both sides of the solar cell are covered with the protective film layer.

[0015] In a highly reliable solar cell provided in the present application, further, the doped microcrystalline or amorphous silicon layer includes a doped N-type microcrystalline or amorphous silicon layer and a doped P-type microcrystalline or amorphous silicon layer;

[0016] A textured structure layer, an intrinsic amorphous silicon layer, a doped N-type microcrystalline or amorphous silicon layer, a transparent conductive film layer, a metal secondary gate line layer, a protective film layer, and a converging body are sequentially deposited on one side of the surface of the single crystal silicon layer;

[0017] The other side of the surface of the single crystal silicon layer is sequentially stacked with a velvet structure layer, an intrinsic amorphous silicon layer, a doped P-type microcrystalline or amorphous silicon layer, a transparent conductive film layer, a metal secondary gate line layer, a protective film layer, and a converging body.

[0018] In a highly reliable solar cell provided in the present application, further, the protective film layer includes one or a combination of several materials including silicon oxide, silicon nitride, lithium fluoride, magnesium fluoride, titanium oxide, and aluminum oxide.

[0019] In a highly reliable solar cell provided in the present application, further, the thickness of the protective film layer is 0.1 to 100 nm. The protective film layer is located between the metal auxiliary grid line layer and the collector, and the metal auxiliary grid line is required to collect carriers so that electrons can be conducted to the main grid line through the tunneling effect and the hole effect, so the thickness of the protective film layer needs to be limited. Considering that after adding the protective film layer, in order to avoid the protective film layer affecting the operation of the solar cell, the thickness of the protective film layer needs to be 0.1 to 100 nm. .

[0020] The present application provides a method for preparing a solar cell with high reliability.

[0021] The surface of the single crystal silicon wafer is polished and cleaned, textured, thin film deposited, and metal gate lines printed in sequence, so as to form a texture structure layer, an intrinsic amorphous silicon layer, a doped microcrystalline or amorphous silicon layer, a transparent conductive film layer, a metal sub-gate line layer, and a converging body in sequence on the surface of the single crystal silicon wafer;

[0022] A protective film is deposited between the collector and the metal auxiliary grid line layer to form a protective film layer covering the metal auxiliary grid line layer, and after sintering and curing, a finished solar cell is formed. The solar cell prepared in this way can protect the solar cell and prevent impurities from invading the interior of the solar cell as the solar cell is used for a long time, thereby affecting the light conversion rate of the solar cell.

[0023] In a method for preparing a solar cell with high reliability provided in the present application, further, the single crystal silicon wafer is polished and cleaned, comprising:

[0024] S1: using a first alkaline solution to clean and polish the monocrystalline silicon wafer to remove a damaged layer on the surface of the solar cell;

[0025] In a highly reliable solar cell preparation method provided in the present application, the single crystal silicon wafer is further textured, including: S2: using a textured solution to clean the surface of the single crystal silicon wafer to prepare a uniformly distributed texture structure layer on the surface of the silicon wafer.

[0026] In a method for preparing a solar cell with high reliability provided in the present application, further, a thin film deposition process is performed on the silicon wafer treated in step S2, including:

[0027] S3: using a first acidic solution to clean the surface of the silicon wafer to passivate the surface of the silicon wafer;

[0028] S4: depositing a layer of intrinsic amorphous silicon on both sides of the silicon wafer processed in S3, and then depositing a doped N-type microcrystalline or amorphous silicon layer on the intrinsic amorphous silicon layer on the second surface of the silicon wafer; and depositing a P-type doped amorphous or microcrystalline silicon layer on the intrinsic amorphous silicon layer on the first surface of the silicon wafer;

[0029] Transparent conductive film layers are deposited on both sides of the silicon wafer.

[0030] In a method for preparing a solar cell with high reliability provided in the present application, further, S5: printing metal auxiliary grid line layers on both sides of the silicon wafer processed in step S4, depositing the protective film layers on the metal auxiliary grid line layers, and printing the collector fluid on the protective film layers; S6: sintering and curing the silicon wafer prepared in S5 to prepare a finished solar cell.

[0031] Beneficial effects:

[0032] (1) The protective film layer covers the metal secondary grid line layer. Specifically, the protective film layer is located between the collector and the metal secondary grid line layer. The collector can be directly connected to the welding strip, thereby ensuring the tension between the collector and the welding strip while maintaining efficiency and high reliability. The protective film layer can also effectively prevent water vapor or other impurities from invading the interior of the solar cell, protect the metal secondary grid line layer from water vapor corrosion, and increase the service life of the metal secondary grid line layer. Protect the transparent conductive film layer and other silicon wafer film layers to prevent impurities from entering the silicon wafer and affecting light transmission, thereby affecting the light conversion efficiency of the solar cell, reducing the attenuation rate of the solar cell, and improving reliability.

[0033] (2) After adding the protective film layer, the protective film layer is located between the metal auxiliary grid line layer and the collector. The metal auxiliary grid line is required to collect carriers so that electrons can be conducted to the metal main grid line through the tunneling effect and the hole effect. Therefore, the thickness of the protective film layer needs to be limited. Considering that after adding the protective film layer, in order to avoid the protective film layer affecting the operation of the solar cell, the thickness of the protective film layer needs to be 0.1 to 100 nm.

[0034] (3) In the traditional method, the main grid line is printed on the TCO layer, while in the present invention, a protective film layer is plated after the secondary grid line is printed and then the main grid line is printed. The main grid line is printed on the protective film layer. Generally, the protective film layer is composed of SiOx, SiNx and other components. Therefore, the protective film layer and the main grid line have a better connection effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 This is a schematic diagram of the structure of a solar cell with a protective film layer in the present application;

[0036] Figure 2 It is a schematic diagram of the structure of a solar cell without a protective film layer;

[0037] Figure 3 It is a schematic diagram of a structure in which a protective film layer is provided on the surface of a solar cell;

[0038] Figure 4 This is a general flow chart of the solar cell preparation method of the present application;

[0039] Figure 5 This is a flow chart of the solar cell preparation method of the present application;

[0040] In the figure:

[0041] 11. Convergence body; 12. Metal sub-gate line layer; 2. Transparent conductive film layer; 3. Doped N-type microcrystalline or amorphous silicon layer; 4. Intrinsic amorphous silicon layer; 5. Velvet structure layer; 6. Single crystal silicon sheet layer; 7. Doped P-type microcrystalline or amorphous silicon layer; 8. Protective film layer. DETAILED DESCRIPTION

[0042] The following detailed description of exemplary embodiments of the present invention refers to the accompanying drawings, which form a part of the description, and in which exemplary embodiments of the present invention that can be implemented are shown as examples. Although these exemplary embodiments are described in sufficient detail to enable those skilled in the art to implement the present invention, it should be understood that other embodiments can be implemented and various changes can be made to the present invention without departing from the spirit and scope of the present invention. The following more detailed description of the embodiments of the present invention is not intended to limit the scope of the claimed invention, but is only for the purpose of illustrating and not limiting the description of the characteristics and features of the present invention, so as to propose the best mode for performing the present invention and to enable those skilled in the art to implement the present invention. Therefore, the scope of the present invention is limited only by the appended claims.

[0043] The inventors of the present application have discovered that the metal grid lines of silicon wafers are often invaded by water vapor or other impurities, which affects the normal conductivity of the metal grid lines, causing the light transmittance of the silicon wafer to decrease, thereby affecting the light conversion rate of the silicon wafer, increasing the attenuation rate of the light conversion efficiency of solar cells, and reducing the service life of solar cells.

[0044] Example 1

[0045] like Figure 1 As shown, in order to solve the above problems, the present application provides a solar cell with high reliability, including a single crystal silicon layer 6, on the surface of which are sequentially prepared a velvet structure layer 5, an intrinsic amorphous silicon layer 6, a doped microcrystalline or amorphous silicon layer, a transparent conductive film layer 2, a metal sub-grid line layer 12, a protective film layer 8 and a collector 11, and the protective film layer 8 covers the metal sub-grid line layer 12 to prevent impurities from entering the interior of the solar cell from the surface of the solar cell.

[0046] Based on the above, the solar cell structure is further described in detail.

[0047] In the embodiment of the present application, the doped microcrystalline or amorphous silicon layer may include a doped N-type microcrystalline or amorphous silicon layer 3 and a doped P-type microcrystalline or amorphous silicon layer 7. In order to facilitate understanding of the embodiment of the present application, a single crystal silicon wafer 6 is used as a basic silicon wafer, and a velvet structure layer 5, an intrinsic amorphous silicon layer 6, a doped N-type microcrystalline or amorphous silicon layer 3, a transparent conductive film layer 2, a metal sub-grid layer 12, a protective film layer 8 and a concentrator 11 are sequentially connected on the first surface (front) of the single crystal silicon wafer 6, and the protective film layer 8 covers the metal sub-grid layer 12. The velvet structure layer 5, the intrinsic amorphous silicon layer 6, the doped P-type microcrystalline or amorphous silicon layer 7, the transparent conductive film layer 2, the metal sub-grid layer 12, the protective film layer 8 and the concentrator 11 are sequentially connected on the second surface (back) of the single crystal silicon wafer 6, and the concentrator 11 is used to conduct carriers and is connected to an external circuit; the protective film layer 8 covers the metal sub-grid layer 12.

[0048] The protective film layer covers the metal auxiliary grid line layer 12, and the specific protective film is located between the collector 11 and the metal auxiliary grid line layer 12, which can effectively prevent water vapor or other impurities from invading the interior of the solar cell. The metal auxiliary grid line layer 12 is protected from water vapor corrosion, and the service life of the metal auxiliary grid line layer 12 is increased. At the same time, the transparent conductive film layer and other silicon wafer film layers are protected to prevent impurities from entering the interior of the silicon wafer and affecting light transmission, thereby affecting the light conversion efficiency of the solar cell and reducing the attenuation rate of the solar cell.

[0049] A method for preparing a solar cell with high reliability is provided, wherein the surface of a single crystal silicon wafer is polished, cleaned, textured, deposited with a thin film, and printed with a metal grid line in sequence, so as to form a velvet structure layer, an intrinsic amorphous silicon layer, a doped microcrystalline or amorphous silicon layer, a transparent conductive film layer, a metal auxiliary grid line layer 12, and a concentrator 11 in sequence on the surface of the single crystal silicon wafer; a protective film is deposited between the metal auxiliary grid line layer 12 and the concentrator 11 to form a protective film layer covering the metal auxiliary grid line layer 12, and after sintering and curing, a finished solar cell is formed. The concentrator 12 can be directly connected to the welding strip, so as to ensure the tension between the concentrator 12 and the welding strip while maintaining efficiency and reliability. The solar cell prepared by this method can protect the solar cell, and prevent impurities from invading the interior of the solar cell as the use time of the solar cell increases, thereby affecting the light conversion rate of the solar cell.

[0050] In this embodiment, the protective film layer may include one or a combination of silicon oxide, silicon nitride, lithium fluoride, magnesium fluoride, titanium oxide, and aluminum oxide.

[0051] Example 2

[0052] like Figure 4As shown, a method for preparing a solar cell with high reliability specifically comprises the following steps:

[0053] S1: Polishing and cleaning the silicon wafer surface

[0054] The single crystal silicon wafer is cleaned with a first alkaline solution to remove the damaged layer on the surface of the silicon wafer caused by cutting with tools such as diamond wire. The first alkaline solution can be a mixed solution of potassium hydroxide solution and hydrogen peroxide, the concentration of potassium hydroxide solution is 3% to 11%, preferably 7%; the concentration of hydrogen peroxide is 4% to 12%, preferably 8%. The temperature of the first alkaline solution is 60 to 80°C, preferably 70°C, and the cleaning time is 100 to 500s, preferably 300s.

[0055] S2: Velveting

[0056] Texturing: Use a texturing solution to clean the surface of the silicon wafer treated in step S1 to prepare a velvet structure layer 5 on both sides of the silicon wafer, and the velvet structure layer 5 is pyramid-shaped. The specific method is: the surface of the silicon wafer is cleaned with a texturing solution, the solution temperature is 20-85°C, preferably 80°C; the cleaning time is 100-500s, preferably 420s. Among them, the texturing solution is a mixed solution composed of potassium hydroxide and a texturing additive, the potassium hydroxide concentration is 2%-5%, preferably 3%; the texturing additive concentration is 0.5-2%, preferably 1%. The size of the velvet on the second surface of the silicon wafer obtained is 0.1-8um.

[0057] S3: Passivation

[0058] The surface of the silicon wafer treated in step S2 is cleaned with a first acidic solution to passivate the surface of the silicon wafer. The first acidic solution may be a hydrofluoric acid solution with a concentration of 2% to 8%, preferably 5%; a solution temperature of 15 to 35° C., preferably 25° C.; and a cleaning time of 100 to 300 seconds, preferably 200 seconds.

[0059] S4: Coating

[0060] S41: The first surface of the silicon wafer is coated to form an amorphous silicon thin film layer and an N-type doped microcrystalline or amorphous silicon layer. The first mixed gas is used to perform the initial coating on the first surface of the silicon wafer treated in step S3, and a layer of amorphous silicon thin film layer is deposited on the first surface of the silicon wafer. The film deposition thickness is 3 to 8 nm, preferably 5 nm. The first mixed gas component can be a mixed gas of SiH4 and H2, and the mixed volume ratio is 1:300, preferably 1:5. The second mixed gas is used to perform the secondary coating on the silicon wafer that has been coated for the first time, and a layer of N-type doped microcrystalline or amorphous silicon layer is deposited on the surface of the silicon wafer. The film deposition thickness is 10 to 60 nm, preferably 20 nm. The second mixed gas component can be a mixed gas of SiH4, H2, and PH3, wherein the mixed volume ratio of SiH4 to H2 is 1:5 to 300, preferably 1:300. The PH3 doping volume accounts for 1 to 8%, preferably 4%.

[0061] S42: Coating the second surface of the silicon wafer to form an amorphous silicon thin film layer and a P-type doped microcrystalline or amorphous silicon layer. The first mixed gas is used to perform the initial coating on the second surface of the silicon wafer treated in step S41, and a layer of amorphous silicon thin film is deposited on the second surface of the silicon wafer. The film deposition thickness is 4 to 10 nm, preferably 6 nm. The third mixed gas is used to perform the secondary coating on the silicon wafer that has been initially coated on the second surface, and a layer of P-type doped microcrystalline or amorphous silicon layer or microcrystalline silicon thin film is deposited on the surface of the silicon wafer. The film deposition thickness is 20 to 100 nm, preferably 25 nm. The third mixed gas composition can be a mixed gas of SiH4, H2, and B2H6, wherein the mixed volume ratio of SiH4 to H2 is 1:5 to 300, preferably 1:300. The doping volume of B2H6 accounts for 0.5 to 6%, preferably 1%.

[0062] S43: Deposit transparent conductive film layer 2 on both sides of the silicon wafer. Using the silicon wafer processed in step S42, deposit transparent conductive film layer 2 or other passivation anti-reflection film layer on both sides (first surface and second surface) of the silicon wafer. In this step, a general PVD sputtering device can be used to process both sides of the silicon wafer. The thickness of the transparent conductive film layer 2 is 60 to 200 nm.

[0063] S5: Prepare the metal secondary gate line layer 12, the protective film layer 8 and the collector 11 on both sides of the silicon wafer.

[0064] Using the silicon wafer formed in step S4, metal secondary gate lines are printed on the first surface and the second surface of the silicon wafer, and then dried and shaped.

[0065] A protective film layer 8 is formed on the metal secondary grid line layer 12 on the first surface and the second surface. The protective film layer 8 can be a dense oxide layer (such as SiOx), or a nitride layer (such as SiNx), or other protective film layer 8 structures (such as MgF2), as long as it can prevent foreign matter from entering the solar cell. The protective film layer 8 can be a single layer or a multi-layer structure, wherein the multi-layer structure refers to a protective film containing more than two layers, and the main components of the multi-layer protective film can be the same or different. The multi-layer protective film can effectively reduce wear and improve the protectiveness of the protective film layer 8. The protective film layer 8 can be prepared using the general atmospheric pressure vapor deposition (APCVD) technology or other chain deposition devices. The deposition thickness of the protective film layer 8 is controlled at 0.1 to 100 nm.

[0066] The conduit 11 is printed on the protective film layer 8 on the first surface and the second surface.

[0067] The electrical connection between the concentrator 11 and the metal sub-grid line layer 12 is achieved through the tunneling effect (when electrons pass through the intersection of the metal main grid line and the metal sub-grid line, due to the field strength distribution there, the electrons will have a certain probability of passing through the protective film layer and entering the concentrator 11) and the hole effect to conduct the electrons to the metal main grid line. Therefore, in order to avoid the protective film layer being too thick and affecting the electrical connection between the concentrator 11 and the metal sub-grid line layer 12, the thickness of the protective film layer 8 needs to be strictly controlled to not exceed 10nm.

[0068] S6: Sintering and curing

[0069] The silicon wafer prepared in S5 is sent to a curing furnace for sintering to prepare a finished solar cell, wherein the curing furnace temperature is 180-200°C and the sintering time is 20-30 minutes.

[0070] Example 3

[0071] Preparation of the first solar cell: polishing and cleaning the surface of the silicon wafer: using the first alkaline solution to clean the monocrystalline silicon wafer to remove the damage layer on the surface of the silicon wafer caused by cutting with tools such as diamond wire. Among them, the first alkaline solution can be a mixed solution of potassium hydroxide solution and hydrogen peroxide, the concentration of potassium hydroxide solution is 7%; the concentration of hydrogen peroxide is 8%. The temperature of the first alkaline solution is 70°C, and the cleaning time is 300s. Texturing: using a mixed solution composed of potassium hydroxide and a texturing additive to clean the surface of the silicon wafer to prepare a velvet structure layer 5 on both sides of the silicon wafer, the velvet structure layer 5 is pyramid-shaped, the solution temperature is 80°C; the cleaning time is 420s. Among them, the concentration of potassium hydroxide is 3%; the concentration of the texturing additive is 1%. The size of the velvet on the second surface of the prepared silicon wafer is 5um. Passivation: using the first acidic solution to clean the surface of the silicon wafer to passivate the surface of the silicon wafer. The first acidic solution can be a hydrofluoric acid solution, the solution concentration is 5%; the solution temperature is 25°C; the cleaning time is 200s. Coating: The first surface of the silicon wafer is coated to form an amorphous silicon thin film layer and an N-type doped microcrystalline or amorphous silicon thin film layer. The first mixed gas is used to perform the initial coating on the first surface of the silicon wafer treated in step S3, and an amorphous silicon thin film layer is deposited on the first surface of the silicon wafer, and the film deposition thickness is 5nm. The first mixed gas is composed of SiH4 and H2 mixed gas, and the mixed volume ratio is 1:5. The second mixed gas is used to perform the secondary coating on the silicon wafer that has been coated initially, and a N-type doped microcrystalline or amorphous silicon thin film layer is deposited on the surface of the silicon wafer, and the film deposition thickness is 20nm. The second mixed gas is composed of SiH4, H2, and PH3 mixed gas, wherein the SiH4 and H2 mixed volume ratio is 1:300. The PH3 doping volume accounts for 4%. The second surface of the silicon wafer is coated to form an amorphous silicon thin film layer and a P-type doped microcrystalline or amorphous silicon thin film layer: The first mixed gas is used to perform the initial coating on the second surface of the silicon wafer, and an amorphous silicon thin film is deposited on the second surface of the silicon wafer, and the film deposition thickness is 6nm. The silicon wafer that has been initially coated on the second surface is subjected to secondary coating using a third mixed gas, and a layer of P-type doped microcrystalline silicon film is deposited on the surface of the silicon wafer, and the film deposition thickness is 25nm. The third mixed gas is composed of a mixed gas of SiH4, H2, and B2H6, wherein the volume ratio of SiH4 to H2 is 1:300. The volume proportion of B2H6 doping is 1%. Transparent conductive film layer 2 is deposited on both sides of the silicon wafer: a transparent conductive film layer 2 or other passivation anti-reflection film layer is continuously deposited on both sides of the silicon wafer (the first surface and the second surface). In this step, a general PVD sputtering device can be used to process both sides of the silicon wafer. The deposition thickness of the transparent conductive film layer 2 is 100nm. Metal auxiliary grid line layer 12 is prepared on both sides of the silicon wafer: a metal auxiliary grid line layer 12 is prepared on the first surface and the second surface of the silicon wafer. The preparation of metal auxiliary grid lines on the first surface and the second surface is to dry and shape the metal auxiliary grid lines after printing the metal auxiliary grid lines on both sides of the silicon wafer. Then, a protective film layer 8 is deposited on the metal auxiliary grid line layer 12, and the protective film layer 8 is a SiO2 film layer.The protective film layer 8 can be prepared using the general atmospheric pressure vapor deposition (APCVD) technology. The deposition thickness of the protective film layer 8 is controlled to be 1nm. The confluence fluid 11 is printed on the protective film layer 8, and sintered and cured: the silicon wafer is sent to the curing furnace for sintering to prepare a finished solar cell. The curing furnace temperature is 180°C and the sintering time is 26min.

[0072] like Figure 1 As shown, the structure of the first solar cell prepared in Example 3 is as follows Figure 1 As shown, from the front to the back are the conduit 11, the protective film layer 8, the metal sub-gate line layer 12, the transparent conductive film layer 2, the doped N-type microcrystalline or amorphous silicon layer 3, the intrinsic amorphous silicon layer 6, the velvet structure layer 5, the single crystal silicon sheet layer 6, the velvet structure layer 5, the intrinsic amorphous silicon layer 6, the doped P-type microcrystalline or amorphous silicon layer 7, the transparent conductive film layer 2, the metal sub-gate line layer 12, the protective film layer 8 and the conduit 11.

[0073] Comparative Example 1

[0074] In this comparative example, a control solar cell is prepared, which lacks the protective film layer 8 compared to the solar cell prepared in Example 3. The specific preparation method is as follows:

[0075] Preparation of the second solar cell: polishing and cleaning the surface of the silicon wafer: use the first alkaline solution to clean the monocrystalline silicon wafer to remove the damage layer on the surface of the silicon wafer caused by cutting with tools such as diamond wire. Among them, the first alkaline solution can be a mixed solution of potassium hydroxide solution and hydrogen peroxide, the concentration of potassium hydroxide solution is 7%; the concentration of hydrogen peroxide is 8%. The temperature of the first alkaline solution is 70°C, and the cleaning time is 300s. Texturing: use a mixed solution composed of potassium hydroxide and a texturing additive to clean the surface of the silicon wafer to prepare a velvet structure layer 5 on both sides of the silicon wafer, and the velvet structure layer 5 is pyramid-shaped. The solution temperature is 80°C; the cleaning time is 420s. Among them, the concentration of potassium hydroxide is 3%; the concentration of the texturing additive is 1%. The size of the velvet on the second surface of the prepared silicon wafer is 5um. Passivation: use the first acidic solution to clean the surface of the silicon wafer to passivate the surface of the silicon wafer. The first acidic solution can be a hydrofluoric acid solution, the solution concentration is 5%; the solution temperature is 25°C; the cleaning time is 200s. Coating: The first surface of the silicon wafer is coated to form an amorphous silicon thin film layer and an N-type doped microcrystalline or amorphous silicon thin film layer. The first mixed gas is used to perform the initial coating on the first surface of the silicon wafer treated in step S3, and an amorphous silicon thin film layer is deposited on the first surface of the silicon wafer, and the film deposition thickness is 5nm. The first mixed gas is composed of SiH4 and H2 mixed gas, and the mixed volume ratio is 1:5. The second mixed gas is used to perform the secondary coating on the silicon wafer that has been coated initially, and a N-type doped microcrystalline or amorphous silicon thin film layer is deposited on the surface of the silicon wafer, and the film deposition thickness is 20nm. The second mixed gas is composed of SiH4, H2, and PH3 mixed gas, wherein the SiH4 and H2 mixed volume ratio is 1:300. The PH3 doping volume accounts for 4%. The second surface of the silicon wafer is coated to form an amorphous silicon thin film layer and a P-type doped microcrystalline or amorphous silicon thin film layer: The first mixed gas is used to perform the initial coating on the second surface of the silicon wafer, and an amorphous silicon thin film is deposited on the second surface of the silicon wafer, and the film deposition thickness is 6nm. The silicon wafer that has been initially coated on the second surface is subjected to secondary coating using a third mixed gas, and a layer of P-type doped microcrystalline silicon film is deposited on the surface of the silicon wafer, and the film deposition thickness is 25nm. The third mixed gas is composed of a mixed gas of SiH4, H2, and B2H6, wherein the volume ratio of SiH4 to H2 is 1:300. The volume proportion of B2H6 doping is 1%. Transparent conductive film layer 2 is deposited on both sides of the silicon wafer: transparent conductive film layer 2 or other passivation anti-reflection film layer is continuously deposited on both sides of the silicon wafer (first surface and second surface). In this step, a general PVD sputtering device can be used to process both sides of the silicon wafer. The deposition thickness of transparent conductive film layer 2 is 100nm. Metal auxiliary grid line layer 12 is prepared on both sides of the silicon wafer: metal auxiliary grid lines are printed on the first surface and second surface of the silicon wafer, and metal main grid lines are printed on the first surface and second surface of the silicon wafer, and then dried and shaped. Sintering and curing: the silicon wafer is sent to a curing furnace for sintering to prepare a finished solar cell. Among them, the curing furnace temperature is 180°C and the sintering time is 26min.

[0076] like Figure 2 As shown, the structure of the second solar cell obtained in Comparative Example 1 is as follows Figure 2 As shown, from the front to the back are the conduit 11, the metal sub-gate line layer 12, the transparent conductive film layer 2, the doped N-type microcrystalline or amorphous silicon layer 3, the intrinsic amorphous silicon layer 6, the velvet structure layer 5, the single crystal silicon sheet layer 6, the velvet structure layer 5, the intrinsic amorphous silicon layer 6, the doped P-type microcrystalline or amorphous silicon layer 7, the transparent conductive film layer 2, the metal sub-gate line layer 12, and the conduit 11.

[0077] Comparative Example 2:

[0078] A thin film is directly made on the battery cell prepared in Comparative Example 1 to obtain a finished battery cell. The specific preparation method is as follows:

[0079] Preparation of the second solar cell: polishing and cleaning the surface of the silicon wafer: use the first alkaline solution to clean the monocrystalline silicon wafer to remove the damage layer on the surface of the silicon wafer caused by cutting with tools such as diamond wire. Among them, the first alkaline solution can be a mixed solution of potassium hydroxide solution and hydrogen peroxide, the concentration of potassium hydroxide solution is 7%; the concentration of hydrogen peroxide is 8%. The temperature of the first alkaline solution is 70°C, and the cleaning time is 300s. Texturing: use a mixed solution composed of potassium hydroxide and a texturing additive to clean the surface of the silicon wafer to prepare a velvet structure layer 5 on both sides of the silicon wafer, and the velvet structure layer 5 is pyramid-shaped. The solution temperature is 80°C; the cleaning time is 420s. Among them, the concentration of potassium hydroxide is 3%; the concentration of the texturing additive is 1%. The size of the velvet on the second surface of the prepared silicon wafer is 5um. Passivation: use the first acidic solution to clean the surface of the silicon wafer to passivate the surface of the silicon wafer. The first acidic solution can be a hydrofluoric acid solution, the solution concentration is 5%; the solution temperature is 25°C; the cleaning time is 200s. Coating: The first surface of the silicon wafer is coated to form an amorphous silicon thin film layer and an N-type doped microcrystalline or amorphous silicon thin film layer. The first mixed gas is used to perform the initial coating on the first surface of the silicon wafer treated in step S3, and an amorphous silicon thin film layer is deposited on the first surface of the silicon wafer, and the film deposition thickness is 5nm. The first mixed gas is composed of SiH4 and H2 mixed gas, and the mixed volume ratio is 1:5. The second mixed gas is used to perform the secondary coating on the silicon wafer that has been coated initially, and a N-type doped microcrystalline or amorphous silicon thin film layer is deposited on the surface of the silicon wafer, and the film deposition thickness is 20nm. The second mixed gas is composed of SiH4, H2, and PH3 mixed gas, wherein the SiH4 and H2 mixed volume ratio is 1:300. The PH3 doping volume accounts for 4%. The second surface of the silicon wafer is coated to form an amorphous silicon thin film layer and a P-type doped microcrystalline or amorphous silicon thin film layer: The first mixed gas is used to perform the initial coating on the second surface of the silicon wafer, and an amorphous silicon thin film is deposited on the second surface of the silicon wafer, and the film deposition thickness is 6nm. The silicon wafer that has been initially coated on the second surface is subjected to secondary coating using a third mixed gas, and a layer of P-type doped microcrystalline silicon film is deposited on the surface of the silicon wafer, and the film deposition thickness is 25nm. The third mixed gas is composed of a mixed gas of SiH4, H2, and B2H6, wherein the volume ratio of SiH4 to H2 is 1:300. The volume proportion of B2H6 doping is 1%. Transparent conductive film layer 2 is deposited on both sides of the silicon wafer: transparent conductive film layer 2 or other passivation anti-reflection film layer is continuously deposited on both sides of the silicon wafer (first surface and second surface). In this step, a general PVD sputtering device can be used to process both sides of the silicon wafer. The deposition thickness of transparent conductive film layer 2 is 100nm. Metal auxiliary grid line layer 12 is prepared on both sides of the silicon wafer: metal auxiliary grid lines are printed on the first surface and second surface of the silicon wafer, and metal main grid lines are printed on the first surface and second surface of the silicon wafer, and then dried and shaped. Sintering and curing: the silicon wafer is sent to a curing furnace for sintering to prepare a finished solar cell. Among them, the curing furnace temperature is 180°C and the sintering time is 26min.A SiO2 protective film layer is deposited on the obtained battery cell, and the protective film layer is specifically attached to the metal main grid line.

[0080] The finished cell sheets prepared in the above-mentioned Examples 1-3 and Comparative Examples 1-2 were tested for their cell conversion efficiency (Eta) and monitoring time using a solar cell tester (such as the IV tester provided by Maxwell). The specific test results are summarized in the following table:

[0081]

[0082] From the test results, it can be seen that the battery conversion efficiency of the battery cell prepared in Example 1 decayed from 25.09% to 25.08% within 30 days. The battery conversion efficiency of the battery cell prepared in Example 2 decayed from 25.08% to 25.07% within 30 days, and the battery conversion efficiency of the battery cell prepared in Example 3 decayed from 25.12% to 25.10% within 30 days, which is significantly better than the battery cells of Comparative Examples 1-2. In addition, the average welding tensile force of welding Examples 1-3 is also significantly better than Comparative Example 2, and the average welding tensile force of the battery cells of Examples 2-3 is better than Comparative Example 1.

[0083] The present invention and its embodiments are described schematically above, and the description is not restrictive. The drawings show only one embodiment of the present invention, and the actual structure is not limited thereto. Therefore, if a person skilled in the art is inspired by it and designs a structural method and an embodiment similar to the technical solution without creativity without departing from the purpose of the invention, they shall all fall within the protection scope of the present invention.

Claims

1. A highly reliable solar cell comprising a single crystal silicon layer (6), characterized in that: A velvet structure layer (5), an intrinsic amorphous silicon layer (4), a doped microcrystalline or amorphous silicon layer, a transparent conductive film layer (2), a metal secondary gate line layer (12), a protective film layer (8) and a concentrator (11) are prepared on the surface of the single crystal silicon layer (6); Wherein, the protective film layer (8) covers between the metal secondary grid line layer (12) and the collector (11).

2. The highly reliable solar cell according to claim 1, characterized in that: Both sides of the solar cell are covered with the protective film layer (8).

3. The highly reliable solar cell according to claim 2, characterized in that: The doped microcrystalline or amorphous silicon layer comprises a doped N-type microcrystalline or amorphous silicon layer (3) and a doped P-type microcrystalline or amorphous silicon layer (7); A velvet structure layer (5), an intrinsic amorphous silicon layer (4), a doped N-type microcrystalline or amorphous silicon layer (3), a transparent conductive film layer (2), a metal secondary gate line layer (12), a protective film layer (8), and a concentrator (11) are sequentially deposited on one side of the single crystal silicon layer (6); The other side of the single crystal silicon layer (6) is sequentially stacked with a velvet structure layer (5), an intrinsic amorphous silicon layer (4), a doped P-type microcrystalline or amorphous silicon layer (7), a transparent conductive film layer (2), a metal secondary gate line layer (12), a protective film layer (8), and a collector (11).

4. The highly reliable solar cell according to claim 1, characterized in that: The protective film layer (8) comprises one or a combination of silicon oxide, silicon nitride, lithium fluoride, magnesium fluoride, titanium oxide, and aluminum oxide materials.

5. The highly reliable solar cell according to any one of claims 1 to 4, characterized in that: The protective film layer (8) has a thickness of 0.1 to 100 nm.

6. A method for preparing a solar cell with high reliability, characterized in that: The surface of the single crystal silicon wafer is polished and cleaned, textured, thin film deposited, and metal gate lines printed in sequence, so as to form a texture structure layer (5), an intrinsic amorphous silicon layer (4), a doped microcrystalline or amorphous silicon layer, a transparent conductive film layer (2), a metal sub-gate line layer (12), and a concentrator (11) in sequence on the surface of the single crystal silicon wafer; A protective film is deposited between the metal secondary grid line layer (12) and the collector (11) to form a protective film layer (8) covering the metal secondary grid line layer (12), and after sintering and curing, a finished solar cell is formed.

7. The method for preparing a solar cell with high reliability according to claim 6, characterized in that: Polishing and cleaning the single crystal silicon wafer comprises: S1: using a first alkaline solution to clean and polish the monocrystalline silicon wafer to remove a damaged layer on the surface of the solar cell.

8. The method for preparing a solar cell with high reliability according to claim 7, characterized in that: The texturing of the single crystal silicon wafer comprises: S2: using a texturing solution to clean the surface of the single crystal silicon wafer treated in step S1, so as to prepare a uniformly distributed texturing structure layer (5) on the surface of the silicon wafer.

9. The method for preparing a solar cell with high reliability according to claim 8, characterized in that: The silicon wafer processed in step S2 is deposited with a thin film, including: S3: using a first acidic solution to clean the surface of the silicon wafer to passivate the surface of the silicon wafer; S4: depositing a layer of intrinsic amorphous silicon layer (4) on both sides of the silicon wafer processed in S3, and then depositing a doped N-type microcrystalline or amorphous silicon layer (3) on the intrinsic amorphous silicon layer on the second surface of the silicon wafer; and depositing a P-type doped amorphous or microcrystalline silicon layer (7) on the intrinsic amorphous silicon layer on the first surface of the silicon wafer; A transparent conductive thin film layer (2) is deposited on both sides of the silicon wafer.

10. The method for preparing a solar cell with high reliability according to claim 9, characterized in that: S5: printing a metal secondary gate line layer (12) on both sides of the silicon wafer processed in step S4, The protective film layer is deposited on the metal secondary grid line layer (12) respectively, Printing the confluence bodies (11) on the protective film layers respectively; S6: Sintering and curing the silicon wafer prepared in S5 to prepare a finished solar cell.

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