Laminated cell and preparation method thereof

Abstract

The invention relates to the technical field of solar cells, and discloses a laminated cell and a preparation method thereof, and the laminated cell comprises a perovskite cell structure, a first composite layer, a second composite layer and a crystalline silicon cell structure which are sequentially laminated from a light receiving surface to a backlight surface. The doping concentration of the conductive impurities in the first composite layer is gradually increased in a gradient manner along the direction from the perovskite cell structure to the second composite layer; and the doping concentration of the conductive impurities in the second composite layer is gradually reduced in a gradient manner along the direction from the first composite layer to the crystalline silicon cell structure. The part with the relatively high doping concentration of the conductive impurities maximizes the transmission efficiency of current carriers and reduces the recombination loss, and the part with the relatively low doping concentration of the conductive impurities reduces the recombination loss of interface joints, so that the overall performance of the laminated cell is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a stacked cell and a preparation method thereof. Background Art

[0002] Perovskite-crystalline silicon stacked cells are a new type of solar cell structure, which is a superposition of perovskite solar cells and crystalline silicon solar cells. Since perovskite solar cells and crystalline silicon solar cells absorb high-energy and low-energy light respectively, they can more effectively utilize solar energy within the spectral range. In addition, perovskite materials have a higher light absorption coefficient and higher photoelectric conversion efficiency, while crystalline silicon materials have a longer life and better stability. By combining these two materials, their advantages can be fully utilized to achieve higher overall performance.

[0003] In perovskite crystalline silicon tandem cells, a composite layer is often set between the perovskite solar cell and the crystalline silicon solar cell to promote the effective transfer of charge between the perovskite solar cell and the crystalline silicon solar cell, while reducing the recombination loss. However, when the concentration of conductive impurities in the composite layer is too low, the charge transfer efficiency between the perovskite solar cell and the crystalline silicon solar cell will be reduced, and the recombination loss will increase; and when the concentration of conductive impurities in the composite layer is too high, the recombination rate at the interface of the perovskite solar cell and the crystalline silicon solar cell will increase, resulting in a decrease in the output current, making it difficult to control the doping amount of conductive impurities in the composite layer. Summary of the invention

[0004] In view of this, the present invention provides a stacked cell and a preparation method to solve the problem that it is difficult to control the doping amount of conductive impurities in the composite layer in the existing perovskite crystalline silicon stacked cell.

[0005] In a first aspect, the present invention provides a stacked cell, comprising a perovskite cell structure, a first composite layer, a second composite layer, and a crystalline silicon cell structure stacked in sequence from a light-receiving surface to a backlight surface;

[0006] The doping concentration of the conductive impurities in the first composite layer increases gradually along the direction from the perovskite cell structure to the second composite layer;

[0007] The doping concentration of the conductive impurities in the second composite layer decreases gradually along the direction from the first composite layer to the crystalline silicon cell structure.

[0008] Beneficial effects: Since the doping concentration of the conductive impurities in the first composite layer increases gradually along the direction from the perovskite cell to the second composite layer, the conductivity of the first composite layer increases gradually along the direction from the perovskite cell to the second composite layer, so that the carrier transfer efficiency of the first composite layer increases gradually along the direction from the perovskite cell to the second composite layer. In addition, the portion of the first composite layer with a relatively low doping concentration of the conductive impurities can slow down the carrier transfer efficiency to reduce interface defects, thereby reducing the recombination loss at the interface with the perovskite cell structure. In addition, the portion of the first composite layer with a relatively high doping concentration of the conductive impurities can maximize the carrier transfer efficiency and increase the carrier recombination rate to reduce resistance losses. Since the doping concentration of the conductive impurities in the second composite layer decreases gradually along the direction from the first composite layer to the crystalline silicon battery structure, the conductivity of the second composite layer decreases gradually along the direction from the first composite layer to the crystalline silicon battery structure, so that the carrier transmission efficiency of the first composite layer decreases gradually along the direction from the first composite layer to the crystalline silicon battery structure. In addition, the portion with a relatively low doping concentration of the conductive impurities in the second composite layer can slow down the transmission efficiency of the carriers to reduce interface defects, thereby reducing the recombination loss at the interface with the crystalline silicon battery structure and improving the transmission stability of the carriers. The portion with a relatively high doping concentration of the conductive impurities in the second composite layer can maximize the transmission efficiency of the carriers and increase the recombination rate of the carriers to reduce the resistance loss. In the first composite layer and the second composite layer, the portion with a relatively high doping concentration of the conductive impurities maximizes the transmission efficiency of the carriers and reduces the resistance loss, and the portion with a relatively low doping concentration of the conductive impurities reduces the recombination loss at the interface connection, thereby improving the overall performance of the stacked battery.

[0009] In an optional embodiment, the gradient increase is a linear increase or a nonlinear increase, and the gradient decrease is a linear decrease or a nonlinear decrease.

[0010] Different concentration gradients can be adjusted according to different stacked batteries, so as to adapt to more different stacked batteries, thereby improving the applicability of the stacked batteries.

[0011] In an optional embodiment, the first composite layer includes:

[0012] A first doped layer, located between the perovskite cell structure and the second composite layer;

[0013] a second doped layer, located between the first doped layer and the second composite layer;

[0014] The doping concentration of the conductive impurities in the second doping layer is greater than the doping concentration of the conductive impurities in the first doping layer.

[0015] By doping the first doping layer and the second doping layer with conductive impurities of different concentrations, a gradient increase in the doping concentration in the first composite layer can be achieved, avoiding doping of conductive impurities of different concentrations in the same layer, reducing processing difficulty and improving production efficiency.

[0016] In an optional embodiment, the second composite layer includes:

[0017] A third doped layer, located between the second doped layer and the crystalline silicon cell structure;

[0018] A fourth doped layer, located between the third doped layer and the crystalline silicon cell structure;

[0019] The doping concentration of the conductive impurities in the fourth doping layer is lower than the doping concentration of the conductive impurities in the third doping layer.

[0020] By doping the third doping layer and the fourth doping layer with conductive impurities of different concentrations, a gradient decrease in the doping concentration in the second composite layer can be achieved, avoiding doping of conductive impurities of different concentrations in the same layer, reducing processing difficulty and improving production efficiency.

[0021] In an optional embodiment, the perovskite cell structure has a first transmission layer, the first transmission layer is located on a surface of the first doping layer on a side away from the second doping layer, and the first transmission layer and the first doping layer have the same conductivity type;

[0022] The crystalline silicon cell has a second transmission layer, which is located on a surface of the fourth doping layer that is away from the third doping layer, and the second transmission layer has the same conductivity type as the fourth doping layer.

[0023] The first transmission layer has the same conductivity type as the first doping layer to ensure the continuity of carrier transmission between the perovskite cell structure and the first composite layer. The second transmission layer has the same conductivity type as the fourth doping layer to ensure the continuity of carrier transmission between the second composite layer and the crystalline silicon cell structure, thereby ensuring the smoothness of carrier transmission between the perovskite cell structure and the crystalline silicon cell structure, thereby reducing the resistance loss of carriers.

[0024] In an optional embodiment, the doping concentration of the conductive impurities in the first composite layer and the second composite layer is less than or equal to 10 20 cm -3 .

[0025] When the doping concentration of conductive impurities is greater than 10 20 cm -3 When the number of defects in the recombination layer increases, the carrier recombination ratio increases, which in turn leads to an increase in recombination loss.

[0026] In an optional embodiment, the sum of the thicknesses of the first composite layer and the second composite layer is less than or equal to 120 nm.

[0027] When the thickness of the first composite layer and the second composite layer is greater than 120 nm, the carrier transmission path will be too long, which will increase the resistance loss and reduce the light absorption, thereby reducing the photoelectric conversion efficiency of the stacked battery.

[0028] In an optional embodiment, the perovskite cell is capable of at least absorbing light in a first wavelength band and transmitting light in a second wavelength band;

[0029] The crystalline silicon cell can at least absorb light in the second wavelength band.

[0030] The perovskite cell absorbs light in the first band, while the crystalline silicon cell structure absorbs light in the second band, thereby achieving light absorption in a wider spectral range and further improving the photoelectric conversion efficiency of the stacked cell.

[0031] In an optional embodiment, the crystalline silicon cell structure includes any one of a tunneling oxide layer passivation contact cell, a heterojunction thin layer cell, and an emitter back passivation cell.

[0032] Different crystalline silicon cell structures and perovskite cell structures can be used to realize a stacked cell, thereby improving the applicability of the stacked cell.

[0033] In a second aspect, the present invention provides a method for preparing a stacked battery, comprising:

[0034] Forming a crystalline silicon cell structure;

[0035] forming a second composite layer on a surface of one side of the crystalline silicon cell structure;

[0036] Forming a first composite layer on a surface of the second composite layer on a side away from the crystalline silicon cell structure;

[0037] Forming a perovskite cell on a surface of the first composite layer facing away from the second composite layer;

[0038] Wherein, the doping concentration of the conductive impurities in the first composite layer increases gradually along the direction from the perovskite cell to the second composite layer;

[0039] The doping concentration of the conductive impurities in the second composite layer decreases gradually along the direction from the first composite layer to the crystalline silicon cell structure.

[0040] Beneficial effect: the preparation method of the stacked battery is simple and easy to implement. In addition, in the first composite layer and the second composite layer, the portion with a relatively high conductive impurity doping concentration maximizes the carrier transmission efficiency and reduces the resistance loss, and the portion with a relatively low conductive impurity doping concentration reduces the recombination loss at the interface connection, thereby improving the overall performance of the stacked battery. The first composite layer and the second composite layer can improve the photoelectric conversion efficiency and long-term stability of the stacked battery to ensure efficient and stable operation of the stacked battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0042] Figure 1 It is a schematic diagram of the structure of the crystalline silicon battery structure intermediate and the second transmission layer in the preparation of the stacked battery in an embodiment of the present invention;

[0043] Figure 2 It is a schematic diagram of the structure of the crystalline silicon battery structure intermediate, the second transmission layer, and the fourth doping layer in the preparation of the stacked battery in an embodiment of the present invention;

[0044] Figure 3 It is a schematic diagram of the structure of the crystalline silicon cell structure intermediate, the second transmission layer, the fourth doping layer, and the third doping layer in the preparation of the stacked cell in an embodiment of the present invention;

[0045] Figure 4 It is a schematic diagram of the structure of a crystalline silicon cell structure intermediate, a second transmission layer, a fourth doping layer, a third doping layer, and a second doping layer in the preparation of a stacked cell in an embodiment of the present invention;

[0046] Figure 5 It is a schematic diagram of the structure of a crystalline silicon cell structure intermediate, a second transmission layer, a fourth doping layer, a third doping layer, a second doping layer, and a first doping layer in the preparation of a stacked cell in an embodiment of the present invention;

[0047] Figure 6 It is a schematic diagram of the structure of a crystalline silicon cell structure intermediate, a second transmission layer, a fourth doping layer, a third doping layer, a second doping layer, a first doping layer, and a first transmission layer in the preparation of a stacked cell in an embodiment of the present invention;

[0048] Figure 7 It is a schematic diagram of the structure of a crystalline silicon cell structure intermediate, a second transmission layer, a fourth doping layer, a third doping layer, a second doping layer, a first doping layer, a first transmission layer, and a perovskite layer in the preparation of a stacked cell in an embodiment of the present invention;

[0049] Figure 8 It is a schematic diagram of the structure of a crystalline silicon cell structure intermediate, a second transmission layer, a fourth doping layer, a third doping layer, a second doping layer, a first doping layer, a first transmission layer, a perovskite layer, and a third transmission layer in the preparation of a stacked cell in an embodiment of the present invention;

[0050] Fig. 9 It is a schematic diagram of the structure of a crystalline silicon cell structure intermediate, a second transmission layer, a fourth doping layer, a third doping layer, a second doping layer, a first doping layer, a first transmission layer, a perovskite layer, a third transmission layer, and a transparent electrode layer in the preparation of a stacked cell in an embodiment of the present invention;

[0051] Fig.10 It is a schematic diagram of the structure of a crystalline silicon cell structure intermediate, a second transmission layer, a fourth doping layer, a third doping layer, a second doping layer, a first doping layer, a first transmission layer, a perovskite layer, a third transmission layer, a transparent electrode layer, and a passivation layer in the preparation of a stacked cell in an embodiment of the present invention;

[0052] Fig.11 It is a schematic diagram of the structure of a crystalline silicon battery structure intermediate, a second transmission layer, a fourth doping layer, a third doping layer, a second doping layer, a first doping layer, a first transmission layer, a perovskite layer, a third transmission layer, a transparent electrode layer, a passivation layer, a first electrode layer, and a second electrode layer in the preparation of a stacked battery in an embodiment of the present invention.

[0053] Description of reference numerals:

[0054] 100, perovskite cell structure; 101, first transmission layer; 102, perovskite layer; 103, third transmission layer; 104, transparent conductive layer; 105, passivation layer; 106, first electrode;

[0055] 201, first composite layer; 2011, first doped layer; 2012, second doped layer; 202, second composite layer; 2021, third doped layer; 2022, fourth doped layer;

[0056] 300, crystalline silicon cell structure; 301, second transmission layer; 302, intermediate; 303, second electrode. DETAILED DESCRIPTION

[0057] The present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It is understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only some structures related to the present invention are shown in the accompanying drawings, rather than all structures. In the following description, the description of known structures and technologies is omitted to avoid unnecessary confusion of the concept of the present invention. Various structural schematic diagrams according to embodiments of the present invention are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified for the purpose of clear expression, and some details may be omitted. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships between them are only exemplary, and may be deviated due to manufacturing tolerances or technical limitations in practice, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs. In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. In addition, if one layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0058] In the related art, a composite layer is often provided between the perovskite solar cell and the crystalline silicon solar cell, and the composite layer is doped with conductive impurities, in order to promote the effective transfer of charges between the perovskite solar cell and the crystalline silicon solar cell, while reducing the recombination loss. However, when the concentration of the conductive impurities in the composite layer is too low, the charge transfer efficiency between the perovskite solar cell and the crystalline silicon solar cell will be reduced, and the recombination loss will increase; and when the concentration of the conductive impurities in the composite layer is too high, the recombination rate at the interface between the perovskite solar cell and the crystalline silicon solar cell will increase, resulting in a decrease in the output current, making it difficult to control the doping amount of the conductive impurities in the composite layer.

[0059] Therefore, an embodiment of the present invention provides a stacked battery, by adding a first composite layer 201 and a second composite layer 202 between the perovskite battery structure 100 and the crystalline silicon battery structure 300, and the doping concentration of the conductive impurities in the first composite layer 201 increases gradually along the direction from the perovskite battery structure 100 to the second composite layer 202, and the doping concentration of the conductive impurities in the second composite layer 202 decreases gradually along the direction from the first composite layer 201 to the crystalline silicon battery structure 300. The portion with a relatively high conductive impurity doping concentration maximizes the carrier transmission efficiency and reduces the recombination loss, and the portion with a relatively low conductive impurity doping concentration reduces the recombination loss at the interface connection, thereby improving the overall performance of the stacked battery.

[0060] An embodiment of the present invention provides a laminated battery, such as Fig.11As shown, it includes a perovskite cell structure 100, a first composite layer 201, a second composite layer 202, and a crystalline silicon cell structure 300 which are stacked in sequence from the light-receiving surface to the backlight surface; the doping concentration of the conductive impurities in the first composite layer 201 increases gradually along the direction from the perovskite cell structure 100 to the second composite layer 202; the doping concentration of the conductive impurities in the second composite layer 202 decreases gradually along the direction from the first composite layer 201 to the crystalline silicon cell structure 300.

[0061] Specifically, the perovskite battery structure 100 includes a first electrode 106, a passivation layer 105, a transparent conductive layer 104, a third transmission layer 103, a perovskite layer 102, and a first transmission layer 101. The first transmission layer 101 is located on the surface of the first composite layer 201 away from the second composite layer 202. The first transmission layer 101 can be a hole transmission layer or an electron transmission layer. The first transmission layer 101 is described as a hole transmission layer. The first transmission layer 101 is used to transmit the holes generated in the perovskite layer 102 to the first composite layer 201 and block the electrons from being transmitted to the perovskite layer 102, thereby helping to reduce the recombination loss of carriers. In addition, the first transmission layer 101 can be a single layer or a multilayer structure. Preferably, in the present embodiment, the first transmission layer 101 is a multilayer structure, that is, the first transmission layer 101 is formed by stacking multiple layers in sequence. The thickness, doping concentration, and material of each layer in the multilayer structure can be adjusted as needed, so as to optimize the specific carrier transmission characteristics, so as to improve the carrier transmission effect and reduce the recombination loss. The perovskite layer 102 is located on the surface of the first transmission layer 101 on the side away from the first composite layer 201. The perovskite layer 102 is used to absorb sunlight and generate electrons and holes through the light absorption process. The perovskite layer 102 uses a material with a band gap width of 1.6-1.9 eV, so that the perovskite layer 102 absorbs short-wave photons in sunlight and generates holes and electrons. The perovskite layer 102 can be a single layer or a multilayer structure. Preferably, the perovskite layer 102 in this embodiment is a multilayer structure. The multilayer structure can adjust the material composition of each layer to improve the light absorption performance and expand the light absorption range of the perovskite layer 102, so that it can capture sunlight in a wider spectral range. In addition, the design of the multilayer structure can reduce interface defects, thereby reducing recombination losses, and thus improving the separation performance of carriers. The third transport layer 103 is located on the surface of the side of the perovskite layer 102 away from the first transport layer 101. The conductivity type of the third transport layer 103 is opposite to that of the first transport layer 101. When the first transport is a hole transport layer, the third transport layer 103 is an electron transport layer. When the first transport layer 101 is an electron transport layer, the third transport layer 103 is a hole transport layer. This embodiment takes the third transport layer 103 as an electron transport layer as an example for explanation. The third transport layer 103 is used to transmit the electrons generated in the perovskite layer 102 to the first electrode 106 and block the holes from being transmitted to the perovskite layer 102, thereby helping to reduce the charge recombination loss. In addition, the third transport layer 103 can be a single layer or a multilayer structure. Preferably, in this embodiment, the third transport layer 103 is a multilayer structure, that is, the third transport layer 103 is formed by stacking multiple layers in sequence. The thickness, doping concentration, and material of each layer in the multilayer structure can be adjusted as needed, so as to optimize the specific carrier transport characteristics, so as to improve the carrier transport effect and reduce the recombination loss.The transparent conductive layer 104 is located on the side surface of the third transmission layer 103 away from the perovskite layer 102. The transparent conductive layer 104 is made of a transparent conductive oxide. The transparent conductive layer 104 is used to transmit incident light, collect the current generated in the perovskite layer 102, and transmit it to an external circuit. The passivation layer 105 is located on the side surface of the transparent conductive layer 104 away from the third transmission layer 103. The passivation layer 105 is used to protect the perovskite battery structure 100 and prevent the perovskite battery from being affected by the external environment. Preferably, the passivation layer 105 can be a multi-layer structure to enhance the protection effect. The first electrode 106 is a metal or other conductive material. The first electrode 106 is located on the side surface of the passivation layer 105 away from the transparent conductive layer 104. The first electrode 106 is used to collect current and transmit it to an external circuit. The first electrode 106 is located on the light-receiving surface. The first composite layer 201 is located between the perovskite battery structure 100 and the second composite layer 202. The first composite layer 201 is used to connect the perovskite battery structure 100 and the second composite layer 202. The doping concentration of the conductive impurities in the first composite layer 201 increases gradually along the direction from the perovskite battery structure 100 to the second composite layer 202. The second composite layer 202 is located between the first composite layer 201 and the crystalline silicon battery structure 300. The second composite layer 202 is used to connect the first composite layer 201 and the crystalline silicon battery structure 300. The doping concentration of the conductive impurities in the second composite layer 202 increases gradually along the direction from the perovskite battery structure 100 to the second composite layer 202. The degree of the first composite layer 201 gradually decreases from the first composite layer 201 to the crystalline silicon battery structure 300. The materials of the first composite layer 201 and the second composite layer 202 can be indium tin oxide, aluminum-doped zinc oxide, graphene, nano silver wire or other conductive and light-transmitting materials. The first composite layer 201 and the second composite layer 202 can be a single layer or a multilayer structure. The design of the doping concentration of the first composite layer 201 and the second composite layer 202 can improve the charge transfer efficiency and reduce the composite loss. The materials and composition of the perovskite battery structure 100 are all existing technologies and will not be described in detail here. Fig.11 As shown, the perovskite cell structure 100 is located above the crystalline silicon cell, and the first electrode 106 is located on the light-receiving surface, so the perovskite cell structure 100 receives the incident light first, and the crystalline silicon cell structure 300 located below the perovskite cell structure 100 receives the incident light later. Since the band gap width of the absorption layer in the perovskite cell structure 100 is greater than the band gap width of the absorption layer in the crystalline silicon cell structure 300, the perovskite cell is placed above the crystalline silicon cell so that the perovskite cell is used to absorb short-wavelength sunlight, and the crystalline silicon cell structure 300 is used to absorb long-wavelength sunlight.

[0062] In this embodiment, since the doping concentration of the conductive impurities in the first composite layer 201 increases gradually along the direction from the perovskite cell to the second composite layer 202, the conductivity of the first composite layer 201 increases gradually along the direction from the perovskite cell structure 100 to the second composite layer 202, so that the carrier transmission efficiency of the first composite layer 201 increases gradually along the direction from the perovskite cell to the second composite layer 202. In addition, the portion of the first composite layer 201 with a relatively low doping concentration of conductive impurities can slow down the carrier transmission efficiency to reduce interface defects, thereby reducing the recombination loss at the interface with the perovskite cell structure 100. In addition, the portion of the first composite layer 201 with a relatively high doping concentration of conductive impurities can maximize the carrier transmission efficiency and increase the carrier recombination rate to reduce resistance losses. Since the doping concentration of the conductive impurities in the second composite layer 202 decreases gradually along the direction from the first composite layer 201 to the crystalline silicon battery structure 300, the conductivity of the second composite layer 202 decreases gradually along the direction from the first composite layer 201 to the crystalline silicon battery structure 300, so that the carrier transmission efficiency of the first composite layer 201 decreases gradually along the direction from the first composite layer 201 to the crystalline silicon battery structure 300. In addition, the portion with a relatively low doping concentration of the conductive impurities in the second composite layer 202 can slow down the transmission efficiency of the carriers to reduce interface defects, thereby reducing the recombination loss at the interface with the crystalline silicon battery structure 300 and improving the transmission stability of the carriers. The portion with a relatively high doping concentration of the conductive impurities in the second composite layer 202 can maximize the transmission efficiency of the carriers and increase the recombination rate of the carriers to reduce the resistance loss. In the first composite layer 201 and the second composite layer 202, the portion with a relatively high doping concentration of the conductive impurities maximizes the transmission efficiency of the carriers and reduces the resistance loss, and the portion with a relatively low doping concentration of the conductive impurities reduces the recombination loss at the interface connection, thereby improving the overall performance of the laminated battery.

[0063] In this embodiment, the doping concentration of the conductive impurities in the first composite layer 201 increases gradually along the direction from the perovskite battery structure 100 to the second composite layer 202. The gradient increase may be a linear increase or a nonlinear increase, that is, the doping concentration of the conductive impurities in the first composite layer 201 increases gradually along the direction from the perovskite battery structure 100 to the second composite layer 202 (linear increase), or the doping concentration of the conductive impurities in the first composite layer 201 increases randomly along the direction from the perovskite battery structure 100 to the second composite layer 202 (nonlinear increase, with a different concentration each time). The doping concentration of the conductive impurities in the second composite layer 202 decreases gradually along the direction from the first composite layer 201 to the crystalline silicon battery structure 300. The gradient decrease can be linear or nonlinear, that is, the doping concentration of the conductive impurities in the second composite layer 202 gradually decreases from the first composite layer 201 to the crystalline silicon battery structure 300 (linear decrease), or the doping concentration of the conductive impurities in the second composite layer 202 decreases randomly from the first composite layer 201 to the crystalline silicon battery structure 300 (nonlinear decrease, each time the concentration decreases differently). Different concentration gradients can be adjusted according to different laminated batteries, so as to adapt to more different laminated batteries, thereby improving the applicability of the laminated battery.

[0064] In this embodiment, the first composite layer 201 includes a first doping layer 2011 and a second doping layer 2012. The first doping layer 2011 is located between the perovskite cell structure 100 and the second composite layer 202. The second doping layer 2012 is located between the first doping layer 2011 and the second composite layer 202. The doping concentration of the conductive impurities in the second doping layer 2012 is greater than the doping concentration of the conductive impurities in the first doping layer 2011. The first doping layer 2011 and the second doping layer 2012 are both conductive impurities doped in polycrystalline silicon. The conductive impurities in the first doping layer 2011 and the conductive impurities in the second doping layer 2012 may have the same conductivity type or may be opposite. By doping the first doping layer 2011 and the second doping layer 2012 with conductive impurities of different concentrations, the doping concentration gradient in the first composite layer 201 can be increased, avoiding the doping of conductive impurities of different concentrations in the same layer, reducing the processing difficulty, and improving the production efficiency.

[0065] In this embodiment, as an alternative implementation, the first composite layer 201 includes multiple (three or more) doping layers, and the multiple doping layers are stacked in sequence from top to bottom, and the doping concentration of the conductive impurities in the multiple doping layers increases layer by layer from top to bottom.

[0066] In this embodiment, the second composite layer 202 includes a third doping layer 2021 and a fourth doping layer 2022. The third doping layer 2021 is located between the second doping layer 2012 and the crystalline silicon battery structure 300. The fourth doping layer 2022 is located between the third doping layer 2021 and the crystalline silicon battery structure 300. The doping concentration of the conductive impurities in the fourth doping layer 2022 is less than the doping concentration of the conductive impurities in the third doping layer 2021. The third doping layer 2021 and the fourth doping layer 2022 are both polycrystalline silicon doped with conductive impurities. The conductive impurities in the third doping layer 2021 and the conductive impurities in the fourth doping layer 2022 may have the same conductivity type or may be opposite. By doping the third doping layer 2021 and the fourth doping layer 2022 with conductive impurities of different concentrations, the doping concentration gradient in the second composite layer 202 can be increased, avoiding the doping of conductive impurities of different concentrations in the same layer, reducing the processing difficulty, and improving the production efficiency. The doping concentration of the conductive impurities in the third doping layer 2021 may be the same as the doping concentration of the conductive impurities in the second doping layer 2012 , or the doping concentration of the conductive impurities in the third doping layer 2021 may be lower than the doping concentration of the conductive impurities in the second doping layer 2012 .

[0067] In this embodiment, as an alternative implementation, the second composite layer 202 includes multiple (three or more) doping layers, and the multiple doping layers are stacked in sequence from top to bottom, and the doping concentration of conductive impurities in the multiple doping layers decreases from top to bottom, layer by layer.

[0068] In this embodiment, the first transmission layer 101 has the same conductivity type as the first doping layer 2011, and the crystalline silicon battery structure 300 has a second transmission layer 301, which is located on the side surface of the fourth doping layer 2022 away from the third doping layer 2021, and the second transmission layer 301 has the same conductivity type as the fourth doping layer 2022. The first transport layer 101 and the second transport layer 301 can both be electron transport layers or hole transport layers. Taking the example that the first transport layer 101 and the second transport layer 301 are both hole transport layers, the first doping layer 2011 and the fourth doping layer 2022 are both hole transport layers. The first transport layer 101 and the first doping layer 2011 have the same conductivity type to ensure the continuity of carrier transport between the perovskite battery structure 100 and the first composite layer 201. The second transport layer 301 and the fourth doping layer 2022 have the same conductivity type to ensure the continuity of carrier transport between the second composite layer 202 and the crystalline silicon battery structure 300, thereby ensuring the smoothness of carrier transport between the perovskite battery structure 100 and the crystalline silicon battery structure 300, thereby reducing the resistance loss of carriers.

[0069] In this embodiment, the doping concentration of the conductive impurities in the first composite layer 201 and the second composite layer 202 is less than or equal to 1020 cm -3 (the amount of conductive impurities doped / per cubic centimeter), when the doping concentration of conductive impurities is greater than 10 20 cm -3 When the number of defects in the recombination layer increases, the carrier recombination ratio increases, which in turn leads to an increase in recombination loss.

[0070] In this embodiment, the sum of the thicknesses of the first composite layer 201 and the second composite layer 202 is less than or equal to 120 nm (nanometers). When the thicknesses of the first composite layer 201 and the second composite layer 202 are greater than 120 nm, the carrier transmission path will be too long, resulting in increased resistance loss and reduced light absorption, which will further reduce the photoelectric conversion efficiency of the stacked battery.

[0071] In this embodiment, the crystalline silicon cell structure 300 includes any one of a tunneling oxide layer passivation contact cell, a heterojunction thin layer cell, and an emitter back passivation cell. The crystalline silicon cell structure 300 is located below the perovskite cell structure 100. The perovskite cell can at least absorb light in the first band and transmit light in the second band. The light in the first band is the ultraviolet band, and the second band is the visible light and infrared partial band. The crystalline silicon cell can at least absorb light in the second band. The perovskite cell absorbs the light in the first band, and the crystalline silicon cell structure 300 absorbs the light in the second band, thereby achieving light absorption in a wider spectral range, thereby improving the photoelectric conversion efficiency of the stacked cell. In addition, different crystalline silicon cell structures 300 and perovskite cell structures 100 can be used to realize the stacked cell, thereby improving the applicability of the stacked cell.

[0072] In a second aspect, the present invention provides a method for preparing a stacked battery, comprising the following steps:

[0073] S300, forming a crystalline silicon battery structure 300, the crystalline silicon battery structure 300 can be any one of a heterojunction thin-layer battery, an emitter back passivation battery, and a tunneling oxide layer passivation contact battery, and the preparation methods of the heterojunction thin-layer battery, the emitter back passivation battery, and the tunneling oxide layer passivation contact battery have been disclosed in the relevant technology. The preparation method of the heterojunction thin-layer battery is taken as an example for explanation below, and the preparation methods of other emitter back passivation batteries and tunneling oxide layer passivation contact batteries will not be repeated.

[0074] S301 , forming an intermediate body 302 of a crystalline silicon cell structure 300 .

[0075] S3011, providing an n-type silicon substrate; the material of the n-type silicon substrate can be n-type doped polycrystalline silicon or single crystal silicon, and then the n-type silicon substrate is cleaned and textured.

[0076] S3012, forming a first amorphous silicon layer and a second amorphous silicon layer on two opposite surfaces of the n-type silicon substrate respectively.

[0077] Specifically, a plasma enhanced chemical vapor deposition process may be used to form a first amorphous silicon layer and a second amorphous silicon layer on two opposite surfaces of the n-type silicon substrate.

[0078] S3013, forming a fourth transmission layer on a surface of the second amorphous silicon layer that is away from the n-type silicon substrate.

[0079] Specifically, the fourth transport layer may be formed by a vapor deposition process, and the fourth transport layer may be an electron transport layer or a hole transport layer; the material of the fourth transport layer is N-type amorphous silicon or P-type amorphous silicon.

[0080] S3014, forming a second transparent conductive film on a surface of the fourth transmission layer on a side away from the second amorphous silicon layer.

[0081] Specifically, the second transparent conductive film may be formed by a magnetron sputtering process, and the material of the second transparent conductive film is indium tin oxide.

[0082] S3015, preparing a second electrode 303 on a side of the second transparent conductive film away from the fourth transmission layer.

[0083] Specifically, the second electrode 303 may be formed on the second transparent conductive film by using a vacuum evaporation process, and the second electrode 303 may be metal or other conductive materials.

[0084] S302, such as Figure 1 As shown, a second transmission layer 301 is formed on the first amorphous silicon layer.

[0085] Specifically, the second transmission layer 301 can be formed by a vapor deposition process, and the material of the second transmission layer 301 is N-type amorphous silicon or P-type amorphous silicon. When the second transmission layer 301 is a hole transmission layer, the fourth transmission layer is an electron transmission layer. In this case, the second transmission layer 301 is P-type amorphous silicon, and the fourth transmission layer is N-type amorphous silicon. When the second transmission layer 301 is an electron transmission layer, the fourth transmission layer is a hole transmission layer. In this case, the second transmission layer 301 is N-type amorphous silicon, and the fourth transmission layer is P-type amorphous silicon.

[0086] S201, forming a second composite layer 202 on a surface of the second transmission layer 301 facing away from the intermediate 302;

[0087] S2011, as Figure 2 As shown, a fourth doping layer 2022 is formed on a surface of the second transmission layer 301 that is away from the intermediate body 302 .

[0088] Specifically, silane or disilane gas is used as a deposition source gas, and a vapor deposition process is used to form a polysilicon layer on the surface of the second transport layer 301 on the side away from the intermediate 302, wherein the deposition temperature is 550° C. to 650° C., and the thickness of the polysilicon layer is 10 to 20 nm. In this embodiment, the second transport layer 301 is an electron transport layer as an example for explanation. The fourth doped layer 2022 has the same conductivity type as the second transport layer 301, so phosphorus is doped by phosphine gas, and the temperature range of phosphorus doping is 600° C. to 900° C., and then heat treatment is used to diffuse phosphorus in the polysilicon layer, and the diffusion temperature is 800° C. to 1000° C., and the diffusion time is 10 to 60 minutes to form the fourth doped layer 2022, and the doping concentration of the fourth doped layer 2022 is 10 18 cm -3 To ensure that the conductivity of the fourth doping layer 2022 meets the set requirements.

[0089] S2012, as Figure 3 As shown, the third doping layer 2021 is formed on the surface of the fourth doping layer 2022 which is away from the second transmission layer 301 .

[0090] Specifically, the conductivity type of the third doping layer 2021 is the same as or opposite to the conductivity type of the fourth doping layer 2022. This embodiment is described by taking the conductivity type of the third doping layer 2021 and the conductivity type of the fourth doping layer 2022 as opposite as an example. Silane or disilane gas is used as a deposition source gas, and a vapor deposition process is adopted to form a polycrystalline silicon layer on the surface of the side of the fourth doping layer 2022 away from the second transmission layer 301, wherein the deposition temperature is between 550°C and 650°C to ensure that the polycrystalline silicon layer is evenly covered on the fourth doping layer 2022. The thickness of the polycrystalline silicon layer is between 10 and 20 nm. Controlling the thickness of the polycrystalline silicon layer to between 10 and 20 nm can not only improve the effective charge transfer efficiency, but also will not affect the overall performance of the first composite layer 201 afterwards. Boron doping is performed by boron hydrogen or boron trifluoride gas, and the temperature range of boron doping is 600℃~900℃, ensuring that boron atoms can be effectively doped into the polysilicon layer. In order to promote the uniform distribution of boron in the polysilicon layer, the doped polysilicon layer needs to be subjected to high-temperature heat treatment. The temperature of the diffusion process is maintained between 800℃~1000℃, and the treatment time is 10 to 60 minutes. In order to ensure efficient charge transfer efficiency and conductive performance, the doping concentration of the second doping layer 2012 is 10 20 cm-3.

[0091] After step S2011 and before step S2012, a first intermediate doping layer may be formed on the fourth doping layer 2022. The step of forming the first intermediate doping layer is the same as step S2011 or the same as step S2012. The conductivity type of the first intermediate doping layer is the same as or opposite to that of the fourth doping layer 2022. The concentration of the first intermediate doping layer is 1019 cm-3.

[0092] S202 , forming a first composite layer 201 on a surface of the second composite layer 202 that is away from the crystalline silicon cell structure 300 .

[0093] S2021, as Figure 4 As shown, the second doping layer 2012 is deposited on the surface of the third doping layer 2021 which is away from the fourth doping layer 2022 .

[0094] Specifically, silane or bisilane gas is used as a deposition source gas, and a polysilicon layer is formed on the surface of the third doping layer 2021 away from the fourth doping layer 2022 by a vapor deposition process. The deposition temperature is 550°C to 650°C, ensuring that the polysilicon layer is evenly covered on the third doping layer 2021. The thickness of the polysilicon layer is 10 to 20 nm. Controlling the thickness of the polysilicon layer to 10 to 20 nm can not only improve the charge transfer efficiency, but also will not affect the overall performance of the first composite layer 201. The conductivity type of the second doping layer 2012 is the same as or opposite to that of the third doping layer. This embodiment is described by taking the conductivity type of the second doping layer and the conductivity type of the third doping layer as an example. Boron doping is performed by boron hydrogen or boron trifluoride gas. The temperature range of boron doping is 600°C to 900°C, ensuring that boron atoms can be effectively doped into the polysilicon layer. In order to promote the uniform distribution of boron in the polysilicon layer, the doped polysilicon layer needs to be subjected to high-temperature heat treatment. The temperature of the diffusion process is maintained at about 800°C to 1000°C, and the processing time is 10 to 60 minutes. To ensure efficient charge transfer efficiency and conductive performance, the doping concentration of the second doping layer 2012 is 10 20 cm-3.

[0095] S2022, such as Figure 5 As shown, a first doping layer 2011 is formed on one side surface of the second doping layer 2012 .

[0096] Specifically, silane or disilane gas is used as a deposition source gas, and a polysilicon layer is formed on the surface of the fourth doped layer 2022 away from the second transmission layer 301 by a vapor deposition process. The deposition temperature is 550°C to 650°C, ensuring that the polysilicon layer is evenly covered on the second doped layer 2012. The thickness of the polysilicon layer is 10 to 20 nm. Controlling the thickness of the polysilicon layer to 10 to 20 nm can not only improve the efficient charge transmission efficiency, but also will not affect the overall performance of the first composite layer 201. The perovskite cell has a first transmission layer 101. In this embodiment, the first transmission layer 101 is used as a hole transmission layer as an example for explanation. The first doped layer 2011 has the same conductivity type as the first transmission layer 101. Boron is doped by boron hydrogen or boron trifluoride gas. The temperature range of boron doping is 600°C to 900°C, ensuring that boron atoms can be effectively doped into the polysilicon layer. In order to promote the uniform distribution of boron in the polysilicon layer, the doped polysilicon layer needs to be subjected to high-temperature heat treatment. The temperature of the diffusion process is maintained at about 800°C to 1000°C, and the processing time is 10 to 60 minutes. To ensure efficient charge transfer efficiency and conductive performance, the doping concentration of the second doping layer 2012 is 10 -18 cm-3.

[0097] After step S2021 and before step S2022, a second intermediate doping layer may be formed on the second doping layer 2012. The step of forming the second intermediate doping layer is the same as step S2021 or the same as step S2022. The conductivity type of the second intermediate doping layer is the same as or opposite to the conductivity type of the second doping layer 2012. The concentration of the second intermediate doping layer is 10 19 cm-3.

[0098] S101, such as Figure 6 As shown, the first transmission layer 101 is formed on a surface of the first doping layer 2011 that is away from the third doping layer 2021 .

[0099] Specifically, the first transport layer 101 may be formed by a vapor deposition process, and the first transport layer 101 may be an electron transport layer or a hole transport layer; the material of the first transport layer 101 is N-type amorphous silicon or P-type amorphous silicon.

[0100] S102, such as Figure 7 As shown, a perovskite layer 102 is formed on a surface of the first transmission layer 101 that is away from the first doping layer 2011 .

[0101] Specifically, cesium iodide, formamidine iodide, phenethylammonium iodide, lead iodide, lead bromide, and dimethylformamide are mixed, stirred sufficiently to completely dissolve, filtered to form a precursor solution, and then a perovskite film is prepared as the perovskite layer 102 by a solution method.

[0102] S103, such as Figure 8 As shown, the third transmission layer 103 is formed on the side of the perovskite layer 102 facing away from the first transmission layer 101 .

[0103] Specifically, the third transmission layer 103 can be formed by a vapor deposition process. The material of the first transmission layer 101 is N-type amorphous silicon or P-type amorphous silicon. When the first transmission layer 101 is a hole transmission layer, the third transmission layer 103 is an electron transmission layer. In this case, the first transmission layer 101 is P-type amorphous silicon, and the third transmission layer 103 is N-type amorphous silicon. When the first transmission layer 101 is an electron transmission layer, the third transmission layer 103 is a hole transmission layer. In this case, the first transmission layer 101 is N-type amorphous silicon, and the third transmission layer 103 is P-type amorphous silicon.

[0104] S104, such as Fig. 9 As shown, a transparent conductive layer 104 is formed on a side of the third transmission layer 103 facing away from the perovskite layer 102 .

[0105] Specifically, the transparent conductive layer 104 may be formed by a magnetron sputtering process, and the material of the transparent conductive layer 104 is indium tin oxide.

[0106] S105, such as Fig.10 As shown, a passivation layer 105 is formed on a side of the transparent conductive layer 104 facing away from the third transmission layer 103 .

[0107] Specifically, a vapor deposition process may be used to form the passivation layer 105 on the side of the transparent conductive layer 104 away from the third transmission layer 103 . The passivation layer 105 is an oxide film, such as silicon dioxide.

[0108] S106 , forming a first electrode 106 on a surface of the passivation layer 105 that is away from the transparent conductive layer 104 .

[0109] Specifically, the first electrode 106 may be formed on the passivation layer 105 by using a vacuum evaporation process, and the first electrode 106 may be a metal or other conductive materials.

[0110] In this embodiment, the preparation method of the stacked battery is simple and easy to implement. In addition, in the first composite layer 201 and the second composite layer 202, the portion with a relatively high conductive impurity doping concentration maximizes the carrier transmission efficiency and reduces the resistance loss, and the portion with a relatively low conductive impurity doping concentration reduces the recombination loss at the interface connection, thereby improving the overall performance of the stacked battery. The first composite layer 201 and the second composite layer 202 can improve the photoelectric conversion efficiency and long-term stability of the stacked battery to ensure efficient and stable operation of the stacked battery.

[0111] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0112] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A laminated battery, characterized in that: It comprises a perovskite cell structure (100), a first composite layer (201), a second composite layer (202), and a crystalline silicon cell structure (300) which are stacked in sequence from a light-receiving surface to a backlight surface; The doping concentration of the conductive impurities in the first composite layer (201) increases gradually along the direction from the perovskite cell structure (100) to the second composite layer (202); The doping concentration of the conductive impurities in the second composite layer (202) decreases gradually along the direction from the first composite layer (201) to the crystalline silicon cell structure (300).

2. The laminated battery according to claim 1, characterized in that: The gradient increase is linear increase or nonlinear increase, and the gradient decrease is linear decrease or nonlinear decrease.

3. The laminated battery according to claim 2, characterized in that: The first composite layer (201) comprises: A first doping layer (2011) located between the perovskite cell structure (100) and the second composite layer (202); A second doping layer (2012), located between the first doping layer (2011) and the second composite layer (202); The doping concentration of the conductive impurities in the second doping layer (2012) is greater than the doping concentration of the conductive impurities in the first doping layer (2011).

4. The laminated battery according to claim 3, characterized in that: The second composite layer (202) comprises: A third doped layer (2021), located between the second doped layer (2012) and the crystalline silicon cell structure (300); A fourth doped layer (2022), located between the third doped layer (2021) and the crystalline silicon cell structure (300); The doping concentration of the conductive impurities in the fourth doping layer (2022) is lower than the doping concentration of the conductive impurities in the third doping layer (2021).

5. The laminated battery according to claim 4, characterized in that: The perovskite cell structure (100) comprises a first transmission layer (101), the first transmission layer (101) being located on a surface of the first doping layer (2011) facing away from the second doping layer (2012), and the first transmission layer (101) and the first doping layer (2011) have the same conductivity type; The crystalline silicon cell comprises a second transmission layer (301), the second transmission layer (301) is located on a surface of the fourth doping layer (2022) which is away from the third doping layer (2021), and the second transmission layer (301) and the fourth doping layer (2022) have the same conductivity type.

6. The laminated battery according to any one of claims 1 to 5, characterized in that: The doping concentration of the conductive impurities in the first composite layer (201) and the second composite layer (202) is less than or equal to 10 2 0cm-3.

7. The laminated battery according to any one of claims 1 to 5, characterized in that: The sum of the thicknesses of the first composite layer (201) and the second composite layer (202) is less than or equal to 120 nm.

8. The laminated battery according to any one of claims 1 to 5, characterized in that: The perovskite cell is capable of at least absorbing light of a first wavelength band and transmitting light of a second wavelength band; The crystalline silicon cell can at least absorb light in the second wavelength band.

9. The laminated battery according to any one of claims 1 to 5, characterized in that: The crystalline silicon cell structure (300) comprises any one of a tunneling oxide layer passivation contact cell, a heterojunction thin layer cell, and an emitter back passivation cell.

10. A method for preparing a laminated battery, characterized in that: include: forming a crystalline silicon cell structure (300); forming a second composite layer (202) on a surface of one side of the crystalline silicon cell structure (300); forming a first composite layer (201) on a surface of the second composite layer (202) that is away from the crystalline silicon cell structure (300); forming a perovskite cell on a surface of the first composite layer (201) facing away from the second composite layer (202); The doping concentration of the conductive impurities in the first composite layer (201) increases gradually along the direction from the perovskite cell to the second composite layer (202); The doping concentration of the conductive impurities in the second composite layer (202) decreases gradually along the direction from the first composite layer (201) to the crystalline silicon cell structure (300).

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