SOC chip and method integrating M1553B interactive interface

Abstract

This invention relates to a System-on-a-Chip (SoC) chip and method integrating an M1553B interactive interface. By integrating the M1553B controller and M1553B transceiver module onto the SoC, the on-chip integrated M1553B transceiver module can be flexibly connected with minimal modifications to the on-chip M1553B controller. This solves the problems of needing an external transceiver or using the SoC's existing general-purpose interfaces to expand the M1553B interface, making M1553B interface applications simpler and more convenient. Furthermore, the added interactive interface allows for flexible expansion of the M1553B transceiver module's functionality, such as configuring data drive capability, swing, and transmission rate, thereby significantly improving the efficiency of M1553B utilization on the SoC chip.

Description

Technical Field

[0001] This invention belongs to the field of SOC chip interface design technology, and relates to an SOC chip and method integrating an M1553B interactive interface. Background Technology

[0002] The M1553B protocol is a time-division multiplexing bus protocol that defines interactive commands. It is primarily used in aerospace and other similar applications. In use, all different devices distributed across large equipment communicate through a single copper cable, typically with an additional redundant backup line. The M1553B has its own unique interactive commands. In existing System-on-Chip (SoC) chips, two common approaches are used to design and implement the M1553B interface: one is to implement only the M1553B controller within the SoC chip but not the M1553B transceiver, requiring an external M1553B transceiver for practical applications; the other is to omit both the M1553B controller and transceiver from the SoC chip, instead directly utilizing the SoC's existing USB / PCI / Ethernet / UART interfaces and integrating the M1553B controller and transceiver module onto these interfaces. However, these traditional approaches suffer from low efficiency. Summary of the Invention

[0003] To address the problems existing in the aforementioned traditional technologies, this invention proposes a SOC chip integrating an M1553B interaction interface and a processing method for the M1553B interaction interface on the SOC chip, which can significantly improve the utilization efficiency of the M1553B on the SOC chip.

[0004] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions:

[0005] On the one hand, a SOC chip integrating an M1553B interactive interface is provided. The SOC chip integrates an M1553B controller, an M1553B transceiver module, and an arbitrator module. The M1553B controller has a bus interface module inside, and the M1553B transceiver module has a bus interface module, a channel module, extended registers, and storage units inside. The bus interface module supports the AHB and APB protocols.

[0006] The arbitrator module is connected to the SOC system bus of the SOC chip, the bus interface module of the M1553B controller, and the bus interface module of the M1553B transceiver module. The channel module of the M1553B transceiver module is compatible with the channels of different M1553B controller IP cores. The bus interface module of the M1553B transceiver module is connected to the extended registers and memory units. The channels of different M1553B controller IP cores include the M1553B controller's channels ATX, ARX, BTX, BRX, and physical layer chip control signal channels.

[0007] The extended registers and storage units are used to configure the M1553B transceiver module's data drive capability, swing, and transmission rate. The M1553B transceiver module's channel module is used for resampling in the clock domain of bus data transmission. The arbiter module supports the APB and AHB protocols on the SOC system bus side, the M1553B controller's bus interface module side, and the M1553B transceiver module's bus interface module side. The arbiter module is used to forward requests on the SOC system bus to the M1553B controller and the M1553B transceiver module.

[0008] On the other hand, a method for processing the M1553B interaction interface on a SOC chip is also provided. This method is applied to an SOC chip that integrates an M1553B interaction interface. The SOC chip integrates an M1553B controller, an M1553B transceiver module, and an arbitrator module. The M1553B controller has a bus interface module inside, and the M1553B transceiver module has a bus interface module, a channel module, extended registers, and storage units inside. The bus interface module supports the AHB and APB protocols.

[0009] The arbitrator module is connected to the SOC system bus of the SOC chip, the bus interface module of the M1553B controller, and the bus interface module of the M1553B transceiver module. The channel module of the M1553B transceiver module is compatible with the channels of different M1553B controller IP cores. The bus interface module of the M1553B transceiver module is connected to the extended registers and memory units. The channels of different M1553B controller IP cores include the M1553B controller's channels ATX, ARX, BTX, BRX, and physical layer chip control signal channels.

[0010] The extended registers and storage units are used to configure the M1553B transceiver module's data drive capability, swing, and transmission rate. The M1553B transceiver module's channel module is used to resample in the clock domain of bus data transmission. The arbiter module supports the APB and AHB protocols on the SOC system bus side, the M1553B controller's bus interface module side, and the M1553B transceiver module's bus interface module side. The arbiter module is used to forward requests on the SOC system bus to the M1553B controller and the M1553B transceiver module.

[0011] The processing method for the M1553B interaction interface on the aforementioned SOC chip includes the following steps:

[0012] After obtaining the information of the defined address segment from the SOC system bus, the arbitrator module decodes and arbitrates specific address bits in the address segment to determine whether the address segment is a controller configuration segment or a transceiver configuration segment.

[0013] If the address range is neither a controller configuration range nor a transceiver configuration range, the address range is reserved and not processed.

[0014] One of the above technical solutions has the following advantages and beneficial effects:

[0015] The aforementioned SOC chip and method integrating the M1553B interface, by integrating the M1553B controller and M1553B transceiver module onto the SOC, allows for flexible access to the on-chip integrated M1553B transceiver module with minimal modifications to the on-chip M1553B controller. This solves the problems of needing an external transceiver or using the SOC's existing general-purpose interfaces to expand the M1553B interface, making M1553B interface applications simpler and more convenient. Furthermore, the added interface allows for flexible expansion of the M1553B transceiver module's functionality, such as configuring data drive capability, swing, and transmission rate, thereby significantly improving the efficiency of M1553B utilization on the SOC chip. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of a system architecture in an SOC chip that only implements the M1553B controller.

[0018] Figure 2 A schematic diagram of a system architecture for mounting an M1553B controller and transceiver integrated module on a general interface for an SOC chip;

[0019] Figure 3 This is a schematic diagram of an improved structure of a SOC chip integrating an M1553B interaction interface in one embodiment.

[0020] Figure 4 This is a schematic diagram of the M1553B processing flow of a SOC chip integrating the M1553B interaction interface in one embodiment.

[0021] Figure 5 This is a flowchart illustrating the processing method of the M1553B interaction interface on a SOC chip in one embodiment. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention.

[0023] It should be noted that, in this document, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will understand that the embodiments described herein can be combined with other embodiments. The term "and / or" as used in the specification and appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0024] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0025] On the one hand, such as Figure 1 As shown, only the M1553B controller is implemented in the SOC chip, without the M1553B transceiver. In practical applications of this M1553B interface, an external M1553B transceiver needs to be connected to the SOC chip (e.g., Figure 1(As shown in the dashed box in the image). In this existing solution, since the M1553B transceiver is not implemented on the SOC chip, the M1553B transceiver needs to be externally mounted on the SOC chip when applying the M1553B interface. Moreover, the interaction between the M1553B controller and the M1553B transceiver is limited to the transmission of data streams after Manchester encoding. This results in the SOC chip lacking internal control over the M1553B transceiver, limiting the further enrichment of the M1553B transceiver's functionality.

[0026] On the other hand, instead of implementing the M1553B controller and M1553B transceiver in the SOC chip, the SOC directly utilizes the universal interfaces already designed and implemented, such as USB / PCI / Ethernet / UART, and directly connects the M1553B controller and transceiver integrated module to these universal interfaces, such as... Figure 2 As shown in the figure. Under this scheme, users need to spend a lot of time debugging to match the SOC chip and the external integrated module, which makes the overall application device development time too long, requires the device's expansion interface, and is not conducive to the development of devices in embedded scenarios, nor is it conducive to device miniaturization.

[0027] In one embodiment, such as Figure 3 As shown, a SOC chip integrating an M1553B interface is provided. The SOC chip integrates an M1553B controller, an M1553B transceiver module, and an arbitrator module. Figure 3 (Referring to the arbitrator in the original text). The M1553B controller has an internal bus interface module. The M1553B transceiver module has an internal bus interface module, channel module, extended registers, and storage units. The bus interface module supports AHB and APB protocols. The arbitrator module connects to the SOC chip's SOC system bus, the M1553B controller's bus interface module, and the M1553B transceiver module's bus interface module. The M1553B transceiver module's channel module is compatible with connecting to channels of different M1553B controller IP cores. The M1553B transceiver module's bus interface module connects to extended registers and storage units. The channels of different M1553B controller IP cores include the M1553B controller's ATX, ARX, BTX, and BRX channels, as well as the physical layer chip control signal channels.

[0028] Extended registers and memory units are used to configure the M1553B transceiver module's data drive capability, swing, and transmission rate. The M1553B transceiver module's channel module is used for resampling in the clock domain of bus data transmission. The arbiter module supports both APB and AHB protocols on the SOC system bus side, the M1553B controller's bus interface module side, and the M1553B transceiver module's bus interface module side. The arbiter module forwards requests on the SOC system bus to the M1553B controller and the M1553B transceiver module.

[0029] It is understood that in this embodiment, the M1553B controller and M1553B transceiver module are integrated into the SOC chip, and a bus interface module, an arbitrator module and a channel module are added to the design of the SOC chip to realize the interaction interface between the SOC system bus in the SOC chip and the integrated M1553B controller and M1553B transceiver module.

[0030] Specifically, in the design of the SOC chip, based on the functional requirements of the existing M1553B controller and M1553B transceiver, both the M1553B controller and M1553B transceiver modules are integrated within the SOC chip. Furthermore, a bus interface module, channel module, extended registers, and memory units are designed and implemented within the M1553B transceiver module. An arbitrator module is added to the SOC system bus to support the flexible simultaneous mounting of both the M1553B controller and M1553B transceiver modules. The design and implementation of the aforementioned functional modules follow existing chip design specifications in this field. The bus interface module implemented within the M1553B transceiver module supports both AHB and APB protocols, allowing for the expansion and configuration of the required registers and memory units within the M1553B transceiver module. This extended registers and memory units can then be accessed through the bus interface module implemented within the M1553B transceiver module.

[0031] The expanded registers and storage units are used to configure the M1553B transceiver module's data drive capability, swing, and transmission rate, making the M1553B interface suitable for a wider range of applications. The channel modules internally designed and implemented in the M1553B transceiver module are compatible with the (data transmission) channels of different M1553B controller IP (Intellectual Property) cores. This allows the channel modules to connect with the M1553B controller's ATX, ARX, BTX, BRX channels, and physical layer chip control signals, and resamples the data transmission signals within the clock domain of the bus data transmission to ensure compatibility with the existing M1553B controller's external interfaces and the reliability of data transmission.

[0032] The arbitrator module is directly connected to the SOC system bus, the bus interface module of the M1553B controller, and the bus interface module of the M1553B transceiver module. The arbitrator module supports the APB and AHB protocols on the SOC system bus side, the bus interface module side of the M1553B controller, and the bus interface module side of the M1553B transceiver module. By decoding and judging specific address bits, it can forward requests (such as configuration information, valid data or instructions transmitted, etc.) on the SOC system bus to the M1553B controller and the M1553B transceiver module according to the user-defined address range, thereby realizing the selection and configuration of the M1553B controller and the M1553B transceiver module.

[0033] The above integrated design does not require modification of the existing M1553B controller design. By simply adding an arbitrator module and a channel module, the functionality of the existing M1553B controller and M1553B transceiver module can be integrated. In the M1553B transceiver module, the added bus interface module, expanded registers, and storage units can support flexible configuration of more functions such as data driving capability, swing, and transmission rate according to the user's actual needs.

[0034] The aforementioned SOC chip integrating the M1553B interface, by integrating the M1553B controller and M1553B transceiver module onto the SOC, allows for flexible access to the on-chip integrated M1553B transceiver module with minimal modifications to the on-chip M1553B controller. This solves the problem of needing an external transceiver or using the SOC's existing general-purpose interface to expand the M1553B interface, making M1553B interface applications simpler and more convenient. Furthermore, the added interface allows for flexible expansion of the M1553B transceiver module's functionality, such as configuring data drive capability, swing, and transmission rate, thereby significantly improving the efficiency of M1553B utilization on the SOC chip.

[0035] It should be noted that the aforementioned address range definitions are freely defined by the SOC chip designers according to project requirements. For example, the internal addressing range of a certain SOC chip is 0x00000000~0xffffffff, and addresses 0x2000000~0x20003fff can be assigned to these registers and RAM. The specific address bit refers to the criterion used by the arbiter module to forward requests, that is, a certain bit or several bits in the middle of the address used when the registers and RAM within the module are accessed by other components within the chip (such as the processor core). The decoding method uses demux (reverse data selector) and mux (data selector) to route data. The demux has one set of data inputs, two sets of data outputs, and one set of criterion inputs; the mux has one set of data outputs, two sets of data inputs, and one set of criterion inputs.

[0036] In this embodiment, one set of the two data outputs of the demux is connected to the input of the bus interface module of the M1553B controller, and the other set of outputs is connected to the input of the bus interface module of the M1553B transceiver module. The data input of the demux is connected to the output signal of the SOC system bus. Similarly, one set of the two data inputs of the mux is connected to the output of the bus interface module of the M1553B controller, and the other set of inputs is connected to the output of the bus interface module of the M1553B transceiver module. The data input of the mux is connected to the SOC system bus as an input signal. The demux and mux are connected to the same criterion input.

[0037] Assuming the user defines the address range for the M1553B controller as 0x20000000~0x20001fff (which can be called the controller configuration range), and the address range for the M1553B transceiver module as 0x20002000~0x20003fff (which can be called the transceiver configuration range), then the bit that distinguishes the two address ranges is bit number 3 (bits 0 to 7 from right to left). That is, when a request should be sent to the M1553B controller, bit number 3 should be 0 or 1; when a request should be sent to the M1553B transceiver module, bit number 3 should be 1. The value should be 2 or 3; bit 3 can distinguish between the two address segments, thus serving as a criterion input (this bit 3 can be used as a specific address bit). Therefore, when the data in bit 3 of the user-defined address segment is 0 or 1, the arbiter module determines that the demux is connected to the M1553B controller and the mux is also connected to the M1553B controller; when the data in bit 3 of the user-defined address segment is 2 or 3, the arbiter module determines that the demux is connected to the M1553B transceiver module and the mux is also connected to the M1553B transceiver module, thereby achieving the decoding purpose. The aforementioned decoding function can also be implemented similarly using Verilog code.

[0038] In one embodiment, after the arbitrator module obtains the information of the defined address segment from the SOC system bus, it decodes and arbitrates specific address bits in the address segment to determine whether the address segment is a controller configuration segment or a transceiver configuration segment. If it is neither a controller configuration segment nor a transceiver configuration segment, the address segment is retained and not processed.

[0039] Understandable, such as Figure 4 As shown, in practical applications, the SOC chip with the integrated M1553B interface can allow the user to define an address segment within the SOC chip. This address segment can include configuration information that needs to be configured for the M1553B controller or M1553B transceiver module, as well as a specific address bit. After obtaining the address segment information from the SOC system bus, the arbitrator module decodes and arbitrates the specific address bit to determine whether the user-defined address segment is a controller configuration segment or a transceiver configuration segment. If it is neither of these two configuration segments, the address segment is retained and not processed.

[0040] In one embodiment, if the address segment is determined to be a controller configuration segment, the arbiter module configures the internal registers and controller message stack of the M1553B controller through the bus interface module of the M1553B controller according to the configuration information of the address segment. Simultaneously, the arbiter module configures the internal registers and transceiver message stack of the M1553B transceiver module through the bus interface module of the M1553B transceiver module according to the configuration information of the address segment. After configuration, the M1553B controller initiates transmission, performing Manchester encoding on the data from the SOC system bus and transmitting it to the channel module of the M1553B transceiver module. Upon detecting a valid transmission from the channel module, the M1553B transceiver module performs appropriate level conversion on the data and transmits it to the outside of the SOC chip through the external channel.

[0041] Understandable, such as Figure 4As shown, if the user-defined address segment is determined to be the controller configuration segment, the arbitrator module configures the registers inside the M1553B controller and the controller message stack (RAM storage) inside the M1553B controller through the bus interface module of the M1553B controller according to the configuration information of the address segment, so that the M1553B controller enters the working preparation completed state. At the same time, the arbitrator module configures the registers inside the M1553B transceiver module and the transceiver message stack (RAM storage) inside the M1553B transceiver module through the bus interface module of the M1553B transceiver module according to the configuration information of the address segment, so that the M1553B transceiver module enters the working preparation completed state. After configuration, the M1553B controller starts transmission, performs Manchester encoding on the data from the SOC system bus, and transmits it to the channel module of the M1553B transceiver module. The M1553B transceiver module determines that there is a valid transmission from the channel module, performs the corresponding level conversion on the data, and then transmits it to the outside of the SOC chip through the external channel (such as channel A and / or channel B).

[0042] In one embodiment, if the address segment is determined to be a transceiver configuration segment, the arbiter module configures the internal registers and transceiver message stack of the M1553B transceiver module through the bus interface module of the M1553B transceiver module according to the configuration information of the address segment. Simultaneously, the arbiter module configures the internal registers and controller message stack of the M1553B controller through the bus interface module of the M1553B controller according to the configuration information of the address segment. After configuration, the M1553B transceiver module determines whether there is a valid transmission from the external channel. If a valid transmission exists, the M1553B transceiver module performs appropriate level conversion on the data received from the external channel and sends it to the M1553B controller for processing through the channel module. The M1553B controller performs Manchester decoding on the received data and sends it to the SOC system bus.

[0043] Understandable, such as Figure 4As shown, if the user-defined address segment is determined to be the transceiver configuration segment, the arbiter module configures the internal registers of the M1553B transceiver module and the internal transceiver message stack (RAM storage) of the M1553B transceiver module through the bus interface module of the M1553B transceiver module according to the configuration information of the address segment, so that the M1553B transceiver module enters the working preparation completed state. At the same time, the arbiter module configures the internal registers of the M1553B controller and the internal controller message stack (RAM storage) of the M1553B controller through the bus interface module of the M1553B controller according to the configuration information of the address segment, so that the M1553B controller enters the working preparation completed state. After configuration, the M1553B transceiver module determines whether there is a valid transmission from the external channel (such as channel A and / or channel B). If there is a valid transmission, the M1553B transceiver module performs the corresponding level conversion on the data received by the channel and sends it to the M1553B controller for processing through the channel module. The M1553B controller can perform Manchester decoding on the received data and send the data to the SOC system bus.

[0044] In one embodiment, a method for processing the M1553B interaction interface on a SOC chip is also provided. This method is applied to an SOC chip that integrates an M1553B interaction interface. The SOC chip integrates an M1553B controller, an M1553B transceiver module, and an arbitrator module. The M1553B controller has an internal bus interface module, and the M1553B transceiver module has an internal bus interface module, a channel module, extended registers, and storage units. The bus interface module supports the AHB and APB protocols.

[0045] The arbitrator module is connected to the SOC system bus of the SOC chip, the bus interface module of the M1553B controller, and the bus interface module of the M1553B transceiver module. The channel module of the M1553B transceiver module is compatible with the channels of different M1553B controller IP cores. The bus interface module of the M1553B transceiver module is connected to the extended registers and memory units. The channels of different M1553B controller IP cores include the M1553B controller's channels ATX, ARX, BTX, BRX, and physical layer chip control signal channels.

[0046] The extended registers and storage units are used to configure the M1553B transceiver module's data drive capability, swing, and transmission rate. The M1553B transceiver module's channel module is used to resample in the clock domain of bus data transmission. The arbiter module supports the APB and AHB protocols on the SOC system bus side, the M1553B controller's bus interface module side, and the M1553B transceiver module's bus interface module side. The arbiter module is used to forward requests on the SOC system bus to the M1553B controller and the M1553B transceiver module.

[0047] Among them, such as Figure 5 As shown, the processing method of the M1553B interaction interface on this SOC chip can include at least the following processing steps S10 and S12:

[0048] S10, after the arbitrator module obtains the information of the defined address segment from the SOC system bus, it decodes and arbitrates specific address bits in the address segment to determine whether the address segment is the controller configuration segment or the transceiver configuration segment.

[0049] S12, if the address segment is neither a controller configuration segment nor a transceiver configuration segment, then the address segment is reserved and not processed.

[0050] The aforementioned method for handling the M1553B interface on the SOC chip integrates the M1553B controller and M1553B transceiver module onto the SOC. This design allows for flexible access to the on-chip integrated M1553B transceiver module with minimal modifications to the on-chip M1553B controller. This solves the problems of needing an external transceiver or using the SOC's existing general-purpose interfaces to expand the M1553B interface, making its application simpler and more convenient. Furthermore, the added interface allows for flexible expansion of the M1553B transceiver module's functionality, such as configuring data drive capability, swing, and transmission rate, thereby significantly improving the efficiency of M1553B utilization on the SOC chip.

[0051] In one embodiment, the processing method for the M1553B interaction interface on the SOC chip described above may further include the following processing steps:

[0052] If the address segment is determined to be a controller configuration segment, the arbiter module configures the registers and controller message stack of the M1553B controller through the bus interface module of the M1553B controller according to the configuration information of the address segment. At the same time, the arbiter module configures the registers and transceiver message stack of the M1553B transceiver module through the bus interface module of the M1553B transceiver module according to the configuration information of the address segment.

[0053] After configuration, the M1553B controller starts transmission, performs Manchester encoding on the data from the SOC system bus, and then transmits it to the channel module of the M1553B transceiver module.

[0054] After the M1553B transceiver module detects a valid transmission from the channel module, it performs the corresponding level conversion on the data and transmits it to the outside of the SOC chip through the external channel.

[0055] In one embodiment, the processing method for the M1553B interaction interface on the SOC chip described above may further include the following processing steps:

[0056] If the address segment is determined to be a transceiver configuration segment, the arbiter module configures the internal registers and transceiver message stack of the M1553B transceiver module through the bus interface module of the M1553B transceiver module according to the configuration information of the address segment; at the same time, the arbiter module configures the internal registers and controller message stack of the M1553B controller through the bus interface module of the M1553B controller according to the configuration information of the address segment.

[0057] After configuration, the M1553B transceiver module determines whether there is a valid transmission from the external channel;

[0058] If a valid transmission exists, the M1553B transceiver module performs the corresponding level conversion on the data received from the external channel and then sends it to the M1553B controller through the channel module.

[0059] The M1553B controller performs Manchester decoding on the received data and then sends it to the SOC system bus.

[0060] For a detailed explanation and limitation of the processing method of the M1553B interaction interface on the above-mentioned SOC chip, please refer to the corresponding limitation of the SOC chip integrating the M1553B interaction interface mentioned above, which will not be repeated here.

[0061] It should be understood that although Figure 5The steps are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order in which these steps are executed; they can be performed in other orders. Figure 5 At least some of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0062] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided by this invention can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), memory bus DRAM (RDRAM), and interface DRAM (DRDRAM), etc.

[0063] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0064] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of protection of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and all such modifications and improvements fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. A SOC chip integrating an M1553B interactive interface, characterized in that, The SOC chip integrates an M1553B controller, an M1553B transceiver module, and an arbitrator module. The M1553B controller has an internal bus interface module, and the M1553B transceiver module has an internal bus interface module, a channel module, extended registers, and storage units. The bus interface module supports the AHB and APB protocols. The arbiter module is connected to the SOC system bus of the SOC chip, the bus interface module of the M1553B controller, and the bus interface module of the M1553B transceiver module. The channel module of the M1553B transceiver module is compatible with the channels of different M1553B controller IP cores. The bus interface module of the M1553B transceiver module is connected to extended registers and memory units. The channels of different M1553B controller IP cores include the M1553B controller's channels ATX, ARX, BTX, BRX, and physical layer chip control signal channels. The extended registers and storage units are used to configure the M1553B transceiver module's data drive capability, swing, and transmission rate. The channel module of the M1553B transceiver module is used to resample in the clock domain of bus data transmission. The arbiter module supports the APB and AHB protocols on the SOC system bus side, the bus interface module side of the M1553B controller, and the bus interface module side of the M1553B transceiver module. The arbiter module is used to forward requests on the SOC system bus to the M1553B controller and the M1553B transceiver module. After obtaining the information of the defined address segment from the SOC system bus, the arbitrator module decodes and arbitrates specific address bits in the address segment to determine whether the address segment is a controller configuration segment or a transceiver configuration segment. If it is neither a controller configuration segment nor a transceiver configuration segment, the address segment is retained and not processed.

2. The SOC chip integrating the M1553B interactive interface according to claim 1, characterized in that, If the address segment is determined to be a controller configuration segment, the arbiter module configures the registers inside the M1553B controller and the controller message stack inside the M1553B controller through the bus interface module of the M1553B controller according to the configuration information of the address segment. At the same time, the arbiter module configures the registers inside the M1553B transceiver module and the transceiver message stack inside the M1553B transceiver module through the bus interface module of the M1553B transceiver module according to the configuration information of the address segment. After configuration, the M1553B controller starts transmission, performs Manchester encoding on the data from the SOC system bus, and transmits it to the channel module of the M1553B transceiver module. After the M1553B transceiver module determines that there is a valid transmission from the channel module, it performs the corresponding level conversion on the data and transmits it to the outside of the SOC chip through the external channel.

3. The SOC chip integrating the M1553B interactive interface according to claim 1, characterized in that, If the address segment is determined to be a transceiver configuration segment, the arbiter module configures the registers and transceiver message stack inside the M1553B transceiver module through the bus interface module of the M1553B transceiver module according to the configuration information of the address segment. At the same time, the arbiter module configures the registers and controller message stack inside the M1553B controller through the bus interface module of the M1553B controller according to the configuration information of the address segment. After configuration, the M1553B transceiver module determines whether there is a valid transmission from the external channel. If there is a valid transmission, the M1553B transceiver module performs the corresponding level conversion on the data received from the external channel and sends it to the M1553B controller for processing through the channel module. The M1553B controller performs Manchester decoding on the received data and sends it to the SOC system bus.

4. A method for processing the M1553B interactive interface on a SOC chip, characterized in that, This invention relates to a System-on-a-Chip (SoC) chip integrating an M1553B interactive interface. The SoC chip integrates an M1553B controller, an M1553B transceiver module, and an arbitrator module. The M1553B controller internally includes a bus interface module, and the M1553B transceiver module internally includes a bus interface module, a channel module, extended registers, and storage units. The bus interface module supports both AHB and APB protocols. The arbiter module is connected to the SOC system bus of the SOC chip, the bus interface module of the M1553B controller, and the bus interface module of the M1553B transceiver module. The channel module of the M1553B transceiver module is compatible with the channels of different M1553B controller IP cores. The bus interface module of the M1553B transceiver module is connected to extended registers and memory units. The channels of different M1553B controller IP cores include the M1553B controller's channels ATX, ARX, BTX, BRX, and physical layer chip control signal channels. The extended registers and storage units are used to configure the M1553B transceiver module's data drive capability, swing, and transmission rate. The channel module of the M1553B transceiver module is used to resample in the clock domain of bus data transmission. The arbiter module supports the APB and AHB protocols on the SOC system bus side, the bus interface module side of the M1553B controller, and the bus interface module side of the M1553B transceiver module. The arbiter module is used to forward requests on the SOC system bus to the M1553B controller and the M1553B transceiver module. The processing method for the M1553B interaction interface on the SOC chip includes the following steps: After obtaining the information of the defined address segment from the SOC system bus, the arbitrator module decodes and arbitrates specific address bits in the address segment to determine whether the address segment is a controller configuration segment or a transceiver configuration segment. If the address segment is neither a controller configuration segment nor a transceiver configuration segment, then the address segment is retained and no processing is performed.

5. The processing method for the M1553B interactive interface on a SOC chip according to claim 4, characterized in that, It also includes the following steps: If the address segment is determined to be a controller configuration segment, the arbiter module configures the registers and controller message stack of the M1553B controller through the bus interface module of the M1553B controller according to the configuration information of the address segment; simultaneously, the arbiter module configures the registers and transceiver message stack of the M1553B transceiver module through the bus interface module of the M1553B transceiver module according to the configuration information of the address segment. After configuration, the M1553B controller starts transmission, performs Manchester encoding on the data from the SOC system bus, and then transmits it to the channel module of the M1553B transceiver module. After the M1553B transceiver module detects a valid transmission from the channel module, it performs the corresponding level conversion on the data and transmits it to the outside of the SOC chip through the external channel.

6. The processing method for the M1553B interactive interface on a SOC chip according to claim 4, characterized in that, It also includes the following steps: If the address segment is determined to be a transceiver configuration segment, the arbiter module configures the registers and transceiver message stack of the M1553B transceiver module through the bus interface module of the M1553B transceiver module according to the configuration information of the address segment. At the same time, the arbiter module configures the registers and controller message stack of the M1553B controller through the bus interface module of the M1553B controller according to the configuration information of the address segment. After configuration, the M1553B transceiver module determines whether there is a valid transmission from the external channel; If a valid transmission exists, the M1553B transceiver module performs corresponding level conversion on the data received by the external channel and then sends it to the M1553B controller through the channel module. The M1553B controller performs Manchester decoding on the received data and then sends it to the SOC system bus.

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