Package carrier plate manufacturing method and package carrier plate

Abstract

The invention discloses a manufacturing method of a package carrier and the package carrier, and the method comprises the steps: placing dielectric layers at the two sides of a core plate, and carrying out the pressing and solidification at a preset temperature and pressure intensity, and forming a layered structure; holes are formed in the upper surface and the lower surface of the layered structure respectively; metal layers with preset thicknesses are deposited on the upper surface and the lower surface of the layered structure respectively, and the hole wall metal layer is in contact communication with the core plate exposed out of the hole; coating photoresist on the surface of the plane metal layer, and performing exposure and development to form an outer layer circuit pattern; respectively plating surface metal layers with different preset thicknesses on the outer layer circuit pattern and the hole of the layered structure; and respectively performing film stripping on the upper surface and the lower surface of the layered structure, and removing the metal layer which does not belong to the areas of the outer layer circuit patterns and the holes to form the package carrier. According to the invention, the roughness of the dielectric layer of the packaging substrate can be reduced, the manufacturing cost of the packaging substrate is reduced, and pollution in the manufacturing process is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of printed circuit boards, and in particular to a method for manufacturing a packaging carrier and a packaging carrier. Background Art

[0002] As global electronic products are gradually moving towards lightweight and miniaturization, chip manufacturing capabilities are gradually improving, and the minimum line width node is gradually shrinking. In order to achieve more complex signal transmission, the size of the packaging substrate is required to be the same or similar to the size of the bare chip, and the line width and line spacing of the substrate is more refined; at the same time, with the development of AI technology, the demand for high computing power and high-performance storage is increasing. The production of substrates for high-frequency and high-bandwidth signal transmission for high-speed DDR5 and even DDR6 storage has also become an urgent need of the current industry.

[0003] At present, the production process of conventional chip-level packaging substrates is as follows: after the core board is made, a series of processes such as copper cladding and laminating semi-cured sheets, copper reduction, drilling, degumming and copper deposition, graphic exposure, electroplating and film stripping and flash etching are carried out. However, the above process has the following problems when making fine circuits: the ultra-thin copper foil with a thickness of 3μm used for fine circuits is about 3 times more expensive than the conventional 12μm copper foil; in the copper reduction process, the copper thickness to be etched is usually more than 10μm, and a large amount of copper-containing wastewater will be generated in this process, which is easy to cause pollution; after copper cladding and lamination, the roughness Ra of the dielectric layer under the copper surface will be very high, about Ra0.3μm or more, Rz3μm or more, and the transmission loss of high-frequency and high-speed signals is relatively high. Based on the defects of the existing technology, there is an urgent need for a method for making a packaging substrate with lower cost, more environmental protection and lower surface roughness. Summary of the invention

[0004] The main purpose of the present invention is to provide a method for manufacturing a packaging carrier and a packaging carrier, so as to reduce the manufacturing cost and surface roughness of the packaging carrier.

[0005] The technical solution adopted by the present invention is: a method for manufacturing a packaging carrier, including: placing a dielectric layer on both sides of a core board, pressing and curing at a preset temperature and pressure to form a layered structure consisting of a dielectric layer, a core board, and a dielectric layer.

[0006] Holes are respectively opened on the upper and lower surfaces of the layered structure, and the holes penetrate the dielectric layer to expose the core plate; further, after the drilling is completed, the hole wall residue is cleaned, including using plasma to remove the hole wall residue and using chemicals to etch the protruding glass fiber to less than a preset length.

[0007] Metal layers of preset thickness are deposited on the upper and lower surfaces of the layered structure respectively, and the metal layers include a hole wall metal layer on the inner wall of the hole and a planar metal layer located in the non-hole area of ​​the dielectric layer. The hole wall metal layer is in contact with and connected to the core plate exposed in the hole.

[0008] A photoresist is coated on the surface of the planar metal layer, and is exposed and developed to form an outer layer circuit pattern; further, different types of photoresists are selected, and the line width and line spacing of the formed outer layer circuits are different; and laser direct imaging technology is selected for exposure.

[0009] The outer circuit patterns and holes of the layered structure are respectively plated with outer metal layers of different preset thicknesses, namely, the outer circuit pattern outer metal layer and the hole outer metal layer.

[0010] The upper and lower surfaces of the layered structure are stripped respectively, and the metal layer in the area not belonging to the outer layer circuit pattern and the hole is removed to form a package carrier. Furthermore, the operation process of forming the package carrier includes solder mask ink and cutting and forming.

[0011] According to the above technical solution, the dielectric layer includes a prepreg layer and a release film layer; during lamination, the prepreg layer contacts the core board; after drilling is completed, the release film layer is removed.

[0012] According to the above technical solution, the release film is made of polyimide or polytetrafluoroethylene, and the prepreg comprises resin and glass fiber.

[0013] According to the above technical solution, the method for depositing the metal layer is an ion implantation vacuum coating process.

[0014] According to the above technical solution, the metal of the metal layer is nickel or copper.

[0015] According to the above technical solution, the position of the hole enables the bottom of the hole to communicate with the metal of the core plate.

[0016] According to the above technical solution, the photoresist is a dry film or a liquid photoresist, and the thickness required for the dry film or the liquid photoresist when in use is preset respectively.

[0017] According to the above technical scheme, the outer surface metal layer with different preset thicknesses is plated, specifically by hole-filling electroplating, wherein the thickness of the outer surface metal layer on the outer layer circuit pattern is less than or equal to the thickness of the photoresist, and the outer surface metal layer in the hole is in the same plane as the outer surface metal layer on the outer layer circuit pattern after filling the hole.

[0018] According to the above technical solution, the film stripping method is the MSAP film stripping process, and the method for removing the surface metal is etching. The etching amount of the surface metal is preset before etching.

[0019] Another aspect of the present invention provides a packaging carrier, which is manufactured by adopting the above-mentioned method for manufacturing the packaging carrier.

[0020] The beneficial effects of the present invention are as follows: the present invention provides a method for manufacturing a packaging carrier and a packaging carrier. The method of the present invention first combines a prepreg and a release film to press and solidify a core board to form a layered structure, and then sequentially performs drilling, metal layer deposition, adhesive attachment, exposure, development, metal layer plating, film stripping, metal removal and other processes on the layered structure, and finally processes the obtained board into a carrier. Compared with the prior art, which requires the steps of prepreg prepreg, vacuum pressing, and re-pressing after stripping the glass fiber cloth during the pressing process, the present method uses a method of direct hot pressing of a prepreg covered with a release film, and the operation steps are simpler.

[0021] Furthermore, compared with the high-cost ultra-thin copper foil used in the prior art to make fine circuits, the method for making a package carrier of the present invention uses an ion implantation vacuum coating process to deposit a metal layer, so that the thickness of the deposited metal layer is lower, thereby forming a finer circuit on the surface of the carrier, and the manufacturing cost is lower. At the same time, the thinner metal layer requires less etching in the subsequent process, and the manufacturing process is more environmentally friendly.

[0022] Furthermore, in the method for manufacturing the packaging carrier of the present invention, a release film made of polyimide or polytetrafluoroethylene is arranged outside the semi-cured sheet during lamination, so that the dielectric layer of the present method has lower roughness than the dielectric layer used in conventional copper cladding lamination, which is beneficial to reducing the transmission loss of high-frequency and high-speed signals, and the ion implantation vacuum coating process adopted in the present method ensures the reliability of the bonding force under low roughness.

[0023] Furthermore, the pressing process of the package carrier of the present invention is copper-free pressing, which reduces the pollution to the environment caused by the generation of copper-containing wastewater.

[0024] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0026] Figure 1 is a flow chart of a method for manufacturing a packaging carrier according to an embodiment of the present invention;

[0027] Figure 2 It is a schematic diagram of laminating a front core board, a prepreg and a release film according to an embodiment of the present invention;

[0028] Figure 3is a schematic diagram of a layered structure formed by a core board, a prepreg, and a release film after lamination according to an embodiment of the present invention;

[0029] Figure 4 is a schematic diagram of a layered structure after a drilling operation according to an embodiment of the present invention;

[0030] Figure 5 is a schematic diagram of a layered structure after the release film is torn off and the hole wall is cleaned according to an embodiment of the present invention;

[0031] Figure 6 is a schematic diagram of a layered structure after a metal layer is deposited by an ion implantation vacuum coating process according to an embodiment of the present invention;

[0032] Figure 7 is a schematic diagram of a layered structure after photoresist is attached and pattern exposure and development are performed in one embodiment of the present invention;

[0033] Figure 8 is a schematic diagram of a layered structure after electroplating a metal layer according to an embodiment of the present invention;

[0034] Fig. 9 It is a schematic diagram of a layered structure after removing the photoresist and etching the metal according to an embodiment of the present invention.

[0035] Figure numerals: 1, core board; 2, semi-cured sheet layer; 3, release film layer; 401, hole wall deposited metal layer; 402, plane deposited metal layer; 5, photoresist; 601, outer layer circuit pattern surface metal layer; 602, hole surface metal layer. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0037] It should be noted that the illustrations provided in the embodiments of the present invention are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout type may also be more complicated.

[0038] In the present invention, it is also necessary to explain that, if the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, if the terms "first" and "second" appear, they are only used for description and distinction purposes, and cannot be understood as indicating or implying relative importance.

[0039] Example 1

[0040] This embodiment provides a method for manufacturing a packaging substrate, the process is as follows Figure 1 As shown, including:

[0041] S1. Place dielectric layers on both sides of the core board 1, press and solidify them at a preset temperature and pressure to form a layered structure consisting of the dielectric layer, the core board 1, and the dielectric layer.

[0042] Specifically, the dielectric layer includes a prepreg layer 2 and a release film layer 3. During lamination, the prepreg layer 2 contacts the core board. The prepreg layer 2 includes glass fiber and resin, and the release film layer 3 is made of polyimide or polytetrafluoroethylene.

[0043] During lamination, a release film layer 3 is also arranged outside the prepreg layer 2. Under the preset lamination curing pressure and temperature conditions, a lamination steel plate is used for lamination. After lamination, the release film layer 3 and the prepreg layer 2 form a dielectric layer. The roughness Ra of the dielectric layer is in the range of 0.04-0.07μm, and the Rz is in the range of 0.4-0.8μm. The structure of the core board 1, the prepreg layer 2 and the release film layer 3 before lamination is as follows: Figure 2 As shown, the structure of the core board 1, the prepreg layer 2 and the release film layer 3 after lamination is as follows Figure 3 shown.

[0044] S2. Drill holes on the upper and lower surfaces of the layered structure respectively, wherein the holes penetrate the dielectric layer to expose the core plate 1, and clean the residues on the hole walls.

[0045] Specifically, the hole is located so that the bottom of the hole is connected to the metal of the core plate. Figure 4 As shown, in this embodiment, the openings on the upper and lower surfaces of the layered structure are symmetrical structures. According to the actual requirements of the carrier board, the openings on the upper and lower surfaces of the layered structure may also be asymmetrical structures.

[0046] The drilling method is laser drilling. After the drilling is completed, the residue on the hole wall is removed by plasma degumming, and then the protruding glass fiber caused by the drilling is etched to less than 5μm by using a chemical solution. The layered structure after the release film layer 3 is torn off and the hole wall is cleaned is as shown in FIG. Figure 5 shown.

[0047] S3, depositing metal layers of preset thickness on the upper and lower surfaces of the layered structure respectively, wherein the metal layers include a hole wall deposited metal layer on the inner wall of the hole and a plane deposited metal layer located in the non-hole area of ​​the dielectric layer, the hole wall metal layer is in contact with and connected to the core plate exposed in the hole, and the layered structure after the metal layer is deposited is as follows Figure 6 shown.

[0048] Specifically, after drilling a hole in the dielectric layer on the outside of the board, an ion implantation vacuum coating process is used to deposit a layer of metal on the surface of the board. The thickness of the metal layer ranges from 0.1 to 0.5 μm and can be set according to actual needs. The type of metal can be copper or nickel. In this embodiment, copper is selected.

[0049] S4, coating the surface of the planar metal layer with photoresist, and performing exposure and development to form an outer layer circuit pattern. The completed layered structure is as follows: Figure 7 shown.

[0050] Specifically, the photoresist 5 can be selected from dry film RD3015, and the thickness of the attached dry film is 15 μm. The dry film is attached to the surface of the planar metal layer of the layered structure, and exposed using laser direct imaging technology. After development, a pattern circuit with a line width / line spacing less than 4 / 4 μm is formed.

[0051] S5, the outer circuit pattern and the hole of the layered structure are respectively plated with outer metal layers of different preset thicknesses, namely, the outer circuit pattern outer metal layer 601 and the hole outer metal layer 602. The completed layered structure is as follows Figure 8 shown.

[0052] Specifically, the electroplating method is hole-filling electroplating, the copper thickness is controlled at 1.3 μm-10 μm, and the electroplating thickness is set according to the dry film thickness, that is, the electroplating thickness needs to be less than or equal to the dry film thickness.

[0053] S6, respectively stripping the upper and lower surfaces of the layered structure, and removing the metal layer in the area not belonging to the outer layer circuit pattern and the hole, to form a packaging carrier.

[0054] Specifically, the dry film is removed by using the MSAP film stripping process, and then the metal layer outside the graphic area and the hole area in the board after the film stripping is removed by micro-etching. The etching amount is controlled at 0.2μm-1.5μm to form the desired design circuit. After completing the micro-etching, the layered structure of the designed circuit is formed. Fig. 9 shown.

[0055] The layered structure is then coated with solder mask and cut to form a carrier board.

[0056] By implementing the above operations, the chip packaging substrate with fine lines with a line width / line spacing of less than 4 / 4 μm is manufactured. The obtained packaging substrate is subjected to a thermal stress test. The substrate does not delaminate or explode under the test conditions of tinning temperature of 288°C, time of 10s, and number of times 10. The experimental results prove that the packaging substrate manufactured by the manufacturing method in this embodiment has good stability and structural strength.

[0057] Example 2

[0058] This embodiment provides another method for manufacturing a packaging carrier. In this embodiment, the photoresist 5 is selected from liquid photoresist AZ703, and the coating thickness is controlled to be 1.5 μm-4 μm.

[0059] Compared with Example 1, most of the operation processes in this embodiment are the same as those in Example 1, and the difference from Example 1 is that:

[0060] 1. In this embodiment, the specific operation in step S4 of embodiment 1 is changed to coating liquid photoresist on the above-mentioned board, exposing it using laser direct imaging technology, and forming a graphic circuit with a line width / line spacing less than 2 / 2 μm after development.

[0061] 2. This embodiment changes the specific operation of step S5 of embodiment 1 to setting the electroplating thickness according to the thickness of the liquid photoresist, and the electroplating thickness is less than or equal to the thickness of the liquid photoresist.

[0062] 3. In this embodiment, the specific operation of step S6 of embodiment 1 is changed to use the MSAP film stripping process to strip the liquid photoresist.

[0063] In this embodiment, liquid photoresist is selected as the photoresist 5, and a series of operations are performed to complete the production of a chip packaging carrier with fine circuits with a line width / line spacing less than 2 / 2 μm. Compared with Example 1, the size of the graphic circuit that can be achieved is finer. The obtained packaging carrier is subjected to a thermal stress test. The carrier does not show delamination and explosion under the test conditions of tin immersion temperature of 288°C, time of 10s, and number of times 10. The experimental results prove that the packaging carrier produced by the production method in this embodiment also has good stability and structural strength.

[0064] Example 3

[0065] This embodiment provides a packaging carrier, characterized in that the packaging carrier is manufactured by adopting the packaging carrier manufacturing method described in embodiment 1 or 2.

[0066] Example 4

[0067] This embodiment provides a chip structure, which includes the package carrier described in Embodiment 3. Since the circuits of the package carrier in this embodiment are finer and the dielectric layer has lower roughness, the chip structure generates lower transmission loss when transmitting high-frequency and high-bandwidth signals.

[0068] In summary, the present invention provides a method for manufacturing a package carrier and a package carrier, wherein the method simplifies the relatively complicated copper cladding pressing method in the prior art by adopting a release film and an ion implantation vacuum coating process. The present invention not only reduces the roughness of the dielectric layer and thus reduces the loss during high-frequency signal transmission, but also reduces the cost of manufacturing the package carrier and the pollution during the manufacturing process.

[0069] It should be pointed out that, according to the needs of implementation, the various steps / components described in this application can be split into more steps / components, and two or more steps / components or partial operations of steps / components can be combined into new steps / components to achieve the purpose of the present invention.

[0070] The order of execution of each step in the above embodiment does not mean the order of execution. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application.

[0071] It should be understood that those skilled in the art can make improvements or changes based on the above description, and all these improvements and changes should fall within the scope of protection of the appended claims of the present invention.

Claims

1. A method for manufacturing a packaging carrier, characterized in that: include: A dielectric layer is placed on both sides of the core plate, and pressed and cured at a preset temperature and pressure to form a layered structure consisting of a dielectric layer, a core plate, and a dielectric layer; Open holes on the upper and lower surfaces of the layered structure respectively, wherein the holes penetrate the dielectric layer to expose the core plate; Depositing metal layers of preset thickness on the upper and lower surfaces of the layered structure respectively, the metal layers include a hole wall metal layer on the inner wall of the hole, and a planar metal layer located in the non-hole area of ​​the dielectric layer, the hole wall metal layer is in contact with and connected to the core plate exposed in the hole; Coating photoresist on the surface of the planar metal layer, and performing exposure and development to form an outer layer circuit pattern; The outer circuit patterns and holes of the layered structure are respectively plated with outer metal layers of different preset thicknesses; The upper and lower surfaces of the layered structure are stripped respectively, and the metal layer in the area not belonging to the outer layer circuit pattern and the hole is removed to form a packaging carrier.

2. The method for manufacturing a packaging carrier according to claim 1, characterized in that: The medium layer includes a prepreg layer and a release film layer; during lamination, the prepreg layer contacts the core board; after the opening is completed, the release film layer is removed.

3. The method for manufacturing a packaging carrier according to claim 2, characterized in that: The release film layer is made of polyimide or polytetrafluoroethylene, and the prepreg layer comprises resin and glass fiber.

4. The method for manufacturing a packaging carrier according to claim 1, characterized in that: The method for depositing the metal layer is an ion implantation vacuum coating process.

5. The method for manufacturing a packaging carrier according to claim 1, characterized in that: The metal of the metal layer is nickel or copper.

6. The method for manufacturing a packaging carrier according to claim 1, characterized in that: The openings are located so that the bottoms of the holes are in communication with the metal of the core plate.

7. The method for manufacturing a packaging carrier according to claim 1, characterized in that: The photoresist is a dry film or a liquid photoresist, and the thickness required for the dry film or the liquid photoresist when in use is preset respectively.

8. The method for manufacturing a packaging carrier according to claim 7, characterized in that: The coating of the outer metal layer with different preset thicknesses is specifically achieved by hole-filling electroplating; wherein the thickness of the outer surface metal layer on the outer layer circuit pattern is less than or equal to the thickness of the photoresist, and the outer surface metal layer in the hole is on the same plane as the outer surface metal layer on the outer layer circuit pattern after filling the hole.

9. The method for manufacturing a packaging carrier according to claim 1, characterized in that: The film stripping method is the MSAP film stripping process, and the surface metal removal method is etching. The etching amount of the surface metal is preset before etching.

10. A packaging carrier, characterized in that: The packaging carrier is manufactured by adopting the packaging carrier manufacturing method described in any one of claims 1-9.

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