A hybrid optoelectronic integrated chip and a manufacturing method, a laser chip

Abstract

The application discloses a kind of hybrid optoelectronic integrated chip and manufacturing method and laser chip, belong to the technical field of semiconductor;Hybrid optoelectronic integrated chip includes laser chip and optical transmission module, the epitaxial structure upper surface of laser chip has two grooves, ridge waveguide is formed between two grooves, the upper surface of epitaxial structure also has first alignment mark, and first alignment mark is groove structure;Optical transmission module includes substrate and waveguide arranged on substrate, and second alignment mark is also arranged on substrate;Laser chip is aligned and coupled by the alignment of first alignment mark and second alignment mark, and the input end surface of waveguide is aligned and coupled, improve the alignment coupling precision and coupling efficiency of automatic equipment operation laser and waveguide, reduce the optical loss of laser to waveguide.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductors, and particularly relates to a hybrid optoelectronic integrated chip and a manufacturing method and a laser chip. BACKGROUND

[0002] In the integration of lasers, due to the difference in material properties, the alignment and assembly process of mixing multiple components is very complex. For example, a silicon-based hybrid optoelectronic integrated chip, that is, integrating a laser based on InP, GaAs and other III-V group materials with a silicon-based waveguide device on one chip, can not only reduce the cost of the device, but also achieve high performance. It is one of the most practical technical routes in the silicon photon industry at present, and is widely used in high-speed silicon optical modules in data centers and high-performance silicon optical modulation FMCW (frequency-modulated continuous wave) laser radar modules.

[0003] Among them, how to effectively couple the light of a single-mode laser to a silicon-based waveguide is a major issue at present. In the early stage, it is often necessary to actively align the light and adjust the light power of the silicon waveguide to the maximum to achieve alignment coupling. This method not only has a complex process, but also takes a long time. With the gradual expansion of the application market of silicon-based hybrid integration, in order to make the process simple and easy to implement, an automatic placement machine equipped with a high-precision camera is selected to achieve the purpose of alignment coupling. The common method is to realize alignment by alignment marks. In the prior art, alignment marks are formed on the surface of the device by metal deposition. Due to the position deviation of the metal layer mask exposure and evaporation process itself and the wide distribution range of the metal deposition thickness, there is a risk of large deviation in the horizontal and vertical directions. Therefore, due to the uncertainty of the relative position of the laser mark position and the waveguide position, the coupling accuracy and efficiency of the automatic placement machine are seriously affected. SUMMARY

[0004] The purpose of the present application is to provide a hybrid optoelectronic integrated chip and a manufacturing method and a laser chip to reduce the optical loss of the laser to the waveguide.

[0005] In order to achieve the above purpose, the technical scheme of the present application is as follows:

[0006] A hybrid optoelectronic integrated chip, comprising a laser chip and an optical transmission module; the laser chip comprises an epitaxial structure, the upper surface of the epitaxial structure has two grooves, a ridge waveguide is formed between the two grooves, and the upper surface of the epitaxial structure also has a first alignment mark, which is a groove structure; the optical transmission module comprises a substrate and a waveguide arranged on the substrate, and a second alignment mark is also arranged on the substrate; the laser chip is aligned and coupled with the input end face of the waveguide through the alignment of the first alignment mark and the second alignment mark.

[0007] Optionally, the groove structure of the first alignment mark is formed synchronously with the trench.

[0008] Optionally, a passivation layer and a first metal electrode layer are sequentially arranged on the upper surface of the epitaxial structure, the passivation layer is provided with an opening on the ridge waveguide, and the first metal electrode layer is in contact with the ridge waveguide through the opening; the first metal electrode layer does not cover the first alignment mark.

[0009] Optionally, the distance between the first alignment mark and the trench is more than 10 μm.

[0010] Optionally, the epitaxial structure of the laser chip comprises, sequentially from bottom to top, a lower cladding layer, an active region and an upper cladding layer, wherein the upper cladding layer comprises an etching stop layer and a waveguide layer arranged on the etching stop layer, and the depth of the trench and the groove structure reaches the surface of the etching stop layer.

[0011] Optionally, the ridge waveguide is coaxially arranged with the projection of the waveguide on the surface of the substrate.

[0012] Optionally, the epitaxial structure comprises an active region, and the center of the active region in the height direction is flush with the center of the waveguide in the height direction.

[0013] Optionally, the substrate is further provided with a height positioning block, and the laser chip is arranged on the height positioning block; the height of the height positioning block is set such that the vertical height difference between the top surface of the height positioning block and the center of the waveguide in the height direction is equal to the vertical height difference between the lower surface of the laser chip and the center of the active region in the height direction.

[0014] Optionally, the substrate is planned to have a laser arrangement area on the side of the input end surface of the waveguide, and a plurality of height positioning blocks are arranged at intervals on the laser arrangement area.

[0015] Optionally, the back surface of the laser chip is provided with a second metal electrode layer, the height positioning block is a metal connecting block, and the metal connecting block is electrically connected with the second metal electrode layer.

[0016] Optionally, the laser arrangement area and the waveguide arrangement area on the substrate have a height difference, and the height adjustment is realized by the surface height difference and the height positioning block to adapt to different sizes of device structures.

[0017] Optionally, the upper surface of the epitaxial structure is provided with at least two first alignment marks, the two first alignment marks are located on one side of the ridge waveguide, and the connecting line is parallel to the axis of the ridge waveguide.

[0018] Optionally, the substrate is provided with two second alignment marks on two sides of the waveguide respectively, and the line connecting the two second alignment marks on the same side is parallel to the axis of the waveguide.

[0019] Optionally, the laser chip is a laser based on III-V compound semiconductor material, the substrate is a silicon substrate, and the waveguide is a silicon waveguide.

[0020] A laser chip includes an epitaxial structure, an upper surface of the epitaxial structure has two grooves, a ridge waveguide is formed between the two grooves, and the upper surface of the epitaxial structure also has a first alignment mark, which is a groove structure.

[0021] Optionally, the first alignment mark is used for alignment in integration of the laser chip and the waveguide, and the groove structure is formed synchronously with the grooves.

[0022] A method for manufacturing the hybrid optoelectronic integrated chip described above, comprising:

[0023] Step A: manufacturing a laser chip, wherein a groove structure is formed on the upper surface of the epitaxial structure of the laser chip by synchronous lithography and etching, wherein the groove includes two spaced grooves, and the spacing forms a ridge waveguide, and the groove structure forms a first alignment mark;

[0024] Step B: manufacturing an optical transmission module, the optical transmission module includes a substrate and a waveguide provided on the substrate, and the substrate is also provided with a second alignment mark;

[0025] Step C: adjusting the position of the laser chip by identifying the first alignment mark and the second alignment mark, so that the first alignment mark and the second alignment mark satisfy a predetermined relative positional relationship, combining and fixing the lower surface of the laser chip with the optical transmission module, and aligning and coupling the light emitting end surface of the laser with the input end surface of the waveguide.

[0026] Optionally, the step A includes:

[0027] 1) depositing a dielectric layer mask on the upper surface of the epitaxial structure;

[0028] 2) using a mask plate with a ridge waveguide pattern and a first alignment mark pattern, patterning the dielectric layer mask by a lithography process and a first etching process;

[0029] 3) forming a groove corresponding to the ridge waveguide pattern and a groove structure corresponding to the first alignment mark pattern on the upper surface of the epitaxial structure by a second etching process, wherein the epitaxial structure is provided with an etching stop layer, and the etching depth reaches the etching stop layer;

[0030] 4) removing the dielectric layer mask.

[0031] Optionally, the step A further comprises:

[0032] 5) depositing a passivation layer on the upper surface of the epitaxial structure, and opening the passivation layer on the ridge waveguide;

[0033] 6) forming a first metal electrode layer on the passivation layer, wherein the first metal electrode layer does not cover the first alignment mark.

[0034] Optionally, a height positioning block is further arranged on the substrate, and the lower surface of the laser chip is fixedly combined with the height positioning block.

[0035] Optionally, the height positioning block is a metal connecting block made of a metal process; the step A further comprises forming a second metal electrode layer on the back surface of the epitaxial structure; and in the step C, the second metal electrode layer and the metal connecting block are fixedly connected and electrically connected through a metal bonding.

[0036] The present application has the following beneficial effects:

[0037] In the integration of the laser chip and the optical transmission module, the alignment mark of the laser is a groove structure, which can be made by the same process as the groove for forming the ridge waveguide, thereby ensuring the accuracy of the relative position of the alignment mark and the ridge waveguide in the horizontal direction, and accurately providing the vertical height information of the surface of the laser from the active region, thereby ensuring the accuracy of the relative position in the vertical direction, improving the alignment and coupling precision and the coupling efficiency of the automatic equipment operation laser and the waveguide, and reducing the optical loss from the laser to the waveguide.

[0038] Other features and beneficial effects of the present application will be described in the following description, and some of them will become apparent from the description, or will be understood by implementing the present application. BRIEF DESCRIPTION OF DRAWINGS

[0039] Figure 1 A schematic top view of the structure of the hybrid optoelectronic integrated chip of the embodiment;

[0040] Figure 2 A schematic cross-sectional view of the embodiment in the A-A direction (i.e., the laser cavity length direction); Figure 1

[0041] A schematic perspective view of the laser chip of the embodiment; Figure 3

[0042] A schematic cross-sectional view (perpendicular to the laser cavity length direction) of the laser chip of the embodiment; Figure 4

[0043] A flowchart of the preparation process of the laser chip of the embodiment; Figure 5

[0044] A flowchart of the preparation process of the laser chip of the embodiment;Figure 6 A top view schematic diagram of the optical transmission module of the embodiment;

[0045] Figure 7 A cross-sectional view (perpendicular to the laser cavity length direction) of the laser chip of the comparative example. DETAILED DESCRIPTION

[0046] The present application is further explained with reference to the drawing and specific embodiments. The drawing of the present application is only schematic and is provided for easier understanding of the present application, and the specific proportions thereof can be adjusted according to design requirements. The relative positions and front / back definitions of the elements in the figures described herein should be understood by those skilled in the art as referring to the relative positions of the components, and therefore can be reversed to present the same components, which should all be within the scope disclosed by the present specification.

[0047] Reference Figure 1 and Figure 2 The mixed optoelectronic integrated chip of the embodiment includes a laser chip 1 and an optical transmission module 2. The laser chip 1 and the optical transmission module 2 are made of materials with different characteristics. The laser chip 1 can be an edge-emitting laser made of compound semiconductor epitaxial technology, and the following will be described by taking a distributed feedback laser (DFB) of group III-V semiconductor as an example. The epitaxial structure 11 of the laser chip 1 has a ridge waveguide 12 on the surface, the ridge waveguide 12 is formed by setting two grooves 13 along the cavity length direction, and the surface of the epitaxial structure 11 also has a first alignment mark 14, which is a groove structure formed synchronously with the grooves 13. The optical transmission module 2 is a silicon-based optical transmission module, which includes a silicon-based substrate 21 and a silicon waveguide 22 arranged on the substrate 21, and the substrate 21 also has a height positioning block 23 and a second alignment mark 24. The laser chip 1 is arranged on the height positioning block 23, and the light-emitting end face 1a is opposite to the input end face 2a of the silicon waveguide 22, and the light-emitting end face 1a and the input end face 2a are aligned and coupled through the alignment of the first alignment mark 14 and the second alignment mark 24. The synchronous formation of the ridge waveguide 12 and the first alignment mark 14 means that the patterns of the ridge waveguide 12 and the first alignment mark 14 are made on a mask plate, and are formed by the same channel lithography and etching, so that the groove structure of the first alignment mark 14 and the grooves 13 used to form the ridge waveguide 12 have a clear horizontal position relationship and the same vertical depth, which can ensure the precision of the alignment and coupling.

[0048] The conventional epitaxial structure of group III-V semiconductor DFB is suitable for the present embodiment, and reference is made to Figure 3 and Figure 4, the epitaxial structure 11 of the laser chip 1 comprises, in order, a substrate 111, a lower cladding layer 112, an active region 113, and an upper cladding layer 114, two parallel grooves 13 are formed by etching the upper cladding layer 114, and a ridge waveguide 12 is formed in the interval between the two grooves 13. In an embodiment, the upper cladding layer 114 comprises, in order, a grating layer, a waveguide layer, a contact layer, and the like, or the grating can also be made in the lower cladding layer 112. The etching depth of the groove 13 stops in the upper cladding layer 114, and is preferably etched to a partial depth of the waveguide layer, which can be limited by setting an etching stop layer 1141. For example, the material of the waveguide layer is InP, and the material of the etching stop layer 1141 is InGaAsP. The first alignment mark 14 is etched synchronously with the groove 13, i.e., has the same depth, and the depth range is 1-2 μm. The first alignment mark 14 can accurately provide the vertical height information of the laser surface from the active region, and ensure the alignment position information in the vertical direction, so as to realize the alignment of the active region 113 and the silicon waveguide 22, and achieve the maximum optical transmission efficiency. Figure 1 , the interval d between the first alignment mark 14 and the groove 13 is more than 10 μm, and is preferably located at the surface edge of the laser to avoid affecting the performance of the device. In order to facilitate grabbing alignment, a pair of first alignment marks 14 can be arranged at both ends of the cavity length direction of one side of the ridge waveguide 12, and the center line is parallel to the axis of the ridge waveguide 12, i.e., has a clear distance relationship and direction indication relationship with the ridge waveguide 12 in the horizontal direction. By identifying the pair of first alignment marks 14, the axis position and direction of the ridge waveguide 12 can be determined. The first alignment mark 14 can adopt a cross shape, a T shape, or an L shape, and the size (the diameter of the circumscribed circle of the cross section) is about 10-50 μm. The upper surface of the epitaxial structure 11 is provided, in order, with a passivation layer 15 and a first metal electrode layer 16. The passivation layer 15 is, for example, silicon nitride or silicon oxide, and has a thickness of 100-500 nm. It covers the surface of the epitaxial structure 11, including being deposited in the groove structure of the first alignment mark 14, and has an opening 15a on the ridge waveguide 12. The first metal electrode layer 16 is in contact with the epitaxial structure 11 through the opening 15a. The first metal electrode layer 16 is not deposited in the area where the first alignment mark 14 is located. The back of the substrate 111 is provided with a second metal electrode layer 17. Preferably, the first metal electrode layer 16 is a P electrode, and the second metal electrode layer 17 is an N electrode, and the lower cladding layer 112 and the substrate 111 are N-type materials, and the upper cladding layer 114 is a P-type material.

[0049] In the manufacturing of the laser chip 1, reference is made to Figure 5After the epitaxial structure 11 is formed by the epitaxial growth process and the grating fabrication process, a dielectric layer mask 3, such as silicon oxide or silicon nitride, is deposited on the top surface of the epitaxial structure 11. A mask plate with a ridge waveguide pattern (defined by a trench pattern) and a first alignment mark pattern is used to transfer the patterns of the mask plate to the dielectric layer mask 3 by a photolithography process and a first etching process, to obtain a patterned dielectric layer mask 3. The patterned dielectric layer mask 3 is used as a shield to etch the epitaxial structure 11 by a second etching process, such as dry etching or dry etching with wet etching, to form a trench 13 corresponding to the ridge waveguide pattern and a groove structure corresponding to the first alignment mark pattern, and etch to the etching stop layer 1141, and then remove the dielectric layer mask 3. Subsequent processes include deposition of a passivation layer 15, cutting channel and electrode windowing process (to form an opening 15a), evaporation of a first metal electrode layer 16, grinding and thinning the substrate 111 to a chip thickness of 80-100 μm, and evaporation of a second metal electrode layer 17 on one side of the substrate 111. In addition, the conventional process of coating films on both ends of the laser chip 1 is also included, including AR (anti-reflection) film and HR (high reflection) film. When the mask plate is made, the ridge waveguide pattern and the first alignment mark pattern have a clear relative position relationship, and the position relationship of the ridge waveguide 12 and the first alignment mark 14 can be maintained by the same mask, photolithography and etching processes, and the first alignment mark 14 can provide the vertical height information of the laser surface distance from the active region 113.

[0050] In the optical transmission module 2, the second alignment mark 24 satisfies the predetermined relative position relationship with the silicon waveguide 22, which can be made by known alignment mark fabrication methods, including but not limited to patterned deposition or etching, and its shape includes cross-shaped, T-shaped or L-shaped patterns, and preferably has the same shape and size as the first alignment mark 14. Referring to Figure 6In an embodiment, two pairs of second alignment marks 24 are provided on the substrate 21, which are located on both sides of the axis of the silicon waveguide 22, i.e., at the four corners of the periphery. The connecting line of the two second alignment marks 24 on the same side is parallel to the axis of the silicon waveguide 22, so that the position and direction of the axis of the silicon waveguide 22 can be obtained by grabbing the second alignment marks. The height positioning block 23 is located on the laser preset region C on the substrate 21, which is a plurality of columnar structures with a spacing, and the vertical height difference between the upper surface and the center of the silicon waveguide 22 is the same as the vertical height difference between the lower surface of the laser chip 1 and the center of the active region 113. The center of the silicon waveguide 22 and the center of the active region 113 mentioned here refer to the midpoint of the vertical height on the input end face 2a and the light output end face 1a. The arrangement of the height positioning block 23 can be arbitrarily arranged according to the stability of the connection and the requirements of the connection method, for example, a relatively dense arrangement is provided in the ridge waveguide extension region and is provided at the four corners to provide powerful support. The silicon waveguide 22 can be integrated into the silicon optical chip 25, and the silicon optical chip 25 is provided on the substrate 21. When the height difference between the laser chip 1 and the silicon optical chip 25 is large, the surface of the substrate 21 for setting the laser chip 1 and the surface for setting the silicon optical chip 25 have a height difference, for example, the substrate 21 is provided with a mounting groove 21a, and the silicon optical chip 25 is arranged in the mounting groove 21a to adjust the matching height relationship. Thus, the matching of devices of different sizes can be achieved by the arrangement of the height positioning block and the mounting groove, thereby expanding the application range. At the same time, the height positioning block can provide a certain elastic control height space, and after reading the height information, the height is set to achieve height adjustment within a certain range to ensure accurate alignment in the height direction. Further, in an embodiment, at least part of the height positioning block 23 is a metal or alloy solder ball, and serves as an interface of an external circuit. The second metal electrode layer 17 of the laser chip 1 is combined with the height positioning block 23 by metal bonding and is electrically connected to realize circuit connection.

[0051] In the assembly process, an automatic placement machine with a high-precision camera is used to place one side of the second metal electrode layer 17 of the laser chip 1 on the height positioning block 23, and the first alignment mark 14 and the second alignment mark 24 are recognized by automatic or manual image recognition, respectively. The position of the laser is adjusted so that the first alignment mark 14 and the second alignment mark 24 satisfy the preset relative position relationship, thereby aligning the laser chip 1 with the silicon waveguide 22 in the horizontal direction, and achieving coaxial arrangement of the projection of the ridge waveguide 12 and the silicon waveguide 22 on the surface of the substrate 21. The pressure provided by the high-precision placement equipment to the laser chip 1 controls the complete contact and combination of the lower surface of the laser chip 1 and the upper surface of the height positioning block 23, for example, by using eutectic welding or other methods to realize fixation and electrical connection, thereby aligning the active region 113 of the laser and the center of the silicon waveguide 22 in the vertical direction, improving the alignment and coupling precision and efficiency of the automatic equipment operation of the laser and the silicon-based waveguide, and reducing the optical loss from the laser to the silicon-based waveguide.

[0052] In a comparative example, the metal alignment mark 18 on the laser chip 1' is prepared in the laser metal layer mask exposure and evaporation process, i.e. prepared synchronously with the first metal electrode layer 16, as shown in FIG. 2B. Other structures refer to the above-mentioned embodiments. Figure 7 As shown, other structures refer to the above-mentioned embodiments. Since the light emitting position of the laser is defined by the ridge waveguide 12 mask exposure and etching process, the ridge waveguide mask and the metal layer mask are different process layers, and there is always a certain degree of deviation in the horizontal position when the masks are aligned, and the alignment deviation of each wafer is not consistent due to the influence of process deviation uncertainty. As a result, there is always a deviation in the relative distance between the metal alignment mark 18 and the laser ridge waveguide 12 in the horizontal position, and the deviation value is different for different wafer batches. In addition, in the vertical direction, there is also a deviation between the position of the metal alignment mark 18 and the laser ridge waveguide 12, and the metal deposition thickness has a wide distribution range, resulting in a larger alignment coupling deviation in the vertical direction. Compared with the comparative example, the embodiment effectively improves the alignment coupling precision and coupling efficiency by determining the precise position relationship.

[0053] The above-mentioned embodiments are only used to further illustrate the hybrid optoelectronic integrated chip and the manufacturing method and the laser chip of the present application, but the present application is not limited to the embodiments, and any simple modification, equivalent change and modification made according to the technical essence of the present application to the above-mentioned embodiments all fall within the protection scope of the technical solutions of the present application.

Claims

1. A hybrid optoelectronic integrated chip, characterized in that: The system includes a laser chip and an optical transmission module. The laser chip includes an epitaxial structure with two trenches on its upper surface, forming a ridge waveguide between the two trenches. The upper surface of the epitaxial structure also has a first alignment mark, which is a groove structure formed synchronously with the trenches. The optical transmission module includes a substrate and a waveguide disposed on the substrate. The substrate also has a second alignment mark. The laser chip aligns and couples its output end face with the input end face of the waveguide by aligning the first and second alignment marks.

2. The hybrid optoelectronic integrated chip according to claim 1, characterized in that: A passivation layer and a first metal electrode layer are sequentially disposed on the upper surface of the epitaxial structure. The passivation layer has an opening on the ridge waveguide, and the first metal electrode layer contacts the ridge waveguide through the opening. The first metal electrode layer does not cover the first alignment mark.

3. The hybrid optoelectronic integrated chip according to claim 1, characterized in that: The distance between the first alignment mark and the trench exceeds 10 μm.

4. The hybrid optoelectronic integrated chip according to claim 1, characterized in that: The epitaxial structure of the laser chip includes a lower cladding layer, an active region, and an upper cladding layer sequentially disposed on a substrate. The upper cladding layer includes an etch stop layer and a waveguide layer disposed on the etch stop layer. The depth of the trench and groove structure extends to the surface of the etch stop layer.

5. The hybrid optoelectronic integrated chip according to claim 1, characterized in that: The ridge waveguide and the projection of the waveguide on the substrate surface are coaxially arranged.

6. The hybrid optoelectronic integrated chip according to claim 1, characterized in that: The epitaxial structure includes an active region, the center of which in the height direction is flush with the center of the waveguide in the height direction.

7. The hybrid optoelectronic integrated chip according to claim 6, characterized in that: The substrate is further provided with a height positioning block, and the laser chip is disposed on the height positioning block; the height of the height positioning block is set such that the vertical height difference between the top surface of the height positioning block and the center of the waveguide in the height direction is equal to the vertical height difference between the lower surface of the laser chip and the center of the active region in the height direction.

8. The hybrid optoelectronic integrated chip according to claim 7, characterized in that: The substrate has a laser mounting area located on one side of the input end face of the waveguide, and a plurality of height positioning blocks are arranged at intervals on the laser mounting area.

9. The hybrid optoelectronic integrated chip according to claim 7, characterized in that: The laser chip has a second metal electrode layer on its back side, and the height positioning block is a metal connecting block that is electrically connected to the second metal electrode layer.

10. The hybrid optoelectronic integrated chip according to claim 1, characterized in that: The upper surface of the epitaxial structure is provided with at least two first alignment marks, which are located on one side of the ridge waveguide and the line connecting them is parallel to the axis of the ridge waveguide.

11. The hybrid optoelectronic integrated chip according to claim 10, characterized in that: Two second alignment marks are respectively provided on both sides of the waveguide on the substrate, and the line connecting the two second alignment marks on the same side is parallel to the axis of the waveguide.

12. The hybrid optoelectronic integrated chip according to claim 1, characterized in that: The laser chip is a laser based on III-V compound semiconductor materials, the substrate is a silicon-based substrate, and the waveguide is a silicon waveguide.

13. A method for fabricating a hybrid optoelectronic integrated chip according to any one of claims 1 to 12, characterized in that, include: Step A: Fabricate a laser chip, wherein trenches and groove structures are formed on the upper surface of the epitaxial structure of the laser chip by synchronous photolithography and etching, wherein the trenches include two spaced trenches, the spaced trenches forming a ridge waveguide, and the groove structures forming a first alignment mark; Step B: Fabricate an optical transmission module, which includes a substrate and a waveguide disposed on the substrate. The substrate is also provided with a second alignment mark and a height positioning block. Step C: Adjust the position of the laser chip by identifying the first alignment mark and the second alignment mark so that the first alignment mark and the second alignment mark meet the preset relative position relationship, and fix the lower surface of the laser chip with the height positioning block so that the light output end face of the laser is aligned and coupled with the input end face of the waveguide.

14. A laser chip, characterized in that: The device includes an epitaxial structure, the upper surface of which has two grooves forming a ridge waveguide between the two grooves. The upper surface of the epitaxial structure also has a first alignment mark, which is a groove structure. The first alignment mark is used for alignment in the integration of the laser chip and the waveguide. The groove structure is formed synchronously with the groove.

15. The laser chip according to claim 14, characterized in that: The distance between the first alignment mark and the trench exceeds 10 μm.

16. The laser chip according to claim 14, characterized in that: A passivation layer and a first metal electrode layer are sequentially disposed on the upper surface of the epitaxial structure. The passivation layer has an opening on the ridge waveguide, and the first metal electrode layer contacts the ridge waveguide through the opening. The first metal electrode layer does not cover the first alignment mark.

17. The laser chip according to claim 14, characterized in that: The epitaxial structure includes a lower cladding layer, an active region, and an upper cladding layer sequentially disposed on a substrate, wherein the upper cladding layer includes an etch stop layer and a waveguide layer disposed on the etch stop layer, and the depth of the trench and groove structure extends to the surface of the etch stop layer.

18. The laser chip according to claim 14, characterized in that: The upper surface of the epitaxial structure is provided with at least two first alignment marks, which are located on one side of the ridge waveguide and the line connecting them is parallel to the axis of the ridge waveguide.

19. The laser chip according to claim 14, characterized in that: The laser chip is a laser based on III-V compound semiconductor materials.

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