Wafer-scale system-in-package structure and forming method thereof

Abstract

The invention discloses a wafer-scale system-in-package structure and a forming method thereof, and the structure comprises a rewiring layer which comprises an upper surface and a lower surface which are opposite to each other; the plurality of chip modules are mounted on the upper surface of the rewiring layer and are electrically connected with the rewiring layer; the back side bridging chip is mounted on the lower surface of the re-wiring layer and is electrically connected with the re-wiring layer, and the back side bridging chip is used for enabling the adjacent chip modules to be mutually connected; the first plastic package layer is located on the upper surface of the rewiring layer and wraps the chip module, and the first plastic package layer is exposed out of the upper surface of the chip module. According to the invention, the bandwidth (band-width) of the system-in-package structure of the wafer scale is improved. According to the method, support of national key research and development plan projects (the project number is 2023YFB4404300, and the project number is 2023YFB4404305) is obtained.

Description

Technical Field

[0001] The present application relates to the field of semiconductor packaging, and in particular to a wafer-scale system-level packaging structure and a method for forming the same. Background Art

[0002] System in Package (SiP) integrates chips with various functions such as optoelectronics, digital / logic, radio frequency, storage, etc. into one package in the form of chip stacking or package stacking, thereby realizing a system that can realize the above multiple functions.

[0003] The demand for data computing in today's emerging fields (mobile devices, artificial intelligence, automotive electronics, data storage, etc.) is growing exponentially. In order to meet the needs of high-performance computing such as high density, high speed, high heat dissipation, low power consumption, and low latency, the existing system-level packaging is expanding towards wafer scale, that is, integrating multiple chip sub-modules arranged in rows and columns on a silicon wafer to form a wafer-scale system-level packaging structure.

[0004] However, the bandwidth of existing wafer-scale system-level packaging structures still needs to be improved. Summary of the invention

[0005] The present application aims to solve the problem of providing a wafer-scale system-in-package structure and a method for forming the same, so as to improve the bandwidth of the wafer-scale system-in-package structure.

[0006] This application belongs to the National Key R&D Program (Project No.: 2023YFB4404300, Subject No.: 2023YFB4404305). To solve the above problems, this application provides a wafer-scale system-level packaging structure, including: a rewiring layer, the rewiring layer comprising an upper surface and a lower surface opposite to each other; A plurality of chip modules, wherein the plurality of chip modules are mounted on the upper surface of the rewiring layer and are electrically connected to the rewiring layer; A back bridge chip, the back bridge chip is mounted on the lower surface of the rewiring layer and is electrically connected to the rewiring layer, and the back bridge chip is used to interconnect adjacent chip modules; The upper surface of the rewiring layer is covered with a first plastic packaging layer of the chip module, and the first plastic packaging layer exposes the upper surface of the chip module.

[0007] In an optional embodiment, the rewiring layer includes a passivation layer and a plurality of discrete first wirings and a plurality of discrete second wirings located in the passivation layer; the electrical connection between the plurality of chip modules and the rewiring layer includes: the chip module is electrically connected to part of the first wirings and part of the second wirings.

[0008] In an optional embodiment, the back bridge chip includes a substrate and a connecting line located on the substrate; the electrical connection between the back bridge chip and the redistribution layer includes: the connecting line in the back bridge chip is electrically connected to a portion of the second wiring, and the back bridge chip together with a portion of the second wiring interconnects adjacent chip modules.

[0009] In an optional embodiment, the chip module includes: a substrate, a plurality of semiconductor chips and a plastic encapsulation layer, wherein the substrate includes a relative front and back side, the substrate has a connection structure, the back side of the substrate has an external terminal, the external terminal is electrically connected to the connection structure and is electrically connected to part of the first wiring and part of the second wiring, a plurality of the semiconductor chips are mounted on the front side of the substrate, the semiconductor chips are electrically connected to the connection structure, and the plastic encapsulation layer is located on the front side of the substrate and covers the plurality of the semiconductor chips.

[0010] In an optional embodiment, the substrate is a silicon substrate, a glass substrate or a rewiring substrate.

[0011] In an optional embodiment, when the substrate is a re-distribution substrate, a second bridge chip is further embedded in the re-distribution substrate, and the second bridge chip is electrically connected to a part of the connection structure in the re-distribution substrate.

[0012] In an optional embodiment, corresponding substrates in at least two adjacent chip modules in the system-level package structure are of the same type or different types.

[0013] In an optional embodiment, the corresponding substrates in at least two adjacent chip modules in the system-level packaging structure are of the same type, including: the corresponding substrates in at least two adjacent chip modules in the system-level packaging structure are all silicon substrates; or the corresponding substrates in at least two adjacent chip modules in the system-level packaging structure are all glass substrates; or the corresponding substrates in at least two adjacent chip modules in the system-level packaging structure are all rewiring substrates.

[0014] In an optional embodiment, the corresponding substrates of at least two adjacent chip modules in the system-level packaging structure are of different types, including: one type of the corresponding substrates of at least two adjacent chip modules in the system-level packaging structure is a silicon substrate, and the other type is a glass substrate; or one type of the corresponding substrates of at least two adjacent chip modules in the system-level packaging structure is a silicon substrate, and the other type is a redistribution substrate; or one type of the corresponding substrates of at least two adjacent chip modules in the system-level packaging structure is a glass substrate, and the other type is a redistribution substrate.

[0015] In an optional embodiment, the connection structure is one or more of a metal layer, a connection plug, a through-hole connection structure, and a via connection structure.

[0016] In an optional embodiment, it also includes: a first bridging structure mounted on the upper surface of the rewiring layer at the edge of the chip module, the first bridging structure is used to interconnect adjacent chip modules; a second bridging structure mounted on the upper surface of the rewiring layer at the corner of the chip module, the second bridging structure is used to interconnect adjacent chip modules around the corner; and edge dummy devices of different sizes mounted on the upper surface and / or lower surface of the edge area of ​​the rewiring layer outside the chip module array.

[0017] In an optional embodiment, the rewiring layer also includes a plurality of discrete third wirings located in the passivation layer, and the first bridging structure is electrically connected to the adjacent chip modules through the third wirings; the first bridging structure includes a first circuit layer and a first supporting layer located on the upper surface of the first circuit layer, the first circuit layer includes a first dielectric layer, a first circuit located in the first dielectric layer, and a first welding protrusion protruding on the lower surface of the first dielectric layer and electrically connected to the first circuit, when the first bridging structure is mounted on the rewiring layer, the first welding protrusion is electrically connected to the corresponding third wiring in the rewiring layer, and the first bridging structure together with the third wiring in the rewiring layer interconnects the adjacent chip modules.

[0018] In an optional embodiment, the rewiring layer also includes a plurality of discrete fourth wirings located in the passivation layer, and the second bridging structure is electrically connected to the adjacent chip modules through the fourth wirings; the second bridging structure includes a second circuit layer and a second supporting layer located on the upper surface of the second circuit layer, the second circuit layer includes a second dielectric layer, a second circuit located in the second dielectric layer, and a second welding protrusion protruding on the lower surface of the second dielectric layer and electrically connected to the second circuit, when the second bridging structure is mounted on the rewiring layer, the second welding protrusion is electrically connected to the corresponding fourth wiring in the rewiring layer, and the second bridging structure together with the fourth wiring in the rewiring layer interconnects the adjacent chip modules around the corner head.

[0019] In an optional embodiment, the edge dummy component is one or more of a passive component, a heat dissipation discrete component or a dummy piece.

[0020] In an optional embodiment, it also includes: a plurality of discrete metal bumps located on the lower surface of the rewiring layer, the metal bumps being electrically connected to the corresponding first wirings; and a second plastic encapsulation layer located on the lower surface of the rewiring layer and covering the metal bumps and the back bridge chip, the second plastic encapsulation layer exposing the lower surface of the metal bumps.

[0021] In an optional embodiment, it also includes: a power supply module mounted on the lower surface of the second plastic packaging layer and electrically connected to the metal bump, the power supply module supplies power to at least two adjacent functional sub-modules on the upper surface of the silicon substrate.

[0022] In an optional embodiment, it also includes: a plurality of discrete metal bumps located on the lower surface of the rewiring layer, the metal bumps being electrically connected to the corresponding first wirings; a power supply module mounted on the lower surface of the metal bumps; and a second plastic packaging layer located on the lower surface of the rewiring layer and covering the metal bumps, the power supply module and the back bridge chip, the second plastic packaging layer exposing the lower surface of the power supply module.

[0023] On the other hand, the present application also provides a method for forming a wafer-scale system-level packaging structure, comprising: forming a rewiring layer, the rewiring layer comprising opposing upper and lower surfaces; Providing a plurality of chip modules, mounting the plurality of chip modules on the upper surface of the rewiring layer and electrically connecting the plurality of chip modules to the rewiring layer; Providing a backside bridge chip, mounting the backside bridge chip on the lower surface of the rewiring layer and electrically connecting the backside bridge chip to the rewiring layer, wherein the backside bridge chip is used to interconnect adjacent chip modules; A first plastic packaging layer of the chip module is coated on the upper surface of the rewiring layer, and the first plastic packaging layer exposes the upper surface of the chip module.

[0024] In an optional embodiment, the process of forming a rewiring layer includes: providing a carrier board; forming a rewiring layer on the carrier board, the rewiring layer including a passivation layer and a plurality of discrete first wirings and a plurality of discrete second wirings located in the passivation layer; after forming the first plastic encapsulation layer, removing the carrier board and mounting the back bridge chip; the electrical connection between the plurality of chip modules and the rewiring layer includes: the chip module is electrically connected to a portion of the first wirings and a portion of the second wirings.

[0025] In an optional embodiment, the back bridge chip includes a substrate and a connecting line located on the substrate; the electrical connection between the back bridge chip and the redistribution layer includes: the connecting line in the back bridge chip is electrically connected to a portion of the second wiring, and the back bridge chip together with a portion of the second wiring interconnects adjacent chip modules.

[0026] In an optional embodiment, the chip module includes: a substrate, a plurality of semiconductor chips and a plastic encapsulation layer, wherein the substrate includes a relative front and back side, the substrate has a connection structure, the back side of the substrate has an external terminal, the external terminal is electrically connected to the connection structure and is electrically connected to part of the first wiring and part of the second wiring, a plurality of the semiconductor chips are mounted on the front side of the substrate, the semiconductor chips are electrically connected to the connection structure, and the plastic encapsulation layer is located on the front side of the substrate and covers the plurality of the semiconductor chips.

[0027] In an optional embodiment, the substrate is a silicon substrate, a glass substrate or a rewiring substrate.

[0028] In an optional embodiment, when the substrate is a re-distribution substrate, a second bridge chip is further embedded in the re-distribution substrate, and the second bridge chip is electrically connected to a part of the connection structure in the re-distribution substrate.

[0029] In an optional embodiment, corresponding substrates in at least two adjacent chip modules in the system-level package structure are of the same type or different types.

[0030] In an optional embodiment, it also includes: mounting a first bridge structure on the upper surface of the rewiring layer at the edge of the chip module, the first bridge structure is used to interconnect adjacent chip modules; mounting a second bridge structure on the upper surface of the rewiring layer at the corner of the chip module, the second bridge structure is used to interconnect adjacent chip modules around the corner; mounting edge dummy devices of different sizes on the upper surface and / or lower surface of the edge area of ​​the rewiring layer outside the chip module array The advantages of the technical solution of this application are: The wafer-scale system-level packaging structure and its formation method in the aforementioned embodiments of the present application, the packaging structure includes a rewiring layer, the rewiring layer includes a relative upper surface and a lower surface; a plurality of chip modules, the plurality of chip modules are mounted on the upper surface of the rewiring layer and electrically connected to the rewiring layer; a back bridge chip, the back bridge chip is mounted on the lower surface of the rewiring layer and electrically connected to the rewiring layer, the back bridge chip is used to interconnect adjacent chip modules; the first plastic sealing layer located on the upper surface of the rewiring layer covers the chip module, the first plastic sealing layer exposes the upper surface of the chip module. Therefore, in the present application, in addition to interconnecting adjacent chip modules through the wiring layer (first wiring), adjacent chip modules can also be interconnected through the back bridge chip, thereby realizing the diversity of interconnection between adjacent chip modules, further improving the bandwidth (band-width) between adjacent chip modules, and thus improving the entire bandwidth (band-width) of the wafer-scale system-level packaging structure.

[0031] Furthermore, the types of the substrate include a silicon substrate, a glass substrate or a rewiring substrate, and the corresponding substrates in at least two adjacent chip modules in the system-level packaging structure are of the same type or different types to meet different performance requirements, different functional requirements, and different packaging requirements of the packaging structure.

[0032] Furthermore, the wafer-scale system-level packaging structure further includes: a first bridge structure mounted on the upper surface of the rewiring layer at the edge of the chip module, the first bridge structure is used to interconnect adjacent chip modules; a second bridge structure mounted on the upper surface of the rewiring layer at the corner of the chip module, the second bridge structure is used to interconnect adjacent chip modules around the corner. The first bridge structure and the second bridge structure further increase the channels connecting adjacent chip modules (in addition to the first wiring in the rewiring layer and the back bridge chip, the first bridge structure and the second bridge structure are also included), thereby further improving the bandwidth (band-width) between adjacent chip modules, and further improving the overall bandwidth (band-width) of the wafer-scale system-level packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1-Figure 2 FIG. 1 is a schematic diagram of a top view of a wafer-scale system-level packaging structure in an embodiment of the present application, wherein Figure 2 for Figure 1 Schematic diagram of the cross-sectional structure along the cutting line CC1; Figure 3 It is a schematic structural diagram of a wafer-scale system-level packaging structure in another embodiment of the present application; Figure 4 A schematic structural diagram of a wafer-scale system-level packaging structure in another embodiment of the present application; Figure 5 A schematic structural diagram of a wafer-scale system-level packaging structure in another embodiment of the present application; Figure 6 A schematic structural diagram of a wafer-scale system-level packaging structure in another embodiment of the present application; Figure 7 A schematic structural diagram of a wafer-scale system-level packaging structure in another embodiment of the present application; Figure 8-10 This is a schematic structural diagram of a wafer-scale system-level packaging structure in another embodiment of the present application. Fig. 9 In one embodiment Figure 8 Schematic diagram of the cross-sectional structure along the cutting line AA1. Fig.10 In one embodiment Figure 8 Schematic diagram of the cross-sectional structure along the cutting line BB1; Fig.11 In another embodiment Figure 8 Schematic diagram of the cross-sectional structure along the cutting line AA1; Fig.12 In another embodiment Figure 8 Schematic diagram of the cross-sectional structure along the cutting line AA1. DETAILED DESCRIPTION

[0034] The specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. When describing the embodiments of the present application in detail, for the sake of convenience, the schematic diagrams will not be partially enlarged according to the general proportion, and the schematic diagrams are only examples, which should not limit the scope of protection of the present application. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0035] An embodiment of the present application first provides a wafer-scale system-level packaging structure, combined with Figure 1-Figure 2 ,in Figure 2 for Figure 1 The schematic diagram of the cross-sectional structure along the cutting line CC1 includes: a rewiring layer 104, the rewiring layer comprising an upper surface and a lower surface opposite to each other; A plurality of chip modules 20, wherein the plurality of chip modules 20 are mounted on the upper surface of the rewiring layer 104 and are electrically connected to the rewiring layer 104; Backside bridge chip 423 (reference Figure 2 ), the back bridge chip 423 is mounted on the lower surface of the rewiring layer 104 and is electrically connected to the rewiring layer 104, and the back bridge chip 423 is used to interconnect the adjacent chip modules 20; The first plastic packaging layer 111 covering the chip module 20 is located on the upper surface of the redistribution layer 104 , and the first plastic packaging layer 111 exposes the upper surface of the chip module 20 .

[0036] Specifically, in one embodiment, the rewiring layer 104 includes a passivation layer 100 and a plurality of discrete first wirings 102 and a plurality of discrete second wirings 103 located in the passivation layer 100. Part of the first wirings 102 can be used for electrical connection between the upper surface and the lower surface of the rewiring layer 104, part of the first wirings 102 can be used for electrical connection between adjacent chip modules 20, the second wirings 103 are used for electrical connection with the chip module 20 and the back bridge chip 423, and the passivation layer 100 is used for electrical isolation between the first wirings 102, between the second wirings 103, and between the first wirings 102 and the second wirings 103. In one embodiment, the passivation layer 100 can be a single-layer or multi-layer stacked structure, and the corresponding first wirings 102 and the second wirings 103 can also be a single-layer or multi-layer line structure. The passivation layer 100 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride, and the first wiring 102 and the second wiring 103 may be one or more of Al, Cu, W, Au, Ag, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN.

[0037] The packaging structure is a wafer-scale system-level packaging structure. The size of the wafer-scale system-level packaging structure is relatively large, and the size of the corresponding rewiring layer 104 is also relatively large. In a specific embodiment, when the rewiring layer 104 is circular, the diameter of the rewiring layer 104 can be 300 mm, 450±5 mm, and when the rewiring layer 104 is square, the diagonal size of the rewiring layer 104 can be 300 mm, 450±10 mm.

[0038] The back bridge chip 423 is used to interconnect adjacent chip modules 20. In one embodiment, the back bridge chip 423 includes a substrate and connection lines on the substrate, and the density of the connection lines in the back bridge chip 423 is greater than the density of the wiring (such as the first wiring 102 and the second wiring 103) in the rewiring layer 104. The back bridge chip 423 can achieve a higher wiring density within a certain space. The substrate is a semiconductor substrate, specifically a silicon substrate, a germanium substrate or a silicon nitride substrate, the connecting line is a single-layer or multi-layer connecting line, the material of the connecting line is metal, the connecting lines are isolated by a dielectric layer located on the surface of the substrate, the dielectric layer can be a single-layer or multi-layer structure, the material of the dielectric layer can be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride; the back bridge chip 423 is electrically connected to the rewiring layer 104, including: the connecting line in the back bridge chip 423 is electrically connected to part of the second wiring 103, that is, the back bridge chip 423 together with part of the second wiring 103 interconnects the adjacent chip modules 20. Therefore, in the present application, in addition to being interconnected through the first wiring 102 in the wiring layer 104, the adjacent chip modules 20 can also be interconnected through the back bridge chip 423 and the second wiring 103 in the wiring layer 104 (the adjacent chip modules 20 can communicate and / or transfer data during interconnection), thereby achieving diversity in the interconnection between the adjacent chip modules 20, further improving the bandwidth (band-width) between the adjacent chip modules 20, and thereby improving the overall bandwidth (band-width) of the wafer-scale system-level packaging structure.

[0039] In a specific embodiment, the back bridge chip 423 includes a first surface and a second surface opposite to each other, the first surface has a protruding solder bump 413, when the back bridge chip 423 is mounted on the lower surface of the rewiring layer 104, the first surface of the back bridge chip 423 faces the lower surface of the rewiring layer 104, and the solder bump 413 on the first surface of the back bridge chip 423 and the second wiring 103 in the rewiring layer 104 are soldered together by solder. In an embodiment, an underfill layer 414 is also filled between the first surface of the back bridge chip 423 and the lower surface of the rewiring layer 104.

[0040] In one embodiment, the system-level packaging structure further includes: a plurality of discrete metal bumps 113 located on the lower surface of the rewiring layer 104, the metal bumps 113 being electrically connected to the corresponding first wiring 102; a second plastic encapsulation layer 112 located on the lower surface of the rewiring layer 104 and covering the metal bumps 113 and the back bridge chip 423, the second plastic encapsulation layer 112 exposing the lower surface of the metal bumps 113, the metal bumps 113 serving as ports for connecting the system-level packaging structure with other packaging structures, devices or substrates. In one embodiment, the material of the metal bumps 113 is one or more of Al, Cu, W, Au, Ag, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN. The materials of the first plastic encapsulation layer 111 and the second plastic encapsulation layer 112 may be epoxy resin, polyimide resin, benzocyclobutene resin or polybenzoxazole resin with or without fillers; or may be polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyether sulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol with or without fillers. In some embodiments, the filler may be an inorganic filler or an organic filler.

[0041] The chip modules 20 have specific functions. A plurality of chip modules 20 are arranged in an array and mounted on the upper surface of the rewiring layer 104. The number of the chip modules 20 is at least 2, and specifically can be 2, 4, 9, 16, 25 or more (e.g., N 2 (N is greater than 5), a plurality of chip modules 20 can be arranged in a 1X1, 2X2, 3X3, 4X4, 5X5 array or more arrays and mounted on the upper surface of the rewiring layer 104. Figure 1As shown, nine chip modules 20 are arranged in a 3X3 array and mounted on the upper surface of the rewiring layer 104 as an example. In one embodiment, the system-level packaging structure further includes: edge dummy devices 301 of different sizes mounted on the upper surface and / or lower surface of the edge region of the rewiring layer 104 outside the chip module array. Specifically, the edge dummy devices 301 are mounted only on the upper surface or lower surface of the edge region of the rewiring layer 104 outside the chip module array, or the edge dummy devices 301 are mounted on both the upper surface and the lower surface of the edge region of the rewiring layer 104 outside the chip module array. The edge dummy devices 301 will be described in detail in subsequent embodiments.

[0042] In one embodiment, each of the chip modules 20 includes a plurality of semiconductor chips 201. Specifically, each of the chip modules 20 includes one or at least two (two or more) semiconductor chips 201. In one specific embodiment, when each of the chip modules 20 includes at least two semiconductor chips 201, the sizes and / or functions of the at least two semiconductor chips 201 are different. In another specific embodiment, when each of the chip modules 20 includes at least two semiconductor chips 201, the sizes and / or functions of some of the semiconductor chips 201 may be the same, and the sizes and / or functions of some of the semiconductor chips 201 may be different. In one embodiment, the semiconductor chips 201 include but are not limited to logic chips, memory chips, and sensor chips. In a specific embodiment, the logic chip may include but is not limited to a gate array, a cell substrate array, an embedded array, a structured application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a complex programmable logic device (CPLD), a graphics processing unit (GPU), a central processing unit (CPU), a microprocessing unit (MPU), a microcontroller unit (MCU), a logic integrated circuit (IC), an application processor (AP), a display driver IC (DDI), a radio frequency (RF) chip, a power chip or a complementary metal oxide semiconductor (CMOS) image sensor. The memory chip may include but is not limited to a dynamic random access memory (DRAM), a static random access memory (SRAM), a magnetoresistive random access memory (MRAM), a phase-change memory (PRAM), a resistive random access memory (RRAM) or a non-volatile memory chip (such as flash memory).

[0043] In one embodiment, the chip module 20 comprises: a substrate 200, a plurality of semiconductor chips 201 and a plastic encapsulation layer 208, wherein the substrate 200 comprises a front side and a back side opposite to each other, the substrate 200 comprises a connection structure 206, the back side of the substrate 200 comprises an external terminal 207, the external terminal 207 is electrically connected to the connection structure 205, a plurality of semiconductor chips 201 are mounted on the front side of the substrate 200, the semiconductor chips 201 are electrically connected to the connection structure 205, and the plastic encapsulation layer 208 is located on the front side of the substrate 200 and covers the plurality of semiconductor chips 201. The electrical connection of the plurality of chip modules to the rewiring layer comprises: the external terminal 207 on the chip module is electrically connected to part of the first wiring 102 and part of the second wiring 103 in the rewiring layer 104.

[0044] In one embodiment, the chip module 20 is mounted on the upper surface of the rewiring layer 104, including: each chip module 20 is mounted on the upper surface of the rewiring layer 104 in a flip-chip manner, specifically, the external terminal 207 in the chip module 20 is soldered together with the corresponding first wiring 102 and second wiring 103 in the rewiring layer 104 through solder.

[0045] In one embodiment, the semiconductor chip 201 includes an active surface and a back surface facing each other, the active surface has a soldering protrusion 213, an integrated circuit with a specific function (not shown in the figure) is formed in the semiconductor chip 201, and the soldering protrusion 213 is electrically connected to the integrated circuit. The mounting of several semiconductor chips 201 on the front surface of the substrate 200 includes: the mounting of several semiconductor chips 201 on the front surface of the substrate 200 by flip-chip, specifically, the active surface of the semiconductor chip 201 faces downward, and the soldering protrusion 213 on the active surface of the semiconductor chip 201 is soldered together with the substrate 200. In one embodiment, the soldering protrusion 213 may include a solder pad and a solder layer located on the surface of the solder pad. In another embodiment, the soldering protrusion 213 may also include a solder pad, a metal column located on the surface of the solder pad, and a solder layer located on the top surface of the metal column. The material of the solder pad and the metal column is metal, which may be one or more of aluminum, copper, nickel, tin, titanium, tungsten, platinum, chromium, tantalum, gold, and silver. The material of the solder layer is tin or a tin alloy, and the tin alloy is one or more of tin-silver, tin-zinc, tin-lead, tin-indium, tin-gold, tin-copper, tin-silver-copper, tin-silver-zinc, tin-bismuth-indium, tin-zinc-indium or tin-silver-antimony.

[0046] In one embodiment, an underfill layer 209 is filled between the active surface of the semiconductor chip 201 and the front surface of the substrate 200, and the overmolding layer 208 also covers the underfill layer. The underfill layer 209 and the overmolding layer 208 are both made of resin.

[0047] In one embodiment, the front surface of the substrate 200 further has a redistribution layer, and the redistribution layer includes a first dielectric layer 203 located on the front surface of the substrate 200 and a metal line 206 located in the first dielectric layer 203, and the upper surface of the first dielectric layer 203 partially exposes the metal line 206. When the welding protrusions 213 on the active surface of the semiconductor chip 201 are welded together with the substrate 200, the welding protrusions 213 on the active surface of the semiconductor chip 201 are welded together with the corresponding metal line 206 in the redistribution layer on the substrate 200, that is, the semiconductor chip 201 is electrically connected to the connection structure 205 through the metal line 206. The back surface of the substrate 200 further has a second dielectric layer 204, and the lower surface of the external terminal 207 is exposed in the second dielectric layer 204. In one embodiment, the material of the first dielectric layer 203 and the second dielectric layer 204 may be an inorganic material or an organic material, the inorganic material may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, the organic material may be a polymer resin material, specifically epoxy resin, polyimide resin, benzocyclobutene resin or polybenzoxazole resin. The material of the metal line 206 and the external terminal 207 is metal, specifically one or more of Al, Cu, W, Au, Ag, Pt, Ni, Ti, Ta, TiN, TaN, TaC, WN.

[0048] The corresponding substrates 200 in at least two adjacent chip modules 20 in the system-level packaging structure are of the same type or different types to meet different performance requirements, different functional requirements, and different packaging requirements of the packaging structure. In one embodiment, the type of the substrate 200 includes a silicon substrate, a glass substrate, or a rewiring substrate. The rewiring substrate includes two types: a rewiring substrate with a bridge chip embedded and a rewiring substrate without a bridge chip embedded. In a specific embodiment, the rewiring substrate with a bridge chip embedded has a second bridge chip 210 embedded in it (see Figure 4 ), the second bridge chip 210 is electrically connected to a portion of the connection structure 205 in the rewiring substrate. The connection structure 200 is one or more of a metal layer, a connection plug, a through-hole connection structure, and a via connection structure. (Bridge chip not embedded) In a specific embodiment, continue to refer to Figure 2The corresponding substrates 200 in at least two adjacent chip modules 20 in the system-level packaging structure are of the same type, and the substrates 200 are all silicon substrates, and the connection structure 205 is a through-hole connection structure, specifically a through-silicon via connection structure (TSV).

[0049] In another specific embodiment, continue to refer to Figure 2 The corresponding substrates 200 in at least two adjacent chip modules 20 in the system-level packaging structure are of the same type, and the substrates 200 are all glass substrates, and the connection structure 205 is a via connection structure.

[0050] In another specific embodiment, please refer to Figure 3 The corresponding substrates 200 in at least two adjacent chip modules 20 in the system-level package structure are of the same type, and the substrates 200 are all rewiring substrates (without embedding bridge chips), and the connection structures 205 in the substrates 200 are metal layers and connection plugs. The material of the substrates 200 is resin or other suitable materials.

[0051] In another specific embodiment, please refer to Figure 4 , the corresponding substrates 200 in at least two adjacent chip modules 20 in the system-level package structure are of the same type, and the substrates 200 are all rewiring substrates, the connection structure 205 in the substrate 200 is a metal layer and a connection plug, and a second bridge chip 210 is also embedded in the rewiring substrate, and the second bridge chip 210 is electrically connected to part of the connection structure 205 in the rewiring substrate. The number of the second bridge chip 210 can be one or more. The second bridge chip 210 has a higher density of connection lines than that in the rewiring substrate, so as to achieve a higher wiring density within a certain space.

[0052] In another specific embodiment, the corresponding substrates 200 in at least two adjacent chip modules 20 in the system-level packaging structure are of different types. Specifically, the corresponding substrates 200 in at least two adjacent chip modules 20 in the system-level packaging structure are of different types. One type is a silicon substrate, and the other type is a glass substrate.

[0053] In another specific embodiment, referring to Figure 5 The corresponding substrates 200 in at least two adjacent chip modules 20 in the system-level packaging structure are of different types. Specifically, the corresponding substrates 200 in at least two adjacent chip modules 20 in the system-level packaging structure are of different types. One type is a silicon substrate, and the other type is a rewiring substrate (without embedded bridge chip).

[0054] In another specific embodiment, continue to refer to Figure 5 The corresponding substrates 200 in at least two adjacent chip modules 20 in the system-level packaging structure are of different types. Specifically, the corresponding substrates 200 in at least two adjacent chip modules 20 in the system-level packaging structure are of different types. One type is a glass substrate, and the other type is a rewiring substrate (without embedded bridge chip).

[0055] In another specific embodiment, continue to refer to Figure 6 The corresponding substrates 200 in at least two adjacent chip modules 20 in the system-level packaging structure are of different types. Specifically, the corresponding substrates 200 in at least two adjacent chip modules 20 in the system-level packaging structure are of different types. One type is a rewiring substrate (without embedded bridge chip), and the other type is a rewiring substrate embedded with a second bridge chip 210.

[0056] In another specific embodiment, continue to refer to Figure 7 The corresponding substrates 200 in at least two adjacent chip modules 20 in the system-level packaging structure are of different types. Specifically, the corresponding substrates 200 in at least two adjacent chip modules 20 in the system-level packaging structure are of different types. One type is a silicon substrate or a glass substrate, and the other type is a rewiring substrate embedded with a second bridge chip 210.

[0057] In one embodiment, each of the chip modules 20 may be a cuboid or a cube, and each of the chip modules 20 includes four corners and edges between adjacent corners, that is, four corners and four edges. In other embodiments, the chip module 20 may be in other shapes, such as a cuboid, a cube, a parallelogram, or other regular three-dimensional shapes.

[0058] Another embodiment of the present application also provides a wafer-scale system-level packaging structure, referring to Figure 8-Figure 10 , Fig. 9 for Figure 8 Schematic diagram of the cross-sectional structure along the cutting line AA1. Fig.10 for Figure 8 The schematic cross-sectional structure diagram along the cutting line BB1 ​​direction, the main difference between this embodiment and the previous embodiment is that: the wafer-scale system-level packaging structure further includes: a first bridge structure 421 (reference Figure 8 and Fig. 9 ), the first bridge structure 421 is used to interconnect the adjacent chip modules 20; the second bridge structure 422 (reference Figure 8 and Fig.10), the second bridge structure 422 is used to interconnect the adjacent chip modules 20 around the corner. The first bridge structure 421 and the second bridge structure 422 further increase the channels connecting the adjacent chip modules 20 (in addition to the first wiring in the rewiring layer 104 and the back bridge chip 423, the first bridge structure 421 and the second bridge structure 422 are also included), so that the bandwidth (band-width) between the adjacent chip modules 20 is further improved, thereby further improving the overall bandwidth (band-width) of the wafer-scale system-level packaging structure.

[0059] In a specific embodiment, the first bridge structure 421 interconnects two adjacent chip modules 20 on both sides. In a specific embodiment, the second bridge structure 422 can interconnect two, three or four adjacent chip modules 20 on the periphery.

[0060] In one embodiment, continue to refer to Figure 8 and Fig. 9, the rewiring layer 104 further includes a plurality of discrete third wirings 105 located in the passivation layer 100, and the first bridge structure 421 is electrically connected to the adjacent chip module 20 through the third wirings. In one embodiment, the first bridge structure 421 includes a first circuit layer 401 and a first support layer 402 located on the upper surface of the first circuit layer 401, the first circuit layer 401 includes a first dielectric layer, a first circuit (not shown in the figure) located in the first dielectric layer, and a first welding protrusion protruding from the lower surface of the first dielectric layer and electrically connected to the first circuit, when the first bridge structure 421 is mounted on the rewiring layer 104, the first welding protrusion is electrically connected to the corresponding third wiring 105 in the rewiring layer 104, and the first bridge structure 421 together with the third wiring 105 in the rewiring layer 104 interconnects the adjacent chip modules 20. The first bridge structure 421 adopts the aforementioned specific structure, and while increasing the bandwidth (band-width) between adjacent chip modules 20, the first support layer 402 provides physical support for the first circuit layer 401 (because the thickness of the first circuit layer 401 is usually very thin and cannot be processed as a separate device), and protects the first circuit layer 401 from failures such as disconnection due to warping; and the first support layer 402 can also reduce the amount of the first plastic layer 111 formed on the upper surface of the rewiring layer 104, thereby increasing the Si / EMC ratio in the wafer-scale system-level packaging structure (the first support layer 402 is equivalent to Si), thereby reducing the overall warping of the wafer-scale system-level packaging structure due to the small Si / EMC ratio. In other embodiments, the first bridge structure 421 may only include the first circuit layer 401.

[0061] The first dielectric layer in the first circuit layer 401 is used for isolation between the first circuits. In one embodiment, the first dielectric layer can be a single-layer or multi-layer stacked structure, and the material of the first dielectric layer is one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride. The first circuit can also be a single-layer or multi-layer circuit structure, and the material of the first circuit is metal, specifically one or more of Al, Cu, W, Au, Ag, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN. The first support layer 402 is a single-layer or multi-layer stacked structure. The material of the first support layer 402 is one or more of silicon, silicon germanium, silicon carbide, glass, resin, and PCB core.

[0062] In one embodiment, the number of first bridging structures 421 surface-mounted on the rewiring layer 104 of each edge of the chip module 20 is one or more. When the number of the first bridging structures 421 is multiple, such as two or three, the multiple first bridging structures 421 are arranged in a direction parallel to the edge of the chip module 20.

[0063] In one embodiment, continue to refer to Figure 8 and Fig.10 , the rewiring layer 104 further includes a plurality of discrete fourth wirings 106 located in the passivation layer 100, and the second bridge structure 422 is connected to the adjacent chip module 20 through the fourth wirings 106. In one embodiment, the second bridge structure 422 includes a second circuit layer 403 and a second support layer 404 located on the upper surface of the second circuit layer 403, the second circuit layer 403 includes a second dielectric layer, a second circuit located in the second dielectric layer, and a second welding protrusion 403a protruding from the lower surface of the second dielectric layer and electrically connected to the second circuit, when the second bridge structure 422 is mounted on the silicon substrate, the second welding protrusion 403a is electrically connected to the corresponding fourth wiring 106 in the rewiring layer 104, and the second bridge structure 422 together with the corresponding fourth wiring 106 in the rewiring layer 104 interconnect the adjacent chip modules 20 around the corner. Through the second bridging structure 422 of the aforementioned specific structure, while further improving the bandwidth (band-width) between adjacent chip modules 20, the second supporting layer 404 provides physical support for the second circuit layer 403 (because the thickness of the second circuit layer 403 is usually very thin and cannot be processed as a separate device), and protects the second circuit layer 403 from failure such as broken wires due to warping; and the second supporting layer 404 can also buffer and balance the large stress at and near the corners of adjacent chip modules 20, thereby reducing the warping of the wafer-scale system-level packaging structure caused by the large stress at the corners of the chip modules 20.

[0064] The second dielectric layer in the second circuit layer 403 is used for isolation between the second circuits. The second dielectric layer can be a single layer or a multi-layer stacked structure. The material of the second dielectric layer is one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride. The second circuit can also be a single layer or a multi-layer circuit structure. The material of the second circuit is metal, which can be one or more of Al, Cu, W, Au, Ag, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN.

[0065] In one embodiment, the number of first bridge structures 421 mounted on the surface of the redistribution layer 104 of each corner of the chip module 20 is one, and the first bridge structure 421 is used to interconnect two or four chip modules 20 around the corner.

[0066] In one embodiment, the second supporting layer 404 is a flexible structure, and the rigidity of the second supporting layer 404 is less than the rigidity of the first plastic packaging layer 111, so that the second supporting layer 404 can effectively buffer and balance the large stress existing at and near the corners of adjacent chip modules 20, thereby effectively reducing the warping of the wafer-scale system-level packaging structure caused by the large stress at the corners of the chip modules 20.

[0067] In one embodiment, the second support layer 404 of the flexible structure includes a first buffer layer, a core layer located on the surface of the first buffer layer, and a second buffer layer located on the surface of the core layer, wherein the core layer has a blind hole. The blind hole is a cavity, or the blind hole is filled with a filling material. The second support layer of the structure has a smaller rigidity, thereby more effectively buffering and balancing the larger stress existing at and near the corners of adjacent chip modules.

[0068] In one embodiment, the system-level packaging structure further includes: edge dummy devices 301 of different sizes mounted on the upper surface of the edge region 12 of the rewiring layer 104 outside the chip module 20 array 11. Mounting a number of edge dummy devices 301 of different sizes on the upper surface of the edge region 12 of the rewiring layer 104 reduces the amount of the first plastic encapsulation layer 111 on the upper surface of the edge region 12 of the rewiring layer 104, thereby increasing the Si / EMC ratio of the edge region 12 (EMC is a plastic encapsulation material, and the edge dummy devices 301 are equivalent to Si), thereby reducing the difference between the Si / EMC ratio of the edge region 12 and the Si / EMC ratio of the middle region 11, thereby effectively regulating the warpage of the system packaging structure of the wafer-level super-large core module at room temperature or high temperature. In another embodiment, refer to Fig.11 or Fig.12 In addition to mounting edge dummy devices 301 of different sizes on the upper surface of the edge region 12 of the rewiring layer 104 outside the chip module 20 array 11, edge dummy devices 301 of different sizes are also mounted on the lower surface of the edge region 12 of the rewiring layer 104 outside the chip module 20 array 11.

[0069] In one embodiment, the edge dummy device 301 may be one or more of a passive device, a heat dissipation discrete component or a dummy piece. In a specific embodiment, when the edge dummy device 301 mounted on the upper surface of the edge region of the rewiring layer 104 is a passive device, the passive device may be electrically connected to the rewiring layer 104, and the passive device may be one or more of a resistor, a capacitor, and an inductor. In another specific embodiment, when the edge dummy device 301 mounted on the upper surface of the edge region of the rewiring layer 104 is a heat dissipation discrete component, such as a heat dissipation metal block, the lower surface of the heat dissipation discrete component is adhered to the upper surface of the edge region 11 of the rewiring layer 104 by a heat dissipation adhesive, and the heat dissipation discrete component may be used for heat dissipation of the packaging structure, and the material of the heat dissipation discrete component is a metal material used for heat dissipation. In another specific embodiment, when the edge dummy device 301 mounted on the upper surface of the edge area of ​​the rewiring layer 104 is a dummy chip, the lower surface of the dummy chip is adhered to the upper surface of the edge area 12 of the rewiring layer 104 by adhesive, and the dummy chip is a silicon particle without a circuit.

[0070] In one embodiment, the size of the edge dummy device 301 away from the middle area 11 is smaller than the size of the edge dummy device 301 close to the middle area 11. The upper surface of the edge area 12 is fully mounted with the edge dummy device 301, so as to further reduce the material of the first plastic encapsulation layer 111 on the edge area 12, thereby further increasing the Si / EMC ratio of the edge area 12 of the redistribution layer 104, thereby further reducing the difference between the Si / EMC ratio of the edge area 12 and the Si / EMC ratio of the middle area 11, which is conducive to better suppressing the warping of the wafer-scale system-level packaging structure.

[0071] In one embodiment, the edge dummy device 301 mounted on the upper surface of the edge region 12 close to the middle region 11 is a passive device, and the edge dummy device 301 mounted on the upper surface away from the middle region 11 is a heat dissipation discrete component or a dummy piece. The mounting method of the passive device (edge ​​dummy device 301) close to the middle region 11 can be the same as the mounting method of the chip module 20 to maintain consistency in the mounting method and the packaging structure to improve production capacity.

[0072] In one embodiment, continue to refer to Fig.11 The packaging structure also includes: a power supply module 501 mounted on the lower surface of the second plastic packaging layer 112 and electrically connected to the metal bump 113, and the power supply module 501 is used to supply power to at least two adjacent chip modules 20 on the upper surface of the redistribution layer 104.

[0073] The power supply module 501 can convert an external input voltage into a voltage of a specific magnitude and power and supply the voltage to the corresponding chip module 20 .

[0074] In one embodiment, the number of the power supply modules 501 may be one or more. When the number of the power supply modules 501 is one, one power supply module 501 supplies power to all the chip modules 20 on the upper surface of the rewiring layer 104. When the number of the power supply modules 501 is multiple, each power supply module 501 supplies power to multiple (specifically, 2-4) adjacent chip modules 20 on the upper surface of the rewiring layer 104.

[0075] In one embodiment, the power supply module 501 may include a substrate 505, which may be a PCB substrate, with dielectric layers 505 on the upper and lower surfaces of the substrate 505, with connecting lines 504 in the substrate 505 and the dielectric layer 505, with a plurality of pads 502 in the dielectric layer 505 on the upper surface of the PCB substrate, with the pads 502 being electrically connected to the connecting lines 504, and the pads 502 being soldered together with corresponding metal bumps 113 on the lower surface of the silicon substrate 103 through solder. In one embodiment, the power supply module 501 further includes: a semiconductor chip (and passive devices) mounted on the lower surface of the substrate 505 or embedded in the substrate 505 (not shown in the figure), the semiconductor chip may be a power supply control chip, and the semiconductor chip is electrically connected to the connecting lines 504.

[0076] In one embodiment, continue to refer to Fig.11 , further comprising: bonding materials 503 for fixing the four corners of the power supply module 501 to the corresponding lower surface of the second plastic packaging layer 112. The bonding materials 503 further fix the corners of the power supply module 501 to the second plastic packaging layer 112 to improve the mounting firmness of the larger power supply module 501.

[0077] In another embodiment, the structure of the second plastic encapsulation layer 112 in the packaging structure is different from that in the above-mentioned embodiment. Fig.12 The second plastic encapsulation layer 112 covers the back bridge chip 423 , the metal bumps 113 , the power supply module 501 and the edge dummy device 301 located on the lower surface of the redistribution layer 104 , and the second plastic encapsulation layer 112 exposes the lower surface of the power supply module 501 .

[0078] Another embodiment of the present application further provides a method for forming a wafer-scale system-level packaging structure, which is described below in conjunction with the accompanying drawings (it should be noted that the same or similar parts of this embodiment (the method for forming a wafer-scale system-level packaging structure) and the aforementioned embodiment (the wafer-scale system-level packaging structure) are not repeated in this embodiment, and please refer to the definitions or descriptions of the corresponding parts in the aforementioned embodiment for details).

[0079] refer to Figure 1 and Figure 2 , the forming method comprises: forming a rewiring layer 104, the rewiring layer comprising an upper surface and a lower surface opposite to each other; Providing a plurality of chip modules 20, mounting the plurality of chip modules 20 on the upper surface of the rewiring layer 104 and electrically connecting the plurality of chip modules 20 to the rewiring layer 104; Providing a back bridge chip 423, mounting the back bridge chip 423 on the lower surface of the rewiring layer 104 and electrically connecting the back bridge chip 423 to the rewiring layer 104, the back bridge chip 423 being used to interconnect adjacent chip modules 20; The first plastic encapsulation layer 111 of the chip module 20 is coated on the upper surface of the redistribution layer 104 , and the first plastic encapsulation layer 111 exposes the upper surface of the chip module 20 .

[0080] In one embodiment, the process of forming the rewiring layer 104 includes: providing a carrier (not shown in the figure); forming a rewiring layer 104 on the carrier, the rewiring layer 104 including a passivation layer 100 and a plurality of discrete first wirings 102 and a plurality of discrete second wirings 102 located in the passivation layer 100; after forming the first plastic encapsulation layer 111, removing the carrier and mounting the back bridge chip 423; the plurality of chip modules 20 being electrically connected to the rewiring layer 104 includes: the chip module 20 being electrically connected to a portion of the first wiring 102 and a portion of the second wiring 103.

[0081] In one embodiment, the back bridge chip 423 includes a substrate and a connecting line located on the substrate; the electrical connection between the back bridge chip 423 and the rewiring layer 104 includes: the connecting line in the back bridge chip 423 is electrically connected to a part of the second wiring 103, and the back bridge chip 423 together with a part of the second wiring 103 interconnects the adjacent chip modules 20.

[0082] In one embodiment, the chip module 20 includes: a substrate 200, a plurality of semiconductor chips 201 and a plastic encapsulation layer 208, wherein the substrate 200 includes a relative front and back side, the substrate 200 has a connection structure 205, the back side of the substrate 200 has an external terminal 207, the external terminal 207 is electrically connected to the connection structure 205 and is electrically connected to a portion of the first wiring 102 and a portion of the second wiring 103, a plurality of the semiconductor chips 201 are mounted on the front side of the substrate 200, the semiconductor chip 200 is electrically connected to the connection structure 205, and the plastic encapsulation layer 208 is located on the front side of the substrate 200 and covers a plurality of the semiconductor chips 201.

[0083] In one embodiment, the substrate 200 is a silicon substrate, a glass substrate or a rewiring substrate.

[0084] In one embodiment, reference Figure 4 When the substrate 200 is a rewiring substrate, a second bridge chip 210 is further embedded in the rewiring substrate, and the second bridge chip 210 is electrically connected to a part of the connection structure 205 in the rewiring substrate.

[0085] In one embodiment, the corresponding substrates 200 in at least two adjacent chip modules 20 in the system-in-package structure are of the same type or different types.

[0086] In one embodiment, the corresponding substrates 200 in at least two adjacent chip modules 20 in the system-level package structure are of the same type, including: the corresponding substrates 200 in at least two adjacent chip modules 20 in the system-level package structure are both silicon substrates (refer to Figure 2 ); or the corresponding substrates 200 in at least two adjacent chip modules 20 in the system-level package structure are both glass substrates (reference Figure 2 ); or the corresponding substrates 200 in at least two adjacent chip modules 20 in the system-level package structure are all rewiring substrates (without embedded bridge chips) (reference Figure 3 ), or the corresponding substrates 200 in at least two adjacent chip modules 20 in the system-level package structure are all rewiring substrates embedded with the second bridge chip 210 (refer to Figure 3 ).

[0087] In another embodiment, the corresponding substrates 200 in at least two adjacent chip modules 20 in the system-level packaging structure are of different types, including: one type of the corresponding substrates 200 in at least two adjacent chip modules 20 in the system-level packaging structure is a silicon substrate, and the other type is a glass substrate; or one type of the corresponding substrates 200 in at least two adjacent chip modules 200 in the system-level packaging structure is a silicon substrate, and the other type is a rewiring substrate (refer to Figure 5 ); or the corresponding substrate 200 types in at least two adjacent chip modules 20 in the system-level package structure are one type of glass substrate and the other type of rewiring substrate (reference Figure 5 ); or the corresponding substrate 200 types in at least two adjacent chip modules 200 in the system-level package structure are one type of rewiring substrate (without embedded bridge chip), and the other type is a rewiring substrate embedded with a second bridge chip 210 (reference Figure 6 ); or the corresponding substrate 200 types in at least two adjacent chip modules 200 in the system-level package structure are one type of silicon substrate or glass substrate, and the other type is a rewiring substrate embedded with a second bridge chip 210 (reference Figure 7 ).

[0088] In one embodiment, reference Figure 8-Figure 10 , further comprising: mounting a first bridge structure 421 on the surface of the rewiring layer 104 at the edge of the chip module 20, wherein the first bridge structure 421 is used to interconnect adjacent chip modules 20; mounting a second bridge structure 422 on the surface of the rewiring layer 104 at the corner of the chip module 20, wherein the second bridge structure 422 is used to interconnect adjacent chip modules 20 around the corner; referring to Figure 11-Figure 12 , edge dummy devices 301 of different sizes are mounted on the upper surface and / or lower surface of the edge region 12 of the redistribution layer 104 outside the chip module 20 array 11.

[0089] Although the present application has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present application. Any technical personnel in this field can use the methods and technical contents disclosed above to make possible changes and modifications to the technical solution of the present application without departing from the spirit and scope of the present application. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are within the protection scope of the technical solution of the present application.

Claims

1. A wafer-scale system-level packaging structure, characterized in that: include: a rewiring layer, the rewiring layer comprising an upper surface and a lower surface opposite to each other; A plurality of chip modules, wherein the plurality of chip modules are mounted on the upper surface of the rewiring layer and are electrically connected to the rewiring layer; A back bridge chip, the back bridge chip is mounted on the lower surface of the rewiring layer and is electrically connected to the rewiring layer, and the back bridge chip is used to interconnect adjacent chip modules; The upper surface of the rewiring layer is covered with a first plastic packaging layer of the chip module, and the first plastic packaging layer exposes the upper surface of the chip module.

2. The wafer-scale system-in-package structure according to claim 1, wherein: The rewiring layer includes a passivation layer and a plurality of discrete first wirings and a plurality of discrete second wirings located in the passivation layer; The plurality of chip modules are electrically connected to the redistribution layer, including: the chip module is electrically connected to a portion of the first wiring and a portion of the second wiring.

3. The wafer-scale system-in-package structure according to claim 2, wherein: The backside bridge chip includes a substrate and a connection circuit located on the substrate; The electrical connection between the back bridge chip and the rewiring layer includes: the connection line in the back bridge chip is electrically connected to a part of the second wiring, and the back bridge chip and a part of the second wiring interconnect the adjacent chip modules.

4. The wafer-scale system-in-package structure according to claim 2, wherein: The chip module includes: a substrate, a plurality of semiconductor chips and a plastic encapsulation layer, wherein the substrate includes a front side and a back side opposite to each other, the substrate has a connection structure, the back side of the substrate has an external terminal, the external terminal is electrically connected to the connection structure and to part of the first wiring and part of the second wiring, a plurality of the semiconductor chips are mounted on the front side of the substrate, the semiconductor chips are electrically connected to the connection structure, and the plastic encapsulation layer is located on the front side of the substrate and encapsulates the plurality of the semiconductor chips.

5. The wafer-scale system-in-package structure according to claim 4, characterized in that: The substrate is a silicon substrate, a glass substrate or a rewiring substrate.

6. The wafer-scale system-in-package structure according to claim 5, wherein: When the substrate is a rewiring substrate, a second bridge chip is further embedded in the rewiring substrate, and the second bridge chip is electrically connected to a part of the connection structure in the rewiring substrate.

7. The wafer-scale system-in-package structure according to claim 5, wherein: The corresponding substrates in at least two adjacent chip modules in the system-level package structure are of the same type or different types.

8. The wafer-scale system-in-package structure according to claim 7, wherein: The corresponding substrates in at least two adjacent chip modules in the system-level packaging structure are of the same type, including: the corresponding substrates in at least two adjacent chip modules in the system-level packaging structure are all silicon substrates; or the corresponding substrates in at least two adjacent chip modules in the system-level packaging structure are all glass substrates; or the corresponding substrates in at least two adjacent chip modules in the system-level packaging structure are all rewiring substrates.

9. The wafer-scale system-in-package structure according to claim 7, wherein: The different types of corresponding substrates in at least two adjacent chip modules in the system-level packaging structure include: one type of corresponding substrates in at least two adjacent chip modules in the system-level packaging structure is a silicon substrate, and the other type is a glass substrate; or one type of corresponding substrates in at least two adjacent chip modules in the system-level packaging structure is a silicon substrate, and the other type is a redistribution substrate; or one type of corresponding substrates in at least two adjacent chip modules in the system-level packaging structure is a glass substrate, and the other type is a redistribution substrate.

10. The wafer-scale system-in-package structure according to claim 5, wherein: The connection structure is one or more of a metal layer, a connection plug, a through-hole connection structure, and a via connection structure.

11. The wafer-scale system-in-package structure according to claim 2, wherein: Also includes: A first bridge structure mounted on the upper surface of the rewiring layer at the edge of the chip module, the first bridge structure being used to interconnect adjacent chip modules; A second bridge structure mounted on the upper surface of the rewiring layer of the chip module corner head, the second bridge structure is used to interconnect the adjacent chip modules around the corner head; Edge dummy devices of different sizes are mounted on the upper surface and / or lower surface of the edge area of ​​the rewiring layer outside the chip module array.

12. The wafer-scale system-in-package structure according to claim 11, wherein: The rewiring layer also includes a plurality of discrete third wirings located in the passivation layer, and the first bridging structure is electrically connected to the adjacent chip modules through the third wirings; the first bridging structure includes a first circuit layer and a first supporting layer located on the upper surface of the first circuit layer, the first circuit layer includes a first dielectric layer, a first circuit located in the first dielectric layer, and a first welding protrusion protruding from the lower surface of the first dielectric layer and electrically connected to the first circuit, when the first bridging structure is mounted on the rewiring layer, the first welding protrusion is electrically connected to the corresponding third wirings in the rewiring layer, and the first bridging structure together with the third wirings in the rewiring layer interconnect the adjacent chip modules.

13. The wafer-scale system-in-package structure according to claim 12, wherein: The rewiring layer also includes a plurality of discrete fourth wirings located in the passivation layer, and the second bridging structure is electrically connected to the adjacent chip modules through the fourth wirings; the second bridging structure includes a second circuit layer and a second supporting layer located on the upper surface of the second circuit layer, the second circuit layer includes a second dielectric layer, a second circuit located in the second dielectric layer, and a second welding protrusion protruding on the lower surface of the second dielectric layer and electrically connected to the second circuit, when the second bridging structure is mounted on the rewiring layer, the second welding protrusion is electrically connected to the corresponding fourth wiring in the rewiring layer, and the second bridging structure together with the fourth wiring in the rewiring layer interconnects the adjacent chip modules around the corner head.

14. The wafer-scale system-in-package structure according to claim 11, wherein: The edge dummy device is one or more of a passive device, a heat dissipation discrete component or a dummy piece.

15. The wafer-scale system-in-package structure according to claim 2 or 11, characterized in that: Also includes: a plurality of discrete metal bumps located on the lower surface of the rewiring layer, the metal bumps being electrically connected to corresponding first wirings; A second plastic encapsulation layer is located on the lower surface of the rewiring layer and covers the metal bumps and the back bridge chip, and the second plastic encapsulation layer exposes the lower surface of the metal bumps and the back bridge structure.

16. The wafer-scale system-in-package structure according to claim 15, wherein: Also includes: A power supply module is mounted on the lower surface of the second plastic packaging layer and electrically connected to the metal bump, and the power supply module supplies power to at least two adjacent functional sub-modules on the upper surface of the silicon substrate.

17. The wafer-scale system-in-package structure according to claim 2 or 11, characterized in that: Also includes: a plurality of discrete metal bumps located on the lower surface of the rewiring layer, the metal bumps being electrically connected to corresponding first wirings; A power supply module mounted on the lower surface of the metal bump; a second plastic packaging layer located on the lower surface of the rewiring layer and covering the metal bump, the power supply module and the back bridge chip, the second plastic packaging layer exposing the lower surface of the power supply module.

18. A method for forming a wafer-scale system-level packaging structure, characterized in that: include: forming a rewiring layer, the rewiring layer comprising opposing upper and lower surfaces; Providing a plurality of chip modules, mounting the plurality of chip modules on the upper surface of the rewiring layer and electrically connecting the plurality of chip modules to the rewiring layer; Providing a backside bridge chip, mounting the backside bridge chip on the lower surface of the rewiring layer and electrically connecting the backside bridge chip to the rewiring layer, wherein the backside bridge chip is used to interconnect adjacent chip modules; A first plastic packaging layer of the chip module is coated on the upper surface of the rewiring layer, and the first plastic packaging layer exposes the upper surface of the chip module.

19. The method for forming a wafer-scale system-in-package structure according to claim 18, wherein: The process of forming the rewiring layer includes: providing a carrier board; forming a rewiring layer on the carrier board, wherein the rewiring layer includes a passivation layer and a plurality of discrete first wirings and a plurality of discrete second wirings located in the passivation layer; after forming the first plastic encapsulation layer, removing the carrier board and mounting the back bridge chip; the plurality of chip modules are electrically connected to the rewiring layer, including: the chip module is electrically connected to part of the first wiring and part of the second wiring.

20. The method for forming a wafer-scale system-in-package structure according to claim 19, wherein: The backside bridge chip includes a substrate and a connection circuit located on the substrate; The electrical connection between the back bridge chip and the rewiring layer includes: the connection line in the back bridge chip is electrically connected to a part of the second wiring, and the back bridge chip and a part of the second wiring interconnect the adjacent chip modules.

21. The method for forming a wafer-scale system-in-package structure according to claim 19, wherein: The chip module includes: a substrate, a plurality of semiconductor chips and a plastic encapsulation layer, wherein the substrate includes a front side and a back side opposite to each other, the substrate has a connection structure, the back side of the substrate has an external terminal, the external terminal is electrically connected to the connection structure and to part of the first wiring and part of the second wiring, a plurality of the semiconductor chips are mounted on the front side of the substrate, the semiconductor chips are electrically connected to the connection structure, and the plastic encapsulation layer is located on the front side of the substrate and encapsulates the plurality of the semiconductor chips.

22. The method for forming a wafer-scale system-in-package structure according to claim 21, wherein: The substrate is a silicon substrate, a glass substrate or a rewiring substrate.

23. The method for forming a wafer-scale system-in-package structure according to claim 22, wherein: When the substrate is a rewiring substrate, a second bridge chip is further embedded in the rewiring substrate, and the second bridge chip is electrically connected to a part of the connection structure in the rewiring substrate.

24. The method for forming a wafer-scale system-in-package structure according to claim 22, wherein: The corresponding substrates in at least two adjacent chip modules in the system-level package structure are of the same type or different types.

25. The method for forming a wafer-scale system-in-package structure according to claim 18, wherein: Also includes: Mounting a first bridge structure on the surface of the rewiring layer at the edge of the chip module, wherein the first bridge structure is used to interconnect adjacent chip modules; Mounting a second bridge structure on the rewiring layer of the chip module corner head, wherein the second bridge structure is used to interconnect adjacent chip modules around the corner head; Edge dummy devices of different sizes are mounted on the upper surface and / or lower surface of the edge region of the rewiring layer outside the chip module array.

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