Thin film transistor and display panel
By setting stress grooves in the transparent electrode layer, the stress concentration problem caused by the shrinkage of the LTPS display panel film is solved, and the yield and reliability of the display panel are improved.
Patent Information
- Application Number
- CN202411772264.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-04
- Publication Date
- 2025-03-28
AI Technical Summary
The film layer stacking of the LTPS display panel at the overlap of the SD line and the Gate line causes the film to shrink and the stress is concentrated, which easily leads to the film peeling, affecting the yield and reliability of the display panel.
Stress grooves are provided in the transparent electrode layer, and the stress grooves correspond to the position of the gate layer to disperse the stress and avoid excessive concentration in key areas.
By dispersing stress, avoiding film peeling, improving the yield and reliability of the display panel, protecting the structural integrity and stable electrical performance of the transistor.
Smart Images
Figure CN119730613A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of display panels, and in particular to a thin film transistor and a display panel. Background Art
[0002] LTPS is the abbreviation of Low-Temperature Polycrystalline Silicon, which is a high-performance thin-film transistor technology widely used in display technologies such as liquid crystal displays (LCDs) and organic light-emitting diodes (OLEDs). LTPS technology has the advantages of fast response, low power consumption, high resolution, bright colors and reduced eye fatigue.
[0003] The current technical route of LTPS is mostly Top-Vcom. In the Top-Vcom design, the Vcom trench in the pixel area forms an electric field with the Pixel-ITO, and the triode TFT uses metal layer shading technology to reduce leakage current. This design helps to improve the performance and reliability of the display panel. However, because the current LTPS products have the highest film stack at the intersection of the SD line and the Gate line, Vcom-ITO will cause the film to shrink after annealing, and the stress at the highest point of the film layer is relatively concentrated, which is easy to cause the film to peel off, affecting the improvement of the yield and reliability of the display panel.
[0004] Therefore, providing a thin film transistor and a display panel that can improve the yield and reliability of a display panel has become a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention
[0005] Embodiments of the present application provide a thin film transistor and a display panel.
[0006] The embodiment of the present application provides a thin film transistor, including a gate layer, a conductive layer, a source-drain electrode layer, a planarization layer, a passivation layer, and a transparent electrode layer, wherein the gate layer has a first surface and a second surface arranged opposite to each other; the conductive layer is arranged on the first surface; the source-drain electrode layer is arranged on a side of the conductive layer away from the gate transparent layer; A planarization layer is arranged on a side of the source and drain layer away from the conductive layer; a passivation layer is arranged on a side of the planarization layer away from the source and drain layer; a transparent electrode layer is arranged on a side of the passivation layer away from the planarization layer; wherein the transparent electrode layer is provided with a stress groove, and the stress groove corresponds to the position of the gate layer.
[0007] In some embodiments, the stress groove penetrates the transparent electrode layer.
[0008] In some embodiments, an insulating layer, a protective layer and a light shielding layer are also included. The insulating layer is arranged on a side of the gate layer away from the conductive layer, the protective layer is arranged on a side of the insulating layer away from the gate layer, and the light shielding layer is arranged on a side of the protective layer away from the insulating layer.
[0009] In some embodiments, a first strengthening coating is disposed on an edge of the stress groove.
[0010] In some embodiments, a second strengthening coating is disposed on a side of the transparent electrode layer away from the passivation layer.
[0011] In some embodiments, the edge of the stress groove has a stepped surface.
[0012] In some embodiments, the stress groove includes at least two sub-grooves.
[0013] In some embodiments, the stress groove includes a first sub-groove and a second sub-groove, the second sub-groove surrounds the outside of the first sub-groove, and the first sub-groove is connected to the second sub-groove.
[0014] In some embodiments, the second sub-groove is filled with a flexible material layer.
[0015] An embodiment of the present application further provides a display panel, comprising the thin film transistor described in the above embodiment.
[0016] The embodiment of the application provides a thin film transistor, including a gate layer, a conductive layer, a source-drain electrode layer, a planarization layer, a passivation layer, and a transparent electrode layer, wherein the gate layer has a first surface and a second surface that are arranged opposite to each other; the conductive layer is arranged on the first surface; the source-drain electrode layer is arranged on a side of the conductive layer away from the gate transparent layer; The planarization layer is arranged on the side of the source-drain electrode layer away from the conductive layer; the passivation layer is arranged on the side of the planarization layer away from the source-drain electrode layer; the transparent electrode layer is arranged on the side of the passivation layer away from the planarization layer; wherein the transparent electrode layer is provided with a stress groove, and the stress groove corresponds to the position of the gate layer. Since the transparent electrode of the present application is provided with a stress groove, and the position of the stress groove and the gate layer is such that the stress can be dispersed along the direction of the groove, the stress is prevented from being excessively concentrated in the key area corresponding to the gate layer, and the film is prevented from peeling off, thereby protecting the structural integrity of the transistor and stabilizing the electrical performance, and improving the yield and reliability of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative work.
[0018] Figure 1 A schematic diagram of the structure of a thin film transistor provided in an embodiment of the present application.
[0019] Figure 2 Another schematic diagram of the structure of the thin film transistor provided in an embodiment of the present application.
[0020] Figure 3 This is another schematic diagram of the structure of a thin film transistor provided in an embodiment of the present application.
[0021] Figure 4 A schematic diagram of a stress groove structure of a thin film transistor provided in an embodiment of the present application.
[0022] Figure 5 A schematic diagram of the structure of a display panel provided in an embodiment of the present application. DETAILED DESCRIPTION
[0023] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.
[0024] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.
[0025] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0026] In the present application, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.
[0027] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the various specific processes and material examples provided by the present application, but those of ordinary skill in the art can appreciate the application of other processes and / or the use of other materials.
[0028] Embodiments of the present application provide a thin film transistor and a display panel.
[0029] See also Figure 1The embodiment of the present application provides a thin film transistor 100, comprising a gate layer 10, a conductive layer 20, a source-drain electrode layer 30, a planarization layer 40, a passivation layer 50, and a transparent electrode layer 60. The gate layer 10 has a first surface 10a and a second surface 10b arranged opposite to each other; the conductive layer 20 is arranged on the first surface 10a; the source-drain electrode layer 30 is arranged on a side of the conductive layer 20 away from the gate transparent layer; the planarization layer 40 is arranged on a side of the source-drain electrode layer 30 away from the conductive layer 20; the passivation layer 50 is arranged on a side of the planarization layer 40 away from the source-drain electrode layer 30; and the transparent electrode layer 60 is arranged on a side of the passivation layer 50 away from the planarization layer 40; wherein the transparent electrode layer 60 is provided with a stress groove 101, and the stress groove 101 corresponds to the position of the gate layer 10.
[0030] It should be noted that the gate layer 10, as a key component of the thin transistor, has a first surface 10a and a second surface 10b arranged opposite to each other. The first surface 10a is usually the upper surface of the gate layer 10, and the second surface 10b is usually the lower surface of the gate layer 10. Of course, the positions can be swapped as needed.
[0031] The gate layer 10 mainly controls the opening and closing of the current channel, just like a "valve" that regulates the flow of electrons by applying a suitable voltage signal. For example, in a semiconductor device, when a forward voltage is applied to the gate layer 10, an electric field is generated in the semiconductor channel region below it (the conductive region between the gate layer 10 and the source and drain layer 30, which is not mentioned in detail in this question but is related in principle), attracting carriers (such as electrons) to gather, thereby forming a conductive channel, so that current can pass between the source and the drain; and when a reverse voltage or zero voltage is applied, the conductive channel disappears and the current cannot be conducted. The stability of its structure and its electrical properties play a fundamental role in ensuring the normal operation of the entire thin transistor.
[0032] The gate layer 10 is usually made of metal materials with good electrical conductivity, such as polysilicon or metal (such as aluminum, copper and other alloys). The advantage of polysilicon is that it has good compatibility with semiconductor processes and can be easily patterned through micro-machining processes such as photolithography and etching to form a precise gate structure. Metal materials have lower resistance and can achieve more efficient signal transmission, but some special interface treatments are required in terms of contact with semiconductors to avoid adverse electrical effects (such as Schottky barriers that affect carrier injection). During production, polysilicon materials are deposited using processes such as chemical vapor deposition (CVD), or metal materials are deposited using physical vapor deposition (PVD), and then processed into the required shape and size through photolithography and etching processes, and precisely defined at the position of the gate layer 10.
[0033] The conductive layer 20 is arranged on the first surface 10a of the gate layer 10, and it plays an important role in connecting and conducting current. On the one hand, it can act as an intermediate conductive medium to distribute the voltage signal applied to the gate layer 10 more evenly and stably in the corresponding area, ensuring that the gate has more precise control over the electric field of the semiconductor channel below. On the other hand, it may also participate in the construction of the current transmission path inside the entire transistor, and work in conjunction with the source and drain layer 30 to ensure that the current can flow smoothly in the transistor and realize functions such as driving the subsequent circuit.
[0034] The source-drain layer 30 is arranged on the side of the conductive layer 20 away from the gate layer 10, and is the port for the current to flow in and out of the transistor. As the inflow end of the current, the source receives the carriers (electrons or holes, depending on the type of transistor, such as electrons for n-type transistors and holes for p-type transistors) provided by the external circuit, and then the carriers are transmitted to the drain through the conductive channel inside the transistor (controlled by the gate) and flow out, thereby realizing the functions of driving the external circuit or signal transmission. For example, in an integrated circuit, the source and drain electrodes of many thin transistors are interconnected to form a complex circuit network to realize various logical operations and signal processing functions.
[0035] The commonly used materials for the source and drain layer 30 are also metal materials, such as aluminum (Al), titanium (Ti) and their alloys. These metals are selected mainly because of their good electrical conductivity and the ability to form suitable ohmic contacts with semiconductor materials (usually semiconductor channels and other parts in transistor structures), ensuring that carriers can be efficiently injected and extracted between metals and semiconductors, reducing energy loss and signal distortion caused by contact resistance. In terms of manufacturing process, the metal material is generally deposited on the conductive layer 20 through a physical vapor deposition (PVD) process, and then photolithography and etching techniques are used to accurately pattern it into the shape of the source and drain according to the designed layout to determine its specific position and size in the transistor.
[0036] The planarization layer 40 is arranged on the side of the source and drain layer 30 away from the conductive layer 20, and its core function is to flatten the surface. After the previous process steps such as the source and drain layer 30, the surface of the transistor may be uneven due to the deposition, etching and other operations of each layer of materials, and the planarization layer 40 can fill these tiny grooves and protrusions, and provide a smooth and flat surface foundation for the subsequent deposition of the passivation layer 50, transparent electrode layer 60, etc. This is very important for ensuring the uniformity and stability of the subsequent layers. For example, if the surface is uneven, the passivation layer 50 may have uneven thickness during deposition, affecting its protective effect on the transistor; the transparent electrode layer 60 may also cause differences in electrode performance (such as conductivity, light transmittance, etc.) in different areas due to the uneven surface.
[0037] The planarization layer 40 is usually made of organic polymer materials, such as polyimide (PI) and other materials with good film-forming and planarization properties. These materials can be used to form the planarization layer 40 through a spin coating process, where a solution containing polyimide and other materials is dropped onto the surface of the existing source and drain electrode layer 30, and then the solution is evenly spread and dried and solidified by high-speed rotation under the action of centrifugal force, forming a flat film covering the source and drain electrode layer 30, thereby achieving the purpose of a flat surface.
[0038] The passivation layer 50 is located on the side of the planarization layer 40 away from the source and drain layer 30. It mainly protects the internal structure of the transistor from external environmental factors. If external water vapor, oxygen, impurity ions, etc. invade the interior of the transistor, they may react chemically with metal electrodes, semiconductor materials, etc., resulting in a decrease in material performance, poor electrical performance, and even failure of the transistor. For example, water vapor may corrode metal electrodes, and oxygen may affect the carrier concentration of semiconductor materials. The passivation layer 50 is like a solid "shield". With its good barrier properties, it blocks these adverse factors outside the transistor, prolongs the service life of the transistor, and improves its working stability and reliability.
[0039] Common passivation layer 50 materials include silicon nitride (Si3N4), silicon dioxide (SiO2), etc. Silicon nitride has the characteristics of high hardness, high chemical stability and good insulation, and can effectively resist the erosion of water vapor, oxygen and various chemical substances; silicon dioxide also has good insulation performance and chemical stability, and has good compatibility with other materials in some semiconductor processes. They are generally prepared by chemical vapor deposition (CVD) process, and the gas containing silicon source, nitrogen source (for silicon nitride) or oxygen source (for silicon dioxide) is chemically reacted under high temperature, certain pressure and other conditions, and the passivation layer 50 is deposited on the surface of the planarization layer 40, and the thickness of the passivation layer 50 can be accurately adjusted by controlling the process parameters to meet different protection requirements.
[0040] The transparent electrode layer 60 is arranged on the side of the passivation layer 50 away from the planarization layer 40. It has a conductive function and also needs to have good optical transparency. In many application scenarios, such as the application of thin film transistors 100 (TFT) in display panels, the transparent electrode layer 60 needs to be able to conduct current to drive pixels to emit light or control the twisting of liquid crystal molecules, etc., but it cannot significantly block the light to ensure the brightness and visibility of the display. In addition, the layer is provided with a stress groove 101, which corresponds to the position of the gate layer 10. This design has a special function, which will be explained in detail later.
[0041] Commonly used transparent electrode layer 60 materials also include transparent conductive oxides such as indium tin oxide (ITO), as well as some emerging organic conductive materials or transparent conductive systems composited with nanomaterials. ITO is widely used for its mature preparation process (such as sputtering process) and high transmittance in the visible light range and good conductivity. For organic conductive materials, etc., they may be prepared by solution processing processes (such as spin coating, inkjet printing, etc.). They have advantages in flexibility and are suitable for application in flexible electronic devices. When making the transparent electrode layer 60, it is necessary to strictly control factors such as material quality, deposition uniformity, and adhesion between the passivation layer 50 to ensure that it can stably perform the functions of conductivity and light transmission.
[0042] The stress groove 101 provided on the transparent electrode layer 60 corresponds to the position of the gate layer 10, which is mainly to alleviate the stress concentration problem generated during the operation of the transistor or when subjected to external mechanical stress (such as bending, stretching, etc. of the flexible device). When the environment in which the transistor is located changes, such as temperature changes or external forces are applied, stress will be generated between different material layers due to differences in physical properties such as thermal expansion coefficients. If there is no stress groove 101 to disperse these stresses, stress may accumulate excessively in certain local areas, causing cracks, delamination, and even electrode layer fractures in the material, affecting the performance and life of the transistor. The presence of the stress groove 101 allows the stress to be dispersed along the direction of the groove, avoiding excessive concentration of stress in the key area corresponding to the gate layer 10, thereby protecting the structural integrity and electrical performance stability of the transistor.
[0043] Through the effective relief of stress by the stress groove 101, the transistor can operate more stably in various complex working environments and use conditions. For example, in a flexible display device, a thin transistor needs to continuously withstand stress changes as the display screen bends. With the design of the stress groove 101, the transparent electrode layer 60 can better maintain its conductive and light-transmitting properties, thereby ensuring the normal operation of the entire display pixel, improving the stability and reliability of the display effect, and also extending the service life of the transistor and the entire device. The various components of this thin transistor cooperate with each other, from current control, conduction to surface flatness, protection, and stress response, and work together to ensure that the transistor can stably and reliably perform its functions in different application scenarios.
[0044] In some embodiments, the stress groove 101 penetrates the transparent electrode layer 60 .
[0045] It should be noted that when the stress groove 101 penetrates the transparent electrode layer 60, the stress can be released more directly and efficiently. When the transistor is subjected to external stress (such as during the bending process of the flexible display device), the stress can be quickly transmitted from one side of the transparent electrode layer 60 to the other side through the penetrating stress groove 101. This through-type design is like opening a channel directly in a blocked pipe, so that the internal pressure (stress) can be released without hindrance. Compared with the non-penetrating stress groove 101, it can avoid the accumulation of stress inside the transparent electrode layer 60, greatly reducing the risk of the electrode layer breaking or peeling off from other layers due to stress concentration.
[0046] In some embodiments, an insulating layer 70, a protective layer 80 and a light shielding layer 90 are also included. The insulating layer 70 is arranged on a side of the gate layer 10 away from the conductive layer 20, the protective layer 80 is arranged on a side of the insulating layer 70 away from the gate layer 10, and the light shielding layer 90 is arranged on a side of the protective layer 80 away from the insulating layer 70.
[0047] It should be noted that the insulating layer 70 is located on the side of the gate layer 10 away from the conductive layer 20, and its main function is to provide electrical insulation to prevent current from leaking on an undesired path. During the operation of the thin transistor, the voltage applied to the gate layer 10 is used to control the current channel between the source and the drain. If there is no good insulating layer 70, the voltage of the gate layer 10 may leak through other paths (such as with the substrate or adjacent non-related circuits), causing the transistor to fail to work properly. For example, in an integrated circuit, many transistors are closely arranged, and the insulating layer 70 can prevent the gate signals between adjacent transistors from interfering with each other, ensuring that the control signal of each transistor is independent and accurate.
[0048] The protective layer 80 is arranged on the side of the insulating layer 70 away from the gate layer 10, and its main purpose is to protect the insulating layer 70 and the underlying gate layer 10 from physical damage and chemical corrosion. During the manufacture, packaging and use of thin transistors, they may be affected by various external factors, such as mechanical friction, particle collision, chemical solution erosion, etc. The protective layer 80 is like a tough shell that can resist these adverse factors and extend the service life of the transistor. For example, in the chip manufacturing process, multiple process steps such as photolithography and etching are required. These processes may generate tiny particles or mechanical stress. The protective layer 80 can prevent these factors from damaging the internal insulating layer 70 and the gate layer 10.
[0049] The light shielding layer 90 is located on the side of the protective layer 80 away from the insulating layer 70. Its main function is to control the propagation of light and prevent the light from having an adverse effect on the internal structure of the transistor. In some application scenarios, such as in a display panel, external light may interfere with the normal operation of the transistor, or cause an internal photoelectric effect, affecting the electrical performance. The light shielding layer 90 can effectively block these lights to ensure that the transistor operates in a relatively stable optical environment. For example, in an organic light emitting diode (OLED) display panel, the light shielding layer 90 can prevent external light from irradiating the transistor, avoiding the generation of additional photogenerated carriers, thereby improving the control accuracy of the display pixels.
[0050] See also Figure 2 In some embodiments, a first strengthening coating 102 is disposed on the edge of the stress groove 101 .
[0051] It should be noted that when the stress groove 101 penetrates the transparent electrode layer 60, the edge of the stress groove 101 is the area where stress concentration is most likely to occur. The first strengthening coating 102 can further disperse the stress at this position. It is like adding a buffer zone at the edge of the stress groove 101. When the stress is transmitted to the edge, the coating material can diffuse the stress to a wider area through its own elasticity or special microstructure. For example, the coating material may have a sponge-like microporous structure. When stress acts, these small holes can deform to absorb and disperse stress, thereby reducing the stress peak at the edge and reducing the risk of material damage due to stress concentration.
[0052] During the use of the transistor, especially when it is affected by mechanical deformation (such as in a flexible device) or temperature changes, tiny cracks may be generated at the edge of the stress groove 101. The first strengthening coating 102 can effectively prevent the expansion of these cracks. It prevents the cracks from further extending to the main part of the transparent electrode layer 60 by filling potential cracks or forming chemical bonds with the crack surface. This is like applying a layer of strong glue to the cracks in the wall. The glue can stick the cracks together and prevent the cracks from continuing to expand, thereby protecting the integrity of the transparent electrode layer 60.
[0053] The material of the first strengthening coating 102 generally has high toughness. For example, some special organic-inorganic hybrid materials, the organic part of which provides good flexibility and can withstand large deformation without breaking, and the inorganic part gives the material a certain hardness and strength, so that it can effectively resist external forces. In addition, some rubber-like materials can also be used as coating materials. They have excellent elasticity and toughness, can undergo reversible elastic deformation under stress, and absorb and buffer stress.
[0054] In some embodiments, a second strengthening coating 103 is disposed on a side of the transparent electrode layer 60 away from the passivation layer 50 .
[0055] It should be noted that the second strengthening coating 103 is located on the side of the transparent electrode layer 60 away from the passivation layer 50, which makes it the first line of defense for the transparent electrode layer 60 to resist external physical damage. In practical applications, such as in a display panel or other electronic devices, the transparent electrode layer 60 may be scratched, rubbed or hit by tiny particles from external objects. At the same time, it prevents the transparent electrode layer 60 from being damaged from the stress groove 101 when the stress is diffused.
[0056] See also Figure 3 In some embodiments, the edge of the stress groove 101 has a stepped surface 104 .
[0057] It should be noted that the step surface 104 design at the edge of the stress groove 101 can disperse the stress in multiple directions. When the stress is transmitted to the edge of the stress groove 101, the step surface 104 is like a buffer structure with multiple levels. Compared with ordinary smooth edges, the step surface 104 can guide the stress to propagate along different planes instead of concentrating on one plane. For example, in the direction perpendicular to the transparent electrode layer 60, the stress can be gradually released through the different levels of the steps to avoid excessive accumulation of stress on a plane at a certain height.
[0058] In some embodiments, the stress groove 101 includes at least two sub-grooves.
[0059] It is understandable that the stress groove 101 may include two, three or even more sub-grooves, so as to disperse the stress.
[0060] For details, please refer to Figure 4 The stress groove 101 includes a first sub-groove 101a and a second sub-groove 101b. The second sub-groove 101b surrounds the outside of the first sub-groove 101a, and the first sub-groove 101a is connected to the second sub-groove 101b.
[0061] It should be noted that the structure composed of the first sub-groove 101a and the second sub-groove 101b forms a graded stress dispersion system. When stress acts on the transparent electrode layer 60 and is transmitted to the stress groove 101 area, the stress will first enter the first sub-groove 101a. The first sub-groove 101a, as the part that directly receives the stress, begins to initially disperse the stress. Just like water flows into the main river first. Then, since the second sub-groove 101b surrounds the outside of the first sub-groove 101a and is connected to it, part of the stress can be diverted from the first sub-groove 101a to the second sub-groove 101b to achieve secondary dispersion. This allows the stress to be more evenly distributed throughout the stress groove 101 and its surrounding areas, reducing the possibility of excessive peak values of stress locally, and effectively protecting the transparent electrode layer 60 and the entire transistor structure.
[0062] In some embodiments, the second sub-groove 101 b is filled with a flexible material layer 105 .
[0063] It should be noted that when external stress acts on the transparent electrode layer 60 and is transmitted to the stress groove 101 area, the flexible material layer 105 filled in the second sub-groove 101b can play an excellent buffering role. Flexible materials usually have a low elastic modulus, which means that they can easily undergo elastic deformation when subjected to stress. For example, similar to a sponge that absorbs external force through its own deformation when squeezed, the flexible material layer 105 will also change its shape accordingly under the action of stress, converting part of the stress into its own elastic potential energy and storing it, thereby effectively reducing the intensity of stress, avoiding stress from directly impacting the electrode layer structure or causing excessive concentration at the edge of the stress groove 101, and greatly reducing the risk of material damage (such as electrode layer rupture, delamination, etc.) caused by stress concentration.
[0064] See also Figure 5 Another embodiment of the present application further provides a thin film transistor 1000, including the thin film transistor 100 described in the above embodiment. Since the thin film transistor 100 has been described in detail in the above embodiment, the thin film transistor 100 in the above embodiment will not be described in detail in the present application embodiment.
[0065] The above is a detailed introduction to the thin film transistor and display panel provided in the embodiments of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the present application. At the same time, for those skilled in the art, according to the ideas of the present application, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as limiting the present application.
Claims
1. A thin film transistor, characterized in that: include: The gate layer has a first surface and a second surface that are oppositely disposed; A conductive layer is disposed on the first surface; A source-drain electrode layer, arranged on a side of the conductive layer away from the gate layer; A planarization layer, disposed on a side of the source and drain electrode layer away from the conductive layer; A passivation layer, disposed on a side of the planarization layer away from the source and drain electrode layers; A transparent electrode layer is arranged on a side of the passivation layer away from the planarization layer; Wherein, the transparent electrode layer is provided with a stress groove, and the position of the stress groove corresponds to the position of the gate layer.
2. The thin film transistor according to claim 1, characterized in that: The stress groove penetrates the transparent electrode layer.
3. The thin film transistor according to claim 1, characterized in that: It also includes an insulating layer, a protective layer and a light shielding layer. The insulating layer is arranged on a side of the gate layer away from the conductive layer, the protective layer is arranged on a side of the insulating layer away from the gate layer, and the light shielding layer is arranged on a side of the protective layer away from the insulating layer.
4. The thin film transistor according to claim 1, characterized in that: A first strengthening coating is disposed on the edge of the stress groove.
5. The thin film transistor according to claim 4, characterized in that: A second strengthening coating is disposed on a side of the transparent electrode layer away from the passivation layer.
6. The thin film transistor according to claim 1, characterized in that: The edge of the stress groove has a stepped surface.
7. The thin film transistor according to claim 1, characterized in that: The stress groove includes at least two sub-grooves.
8. The thin film transistor according to claim 7, characterized in that: The stress groove includes a first sub-groove and a second sub-groove, the second sub-groove surrounds the outside of the first sub-groove, and the first sub-groove is connected to the second sub-groove.
9. The thin film transistor according to claim 8, characterized in that: The second sub-groove is filled with a flexible material layer.
10. A display panel, characterized in that: The invention comprises a thin film transistor as claimed in any one of claims 1 to 9.