Voltage switching in power management integrated circuit

Abstract

Voltage switching in a power management integrated circuit (PMIC) is provided. The PMIC needs to increase or decrease a modulation voltage from a current voltage level in a current one of a plurality of time intervals to a future voltage level in an upcoming one of the time intervals at very short switching intervals. Herein, the PMIC determines whether to change the modulation voltage based on a first voltage transition scheme or a second voltage transition scheme, and dynamically switches between the first voltage transition scheme and the second voltage transition scheme from one time interval to another. By employing the first voltage transition scheme or the second voltage transition scheme, the PMIC can switch the modulation voltage in a timely manner. Moreover, by opportunistically employing the first voltage transition scheme at any possible time, the PMIC may also help reduce potential power losses associated with switching the modulated voltage.

Description

[0001] Related Applications

[0002] This application claims the benefit of U.S. Provisional Patent Application Serial No. 63 / 401,785 filed on August 29, 2022 and the benefit of U.S. Provisional Patent Application Serial No. 63 / 480,796 filed on January 20, 2023, the disclosures of which are hereby incorporated by reference in their entirety. Technical Field

[0003] The technology of the present disclosure generally relates to power management integrated circuits (PMICs). Background Art

[0004] Fifth Generation (5G) New Radio (NR) (5G-NR) is widely considered to be the next generation of wireless communication technology beyond the current third generation (3G) and fourth generation (4G) technologies. In this regard, wireless communication devices capable of supporting 5G-NR wireless communication technology are expected to achieve higher data rates, improved coverage, enhanced signal conduction efficiency, and reduced latency.

[0005] Downlink and uplink transmission in 5G-NR systems are widely based on Orthogonal Frequency Division Multiplexing (OFDM) technology. In OFDM-based systems, physical radio resources are divided into multiple subcarriers in the frequency domain and multiple OFDM symbols in the time domain. The subcarriers are separated from each other orthogonally by a subcarrier spacing (SCS). OFDM symbols are separated by a cyclic prefix (CP), which acts as a guard band to help overcome inter-symbol interference (ISI) between OFDM symbols.

[0006] Radio frequency (RF) signals transmitted in OFDM-based systems are typically modulated into multiple subcarriers in the frequency domain and multiple OFDM symbols in the time domain. The multiple subcarriers occupied by the RF signal collectively define the modulation bandwidth of the RF signal. On the other hand, the multiple OFDM symbols define multiple time intervals during which the RF signal is transmitted. In 5G-NR systems, RF signals are typically modulated with a high modulation bandwidth of more than 200 MHz.

[0007] The duration of an OFDM symbol depends on the SCS and the modulation bandwidth. The following table (Table 1) provides some OFDM symbol durations defined by the 3G Partnership Project (3GPP) standards for various SCS and modulation bandwidths. It is worth noting that the higher the modulation bandwidth, the shorter the OFDM symbol duration will be. For example, when the SCS is 120KHz and the modulation bandwidth is 400MHz, the OFDM symbol duration is 8.93μs.

[0008] Table 1

[0009]

[0010] In 5G-NR systems, RF signals can be modulated with time-varying power that changes from one OFDM symbol to another. In this regard, a power amplifier circuit is required to amplify the RF signal to a certain power level within the duration of each OFDM symbol. Such inter-symbol power variations present unique challenges to the power management integrated circuit (PMIC), as the PMIC must be able to adapt the modulation voltage supplied to the power amplifier circuit within the CP of each OFDM symbol to help avoid distortion (e.g., amplitude clipping) in the RF signal. Summary of the invention

[0011] Embodiments of the present disclosure relate to voltage switching in a power management integrated circuit (PMIC). The PMIC is required to increase or decrease a modulation voltage from a current voltage level in a current time interval in a plurality of time intervals to a future voltage level in an upcoming time interval in the time interval at a very short switching interval (e.g., <20 nanoseconds). In this document, the PMIC may determine whether to change the modulation voltage based on a first voltage transition scheme or a second voltage transition scheme, and dynamically switch between the first voltage transition scheme and the second voltage transition scheme from one time interval to another. By changing the modulation voltage based on the first voltage transition scheme or the second voltage transition scheme, the PMIC may switch the modulation voltage from the current voltage level to the future voltage level in a timely manner. In addition, by opportunistically employing the first voltage transition scheme whenever possible, the PMIC may also help reduce potential power losses associated with switching the modulation voltage.

[0012] In one aspect, a PMIC is provided. The PMIC includes a voltage output that outputs a modulation voltage to a power amplifier circuit to amplify an RF signal modulated in a plurality of time intervals. The PMIC also includes a voltage processing circuit. The voltage processing circuit is configured to generate a modulation voltage at a corresponding voltage level in each of a plurality of time intervals. The PMIC also includes a control circuit. The control circuit is configured to receive a modulated target voltage, the modulated target voltage indicating that the modulation voltage needs to be transitioned from a current voltage level in a current time interval among a plurality of time intervals to a future voltage level in an upcoming time interval immediately after the current time interval among a plurality of time intervals. The control circuit is also configured to control the voltage processing circuit to change the modulation voltage from the current voltage level to the future voltage level based on one of a first voltage transition scheme and a second voltage transition scheme.

[0013] Those skilled in the art will appreciate the scope of the present disclosure and become aware of additional aspects thereof after reading the following detailed description of the preferred embodiments and the associated drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0015] Figure 1 is a schematic diagram of an exemplary wireless communication circuit in which a power management integrated circuit (PMIC) is configured to change a modulation voltage based on a first voltage transition scheme or a second voltage transition scheme according to an embodiment of the present disclosure;

[0016] Figure 2A It can be done by Figure 1 A flowchart of an exemplary process employed by a PMIC in order to change a modulation voltage;

[0017] Figure 2B is a flow chart of an exemplary process, wherein Figure 1 The PMIC in the embodiment may determine whether to change the modulation voltage based on the first voltage conversion scheme or the second voltage conversion scheme;

[0018] Figure 3 Yes Figure 1 An exemplary illustrated timing diagram of a PMIC in accordance with an embodiment of the present disclosure configured to increase a modulation voltage from a present voltage level to a future voltage level based on a first voltage transition scheme;

[0019] Figure 4 Yes Figure 1 An exemplary illustrated timing diagram of a PMIC in accordance with an embodiment of the present disclosure configured to reduce a modulation voltage from a present voltage level to a future voltage level based on a first voltage transition scheme;

[0020] Figure 5 Yes Figure 1 An exemplary illustrated timing diagram of a PMIC in accordance with an embodiment of the present disclosure configured to increase a modulation voltage from a current voltage level to a future voltage level based on a second voltage transition scheme;

[0021] Figure 6 Yes Figure 1 An exemplary illustrated timing diagram of a PMIC in accordance with an embodiment of the present disclosure configured to reduce a modulation voltage from a present voltage level to a future voltage level based on a second voltage transition scheme;

[0022] Figure 7 Yes Figure 1An exemplary illustrated timing diagram of a PMIC in , the PMIC configured according to another embodiment of the present disclosure to reduce a modulation voltage from a current voltage level to a future voltage level based on a second voltage transition scheme; and

[0023] Figure 8 is a schematic diagram of an exemplary user element, in which a Figure 1 Wireless communication circuit. DETAILED DESCRIPTION

[0024] The embodiments set forth below represent information necessary to enable those skilled in the art to practice the embodiments and to illustrate the best mode for practicing the embodiments. After reading the following description with reference to the accompanying drawings, those skilled in the art will understand the concepts of the present disclosure and will appreciate the applications of these concepts not specifically set forth herein. It should be understood that these concepts and applications are within the scope of the present disclosure and the appended claims.

[0025] It will be appreciated that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish different elements. For example, without departing from the scope of the present disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more items in the associated listed items.

[0026] It should be understood that when an element such as a layer, a region or a substrate is referred to as being "on another element" or "extending onto another element", it may be directly on another element or directly extending onto another element, or there may also be an intermediate element. On the contrary, when an element is referred to as being "directly on another element" or "extending directly onto another element", there is no intermediate element. Similarly, it should be understood that when an element such as a layer, a region or a substrate is referred to as being "above another element" or "extending above another element", it may be directly above another element or directly extending above another element, or there may also be an intermediate element. On the contrary, when an element is referred to as being "directly above another element" or "extending directly above another element", there is no intermediate element. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to another element, or there may be an intermediate element. On the contrary, when an element is referred to as being "directly connected" or "directly coupled" to another element, there is no intermediate element.

[0027] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe one element, layer or region's relationship to another element, layer or region as illustrated in the figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0028] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are also intended to include the plural forms. It should also be understood that when used herein, the terms "comprises", "comprising", "includes", and / or "including" specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0029] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that, unless expressly defined herein, the terms used herein should be interpreted as having a meaning consistent with their meaning in the context of this specification and the relevant art, and will not be interpreted in an idealized or overly formal sense.

[0030] Embodiments of the present disclosure relate to voltage switching in a power management integrated circuit (PMIC). The PMIC is required to increase or decrease a modulation voltage from a current voltage level in a current time interval in a plurality of time intervals to a future voltage level in an upcoming time interval in the time interval at a very short switching interval (e.g., <20 nanoseconds). In this document, the PMIC may determine whether to change the modulation voltage based on a first voltage transition scheme or a second voltage transition scheme, and dynamically switch between the first voltage transition scheme and the second voltage transition scheme from one time interval to another. By changing the modulation voltage based on the first voltage transition scheme or the second voltage transition scheme, the PMIC may switch the modulation voltage from the current voltage level to the future voltage level in a timely manner. In addition, by opportunistically employing the first voltage transition scheme whenever possible, the PMIC may also help reduce potential power losses associated with switching the modulation voltage.

[0031] in this regard, Figure 1is a schematic diagram of an exemplary wireless communication circuit 10, wherein the PMIC 12 is configured to change the modulation voltage V based on the first voltage conversion scheme or the second voltage conversion scheme according to an embodiment of the present disclosure. CC The PMIC 12 includes a voltage output 14 that modulates the voltage V CC The power amplifier circuit 16 is configured to output the power amplifier circuit 16 based on the modulation voltage V CC A radio frequency (RF) signal 18 is amplified.

[0032] The RF signal 18 that may be generated by the transceiver circuit 20 is modulated in a plurality of time intervals. For reference and illustration, a time interval is hereinafter referred to as a pair of adjacent time intervals S N-1 , S N Indicates that S N Immediately after S N-1 It will be appreciated that the RF signal 18 may be modulated in an unlimited number of consecutive time intervals.

[0033] In the context of the present disclosure, the time interval S N-1 , S N Each of the symbols may be an orthogonal frequency division multiplexing (OFDM) symbol. In this regard, the time interval S may be modulated. N-1 , S N Each of the symbols may carry a data payload (referred to herein as a “data symbol”) and a reference signal (referred to herein as a “reference symbol”), such as a demodulation reference signal (DMRS), a sounding reference signal (SRS), and the like.

[0034] Since the power amplifier circuit 16 needs to amplify the data symbols and the reference symbols to different power levels, the PMIC 12 needs to adapt (increase or decrease) the modulation voltage V on a per-symbol basis. CC In addition, as mentioned previously, the PMIC 12 must N-1 , S N The modulation voltage V is modulated within the corresponding cyclic prefix (CP) of each CC Change from one voltage level to another.

[0035] PMIC 12 includes a voltage processing circuit 22 coupled to voltage output 14. Voltage processing circuit 22 is configured to N-1 , S N Each of the modulation voltages V is generated at a corresponding voltage level. CC .

[0036] As an example, the PMIC 12 also includes a control circuit 24, which may be a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a microprocessor. Herein, the control circuit 24 is configured to receive the modulated target voltage V from the transceiver circuit 20. TGT In a non-limiting example, the control circuit 24 may receive the modulation voltage V via the RF front end (RFFE) bus 26. TGT .

[0037] The modulated target voltage V is thus generated. TGT To indicate the modulation voltage V CC Is it necessary to start from the time interval S N-1 The current voltage level (denoted as “V CC(N-1) ”) changes (increases, decreases or remains unchanged) to the time interval S N The future voltage level (denoted as “V CC(N) ”).

[0038] According to various embodiments of the present disclosure, the control circuit 24 is further configured to dynamically determine whether the modulation voltage V should be changed according to the first voltage conversion scheme or the second voltage conversion scheme. CC Therefore, the control circuit 24 can control the voltage processing circuit 22 to convert the modulation voltage V to the value determined based on the first voltage conversion scheme and the second voltage conversion scheme. CC From the current voltage level V CC(N-1) Change to the next voltage level V CC(N) .

[0039] The PMIC 12 can be configured to modulate the voltage V based on the process CC From the current voltage level V CC(N-1) Change to the next voltage level V CC(N) .in this regard, Figure 2A It can be done by Figure 1 The PMIC 12 in the embodiment adopts a modulation voltage V CC Flowchart of an exemplary process 100 of FIG.

[0040] Herein, the control circuit 24 receives the modulated target voltage V TGT , the modulated target voltage indicates the modulation voltage V CC Need to start from the time interval S N-1 , S N The current time interval S N-1 The current voltage level V CC(N-1) Transition to time interval S N-1 , S NWhich is immediately followed by the current time interval S N-1 The upcoming time interval after S N The future voltage level V CC(N) (Step 102). Therefore, the control circuit 24 can control the voltage processing circuit 22 to convert the modulation voltage V to the voltage V according to one of the first voltage conversion scheme and the second voltage conversion scheme. CC From the current voltage level V CC(N-1) Change to the next voltage level V CC(N) (Step 104).

[0041] In an embodiment, the control circuit 24 can determine whether the modulation voltage V should be changed according to the first voltage conversion scheme or the second voltage conversion scheme according to the process. CC .in this regard, Figure 2B is a flow chart of an exemplary process 106, wherein Figure 1 The PMIC 12 in the embodiment may determine whether to change the modulation voltage V based on the first voltage conversion scheme or the second voltage conversion scheme. CC .

[0042] In this article, the control circuit 24 sets the current voltage level V CC(N-1) and the future voltage level V CC(N) Both with the threshold voltage V TH Compare (step 108). At the current voltage level V CC(N-1) and the future voltage level V CC(N) are greater than or equal to the threshold voltage V TH (V CC(N-1) ≥V TH And V CC(N) ≥V TH ), or at the current voltage level V CC(N-1) and the future voltage level V CC(N) are lower than or equal to the threshold voltage V TH (V CC(N-1) ≤V TH And V CC(N) ≤V TH ), the control circuit 24 determines to change the modulation voltage V based on the first voltage conversion scheme. CC Change to the upcoming time interval S N The future voltage level V CC(N) (Step 110). Otherwise, the control circuit 24 determines to adjust the modulation voltage V CC Change to the upcoming time interval S N The future voltage level V CC(N)(Step 112 ). It is worth noting that both the first voltage conversion scheme and the second voltage conversion scheme are determined in such a way as to ensure that the PMIC 12 can switch the modulation voltage V to V within a very short switching interval (eg, <20 nanoseconds). CC From the current voltage level V CC(N-1) Change to the next voltage level V CC(N) .

[0043] Return to reference Figure 1 , the voltage processing circuit 22 is configured to respectively N-1 , S N The voltage level V CC(N-1) 、V CC(N) Generates the modulation voltage V CC .like Figures 3 to 7 As further described in the specification, the control circuit 24 is configured to control the voltage processing circuit 22 to convert the modulation voltage V CC From the current voltage level V CC(N-1) Change to the next voltage level V CC(N) , as determined based on process 100 of FIG. 2 .

[0044] In an embodiment, the voltage processing circuit 22 includes a voltage amplifier 28 (denoted as "VA"), an offset circuit 30, a switch circuit 32, and a supply voltage circuit 34. The voltage amplifier 28 is coupled to an input 36 of the offset circuit 30 and the offset circuit 30 is coupled to the voltage output 14. In the context of the present disclosure, it is assumed that the power amplifier circuit 16 has a much higher bandwidth than the bandwidth of the offset circuit 30.

[0045] Specifically, the voltage amplifier 28 is configured to be based on the amplifier target voltage V TGT-AMP and the power supply voltage V SUP To generate the initial voltage V AMP The power supply voltage circuit 34 is configured to generate a power supply target voltage V TGT-SUP Generates power supply voltage V SUP , and the power supply voltage V SUP Provided to the voltage amplifier 28. According to various embodiments described herein, the control circuit 24 is configured to modulate the target voltage V TGT and generating an amplifier target voltage V according to a determined one of the first voltage conversion scheme and the second voltage conversion scheme TGT-AMP and the power supply target voltage V TGT-SUP .

[0046] In this context, the offset circuit 30 includes an offset capacitor C OFF and bypass switch S BYP . Offset capacitor C OFFis coupled between the input 36 and the voltage output 14 and bypasses the switch S BYP is coupled between input 36 and ground (GND). The offset capacitor C OFF The voltage amplifier 28 and the voltage output 14 are charged or discharged to provide a modulated offset voltage V OFF Therefore, the offset circuit 30 can modulate the initial voltage V AMP Increase the modulated offset voltage V OFF , thereby generating a modulation voltage V at the voltage output 14 CC (V CC =V AMP +V OFF ).

[0047] The switcher circuit 32 includes a multi-level charge pump (MCP) 38. The MCP 38, which may be a direct current (DC)-DC buck-boost converter, is configured to generate a voltage based on the battery voltage V BAT Generate low frequency voltage V DC (eg, a DC voltage). Specifically, the MCP 38 may operate in a buck mode to generate a voltage at 0×V BAT or 1×V BAT The low frequency voltage V DC , or operate in boost mode to generate a voltage at 2×V BAT The low frequency voltage V DC The MCP 38 can be configured to operate based on a specific duty cycle (e.g., 20% @ 0×V BAT 、30%@1×V BAT and 50%@2×V BAT ) switches between buck mode and boost mode. Thus, the MCP 38 can be controlled to generate a low-frequency voltage V at a desired level. DC .

[0048] In an embodiment, the control circuit 24 may be further configured to modulate the target voltage V based on the modulation TGT and generating an offset target voltage V according to a determined one of the first voltage conversion scheme and the second voltage conversion scheme TGT-OFF . Offset target voltage V TGT-OFF Can indicate the modulation voltage V CC The future voltage level V CC(N) Therefore, the MCP 38 can determine and operate based on the corresponding duty cycle to offset the target voltage V TGT-OFF Generates a low frequency voltage V at the desired level indicated DC .

[0049] The switch circuit 32 also includes a power inductor L P . Power inductor LP is coupled between the MCP 38 and the voltage output 14 and is configured to be based on the low frequency voltage V DC To sense the low frequency current I DC (e.g., DC current). It is understood that the low frequency current I DC According to the low frequency voltage V DC and power inductor L P Therefore, the control circuit 24 can further be based on the offset target voltage V TGT-OFF To change the low frequency current I DC .

[0050] When operating under the first voltage conversion scheme, the PMIC 12 can maintain the offset voltage V OFF Constant and variable modulation initial voltage V AMP To modulate the voltage V CC From the current voltage level V CC(N-1) Change to the next voltage level V CC(N) It can be understood that by maintaining the offset voltage V OFF Constant, no need for offset capacitor C OFF Therefore, it is possible to prevent the capacitor C from being charged or discharged. OFF Potential power loss due to charging or discharging.

[0051] Figure 3 Yes Figure 1 12 in FIG. 1 , which is configured according to an embodiment of the present disclosure to convert a modulation voltage V to a first voltage conversion scheme based on a first voltage conversion scheme. CC From the current voltage level V CC(N-1) Increase to the future voltage level V CC(N) In this paper, the modulation target voltage V TGT Indicates the modulation voltage V CC The current time interval S N-1 The current voltage level V CC(N-1) (e.g., 2.3V) to the upcoming time interval S N The future voltage level V CC(N) (e.g., 2.9V).

[0052] As mentioned above, the control circuit 24 controls the amplifier target voltage V TGT-AMP , offset target voltage V TGT-OFF and the power supply target voltage V TGT-SUP To control the voltage amplifier 28, the switch circuit 32 and the power supply voltage circuit 34. In a non-limiting example, the control circuit 24 will offset the target voltage V TGT-OFF Set equal to VTH -V NHEAD (also called "headroom voltage"). The control circuit 24 also sets the amplifier target voltage V TGT-AMP Set to V CC(N-1) -V TGT-OFF The current level increases to V CC(N) -V TGT-OFF The control circuit 24 further sets the power supply target voltage V TGT-SUP Set to V CC(N-1) -V OFF +V PHEAD The current level of the voltage (also called the "floor voltage") increases to V CC(N) -V OFF +V PHEAD future level.

[0053] It is worth noting that in the current time interval S N-1 , the control circuit 24 has activated the voltage amplifier 28 to CC(N-1) -V OFF The initial voltage V of the modulation is generated at the current level AMP Therefore, in the upcoming time interval S N At the beginning (eg, at time T1), the voltage amplifier 28 remains active to start modulating the initial voltage V AMP Increase to V CC(N) -V OFF At the same time, the power supply voltage circuit 34 starts to adjust the power supply voltage V TGT-SUP Increase the power supply voltage V SUP to ensure that the voltage amplifier 28 can operate at a higher efficiency to the upcoming time interval S N At the end of CP (for example, at time T2), the initial voltage V AMP Increase to V CC(N) -V OFF future level.

[0054] Figure 4 Yes Figure 1 12 in FIG. 1 , which is configured according to an embodiment of the present disclosure to convert a modulation voltage V to a first voltage conversion scheme based on a first voltage conversion scheme. CC From the current voltage level V CC(N-1) Reduced to the future voltage level V CC(N) In this paper, the modulation target voltage V TGT Indicates the modulation voltage V CC The current time interval S N-1 The current voltage level V CC(N-1)(e.g., 2.9V) is reduced to the upcoming time interval S N The future voltage level V CC(N) (e.g., 2.3V).

[0055] In a non-limiting example, the control circuit 24 will offset the target voltage V TGT-OFF Set equal to V TH +V NHEAD (also called "headroom voltage"). The control circuit 24 also sets the amplifier target voltage V TGT-AMP Set to V CC(N-1) -V TGT-OFF The current level decreases to V CC(N) -V TGT-OFF The control circuit 24 further sets the power supply target voltage V TGT-SUP Set to V CC(N-1) -V OFF +V PHEAD (also called the "bottom voltage") decreases to V CC(N) -V OFF +V PHEAD future level.

[0056] It is worth noting that in the current time interval S N-1 , the control circuit 24 has activated the voltage amplifier 28 to CC(N-1) -V OFF The initial voltage V of the modulation is generated at the current level AMP Therefore, in the upcoming time interval S N At the beginning (eg, at time T1), the voltage amplifier 28 remains active to start modulating the initial voltage V AMP Reduce to V CC(N) -V OFF At the same time, the power supply voltage circuit 34 starts to adjust the power supply voltage V TGT-SUP Reduce the power supply voltage V SUP to ensure that the voltage amplifier 28 can operate at a higher efficiency to the upcoming time interval S N At the end of CP (for example, at time T2), the initial voltage V AMP Reduce to V CC(N) -V OFF future level.

[0057] Return to reference Figure 1 When operating under the second voltage conversion scheme, in addition to using the voltage amplifier 28 to adjust the initial voltage V AMP In addition, PMIC 12 can also adjust the offset voltage V OFF To modulate the voltage VCC From the current voltage level V CC(N-1) Change to the next voltage level V CC(N) More specifically, the offset circuit 30 will make the modulation voltage V CC In the transition interval ( Figures 5 to 7 denoted as "TP") from the current time interval S N-1 The current voltage level V CC(N-1) Change to the upcoming time interval S N The future voltage level V CC(N) . Depends on the modulation voltage V CC From the current time interval S N-1 To the upcoming time interval S N Increase or decrease, the transition interval TP can be located within the current time interval S N-1 or the upcoming time interval S N To ensure that the modulation voltage V CC can be to the upcoming time interval S N When CP reaches the next voltage level V CC(N) .

[0058] like Figures 5 to 7 It is further shown that although the modulation voltage V CC During the transition interval TP, the current voltage level V CC(N-1) Transition to the next voltage level V CC(N) , but the voltage amplifier 28 is activated at the beginning of the transition interval TP (denoted as "T1") and deactivated at the end of the transition interval TP (denoted as "T2") to ensure proper operation of the power amplifier circuit 16. In this article, the voltage amplifier 28 is configured based on the amplifier target voltage V TGT-AMP and the power supply voltage V SUP Generate the initial voltage V for modulation AMP .

[0059] like Figures 5 to 7 As discussed in the detailed example in , the amplifier target voltage V is determined in this way TGT-AMP To ensure that the voltage amplifier 28 can modulate the initial voltage V AMP Maintained at or above a headroom voltage V greater than 0V NHEAD Therefore, the voltage amplifier 28 can convert the modulation voltage V CC Maintain the current voltage level V CC(N-1) , and suppresses the modulation voltage V during the transition interval TP CC , thereby ensuring proper operation of the power amplifier circuit 16 during the transition interval TP.

[0060] According to an embodiment of the present disclosure, the control circuit 24 may be configured to CC(N-1) With the future voltage level V CC(N) The difference between ΔV CC (ΔV CC =V CC(N-1) -V CC(N) ) to determine the transition interval TP should be within the current time interval S N-1 Within or in the upcoming time interval S N It can be understood that at the current voltage level V CC(N-1) Above the future voltage level V CC(N) When the difference ΔV CC will be positive, or at the current voltage level V CC(N-1) Below the future voltage level V CC(N) When the difference ΔV CC Therefore, control circuit 24 may control offset circuit 30 (eg, via control signal 40 ) during transition interval TP.

[0061] The control circuit 24 may also be configured to determine the difference ΔV based on the determined difference ΔV. CC To determine the amplifier target voltage V TGT-AMP When the future voltage level V CC(N) Higher than the current voltage level V CC(N-1) When Figure 5 As shown in Figure 2, the amplifier target voltage V TGT-AMP Equal to the future voltage level V CC(N) and the marked voltage (expressed as "V DIFF ”) as shown in the equation below (Equation 1). In contrast, when the future voltage level V CC(N) Below the current voltage level V CC(N-1) When Figure 6 and 7 As shown in Figure 2, the amplifier target voltage V TGT-AMP Equal to the current voltage level V CC(N-1) and the marked voltage V DIFF The sum of , as shown in the equation below (Equation 2).

[0062] V TGT-AMP =V CC(N) +V DIFF (Equation 1)

[0063] V TGT-AMP =V CC(N-1) +V DIFF (Equation 2)

[0064] In the equations (Equation 1 and Equation 2), depending on the modulation voltage V CC From the current time interval SN-1 To the upcoming time interval S N How will the marked voltage V change? DIFF In this regard, by changing the amplifier target voltage V TGT-AMP And more specifically changing the marking voltage V DIFF , the control circuit 24 can cause the voltage amplifier 28 to generate the modulated initial voltage V at an appropriate level during the transition interval TP AMP , to maintain proper operation of the power amplifier circuit 16.

[0065] The control circuit 24 may be further configured to activate the voltage amplifier 28 at the beginning T1 of the transition interval TP and deactivate the voltage amplifier 28 at the end T2 of the transition interval TP. CC By activating / deactivating the voltage amplifier 28 to ensure proper operation of the power amplifier circuit 16 during the transition interval TP, the PMIC 12 can effectively switch the modulation voltage V under increasingly stringent switching time requirements (e.g., <20ns). CC .

[0066] In one operation scenario under the second voltage conversion scheme, the modulation voltage V CC Set to the current time interval S N-1 The current voltage level V CC(N-1) Increase to the upcoming time interval S N The future voltage level V CC(N) (V CC(N-1) <V CC(N) ). In this regard, the control circuit 24 will offset the target voltage V TGT-OFF Set the modulation voltage V CC The future voltage level V CC(N) , so that the low-frequency current I is generated in the desired amount DC , thereby shifting the offset capacitor C OFF Charge to the future voltage level V CC(N) .

[0067] The control circuit 24 will open the bypass switch S at the beginning of the transition interval TP. BYP and activates the voltage amplifier 28 to generate a voltage higher than the future voltage level V CC(N) The amplifier target voltage V is generated at a level of TGT-AMP , so that the current I TRAN can flow from the MCP38 through the offset capacitor C OFF and is collected in the voltage amplifier 28. Therefore, the current I TRAN During the transition interval TP, the offset capacitor C OFFGradually charging to the future voltage level V CC(N) When the offset capacitor C OFF At the end of the transition interval TP, it is charged to the future voltage level V CC(N) When the control circuit 24 deactivates the voltage amplifier 28 and closes the bypass switch S BYP . Thereafter, the offset capacitor C OFF and MCP 38 will be in the upcoming time interval S N The remaining time will modulate the voltage V CC Maintaining the voltage level V CC(N) .

[0068] The operation described above can be Figure 5 It is shown graphically in . Figure 5 Yes Figure 1 12 in FIG. 1 , which is configured according to an embodiment of the present disclosure to convert the modulation voltage V to V based on the second voltage conversion scheme. CC From the current voltage level V CC(N-1) Increase to the future voltage level V CC(N) .

[0069] As shown in the figure, the transition interval TP falls completely within the upcoming time interval S N The transition interval TP starts at T1 and the current time interval S N-1 With the upcoming time interval S N The boundary between T0 (also called the upcoming time interval S N The start time of the CP in the transition interval TP is aligned, and the end T2 of the transition interval TP occurs at time T3 (also referred to as the upcoming time interval S N It can be understood that CP is usually much shorter than the transition interval TP. In this article, the modulated target voltage V TGT Indicates the modulation voltage V CC The current time interval S N-1 The current voltage level V CC(N-1) (e.g., 2.3V) to the upcoming time interval S N The future voltage level V CC(N) (eg, 2.9 V). Therefore, the control circuit 24 determines the offset target voltage V TGT-OFF At the beginning of the transition interval TP, it is equal to the future voltage level V CC(N) .

[0070] About the amplifier target voltage V TGT-AMP , the control circuit 24 is configured to convert the marking voltage V in the equation (Equation 1) DIFF Set equal to the headroom voltage VNHEAD (V TGT-AMP =V CC(N) +V NHEAD At time T1, the control circuit 24 turns off the bypass switch S BYP And the voltage amplifier 28 is activated. Therefore, the voltage amplifier 28 will be based on the amplifier target voltage V TGT-AMP The modulated initial voltage V is generated at input 36 AMP In a non-limiting example, the voltage amplifier 28 may modulate the initial voltage V AMP Drive quickly from GND level to the difference ΔV CC (ΔV CC <0) to help stabilize the modulation voltage V during the transition interval TP CC After that, the voltage amplifier 28 modulates the initial voltage V AMP Gradually decrease to the clearance voltage V NHEAD .

[0071] Starting from time T1, the offset capacitor C OFF gradually charges to reach the future voltage level V at time T2 CC(N) Therefore, at time T2, the control circuit 24 closes the bypass switch S BYP And deactivate the voltage amplifier 28 so that the initial voltage V AMP Return to GND level. Equal to the initial voltage V AMP and offset voltage V OFF The sum of the modulation voltage V CC will stabilize at the next voltage level V at time T3 CC(N) It is worth noting that since the voltage amplifier 28 bypasses the switch S BYP The initial voltage V AMP Maintained at or above the headroom voltage V NHEAD , so the modulation voltage V CC will not drop below the headroom voltage V NHEAD , thereby ensuring proper operation of the power amplifier circuit 16.

[0072] Return to reference Figure 1 In another operation situation under the second voltage conversion scheme, the modulation voltage V CC Set to the current time interval S N-1 The current voltage level V CC(N-1) Reduce to the upcoming time interval S N The future voltage level V CC(N) (V CC(N-1) >V CC(N) ). In this regard, the control circuit 24 will offset the target voltage VTGT-OFF Set the modulation voltage V CC The future voltage level V CC(N) , so that the low-frequency current I is generated in the desired amount DC , so that the offset capacitor C OFF Discharge to the future voltage level V CC(N) .

[0073] The control circuit 24 will open the bypass switch S at the beginning of the transition interval TP. BYP And activate the voltage amplifier 28 to CC(N-1) The lower generating amplifier target voltage V TGT-AMP , so that the current I TRAN can flow from the voltage amplifier 28 through the offset capacitor C OFF and returns to the MCP 38 and / or the power amplifier circuit 16. Therefore, the offset capacitor C OFF will gradually discharge to the future voltage level V during the transition interval TP CC(N) When the offset capacitor C OFF At the end of the transition interval TP, it discharges to the future voltage level V CC(N) When the control circuit 24 deactivates the voltage amplifier 28 and closes the bypass switch S BYP . Thereafter, the offset capacitor C OFF and MCP 38 will be in the upcoming time interval S N The remaining time will modulate the voltage V CC Maintaining the voltage level V CC(N) .

[0074] The operation described above can be Figure 6 and 7 It is shown graphically in . Figure 6 Yes Figure 1 1 is an exemplary illustrated timing diagram of a PMIC 12 in FIG. 1 , wherein the PMIC is configured according to an embodiment of the present disclosure to convert the modulation voltage V CC From the current voltage level V CC(N-1) Reduced to the future voltage level V CC(N) More specifically, Figure 6 Shows the headroom voltage V NHEAD (e.g., 0.4V) is lower than the current voltage level V CC(N-1) With the future voltage level V CC(N) The difference between ΔV CC (For example, 0.6V)(V NHEAD <ΔV CC ) situation.

[0075] As shown in the figure, the transition interval TP falls completely within the current time interval SN-1 The transition interval TP starts at the beginning T1 of the current time interval S N-1 With the upcoming time interval S N Before the boundary T0 between the transition interval TP and the end T2 of the transition interval TP and the boundary T0 (also referred to as the upcoming time interval S N It is understood that CP is usually much shorter than the transition interval TP. In this article, the modulated target voltage V TGT Indicates the modulation voltage V CC The current time interval S N-1 The current voltage level V CC(N-1) (e.g., 2.9V) is reduced to the upcoming time interval S N The future voltage level V CC(N) (eg, 2.3 V). Therefore, the control circuit 24 determines the offset target voltage V TGT-OFF At the beginning of the transition interval TP, it is equal to the future voltage level V CC(N) .

[0076] About the amplifier target voltage V TGT-AMP , the control circuit 24 is configured to convert the marking voltage V in the equation (Equation 2) DIFF Set to 0V (V TGT-AMP =V CC(N-1) +0). At time T1, the control circuit 24 turns off the bypass switch S BYP And the voltage amplifier 28 is activated. Therefore, the voltage amplifier 28 will be based on the amplifier target voltage V TGT-AMP The modulated initial voltage V is generated at input 36 AMP In a non-limiting example, the voltage amplifier 28 can immediately modulate the initial voltage V AMP Drive from GND level to headroom voltage V NHEAD After that, the voltage amplifier 28 will continue to modulate the initial voltage V AMP Driven to voltage difference ΔV CC .

[0077] Starting from time T1, the offset capacitor C OFF gradually discharges to reach the future voltage level V at time T2 CC(N) Therefore, at time T2, the control circuit 24 closes the bypass switch S BYP And deactivate the voltage amplifier 28 so that the initial voltage V AMP At time T3, it returns to the GND level. It is equal to the initial voltage V AMP and offset voltage V OFF The sum of the modulation voltage V CCwill stabilize at the next voltage level V at time T3 CC(N) It is worth noting that since the voltage amplifier 28 bypasses the switch S BYP The initial voltage V AMP Maintained at or above the headroom voltage V NHEAD , so the modulation voltage V CC will not drop below the headroom voltage V NHEAD , thereby ensuring proper operation of the power amplifier circuit 16.

[0078] Figure 7 Yes Figure 1 12 in FIG. 1 , which is configured according to another embodiment of the present disclosure to convert the modulation voltage V to V based on the second voltage conversion scheme. CC From the current voltage level V CC(N-1) Reduced to the future voltage level V CC(N) More specifically, Figure 7 Shows the headroom voltage V NHEAD (e.g., 0.4V) is higher than or equal to the current voltage level V CC(N-1) With the future voltage level V CC(N) The difference between ΔV CC (For example, 0.1V)(V NHEAD ≥ΔV CC ) situation.

[0079] As shown in the figure, the transition interval TP falls completely within the current time interval S N-1 The transition interval TP starts at the beginning T1 of the current time interval S N-1 With the upcoming time interval S N Before the boundary T0 between the transition interval TP and the end T2 of the transition interval TP and the boundary T0 (also referred to as the upcoming time interval S N It is understood that CP is usually much shorter than the transition interval TP. In this article, the modulated target voltage V TGT Indicates the modulation voltage V CC The current time interval S N-1 The current voltage level V CC(N-1) (e.g., 2.9V) is reduced to the upcoming time interval S N The future voltage level V CC(N) (eg, 2.8 V). Therefore, the control circuit 24 determines the offset target voltage V TGT-OFF At the beginning of the transition interval TP, it is equal to the future voltage level V CC(N) .

[0080] About the amplifier target voltage V TGT-AMP, the control circuit 24 is configured to convert the marking voltage V in the equation (Equation 2) DIFF Set equal to the headroom voltage V NHEAD Subtract the current voltage level V CC(N-1) With the future voltage level V CC(N) The difference between ΔV CC (V TGT-AMP =V CC(N-1) + NHEAD -ΔV CC At time T1, the control circuit 24 turns off the bypass switch S BYP And the voltage amplifier 28 is activated. Therefore, the voltage amplifier 28 will be based on the amplifier target voltage V TGT-AMP The modulated initial voltage V is generated at input 36 AMP In a non-limiting example, the voltage amplifier 28 can immediately modulate the initial voltage V AMP Drive from GND level to difference ΔV CC After that, the voltage amplifier 28 will continue to modulate the initial voltage V AMP Drive to headroom voltage V NHEAD .

[0081] Starting from time T1, the offset capacitor C OFF gradually discharges to reach the future voltage level V at time T2 CC(N) Therefore, at time T2, the control circuit 24 closes the bypass switch S BYP And deactivate the voltage amplifier 28 so that the initial voltage V AMP At time T3, it returns to the GND level. It is equal to the initial voltage V AMP and offset voltage V OFF The sum of the modulation voltage V CC will stabilize at the next voltage level V at time T3 CC(N) It is worth noting that since the voltage amplifier 28 bypasses the switch S BYP The initial voltage V AMP Maintained at or above the headroom voltage V NHEAD , so the modulation voltage V CC will not drop below the headroom voltage V NHEAD , thereby ensuring proper operation of the power amplifier circuit 16.

[0082] Figure 1 The wireless communication circuit 10 may be provided in a user element to change the modulation voltage V according to the embodiment described above. CC .in this regard, Figure 8 is a schematic diagram of an exemplary user element 200, in which a Figure 1 Wireless communication circuit 10.

[0083] Herein, user element 200 can be any type of user element, such as a mobile terminal, smart watch, tablet computer, computer, navigation device, access point and similar wireless communication device supporting wireless communication, such as cellular, wireless local area network (WLAN), Bluetooth and near field communication. User element 200 will generally include control system 202, baseband processor 204, transmission circuit system 206, receiving circuit system 208, antenna switching circuit system 210, multiple antennas 212 and user interface circuit system 214. In a non-limiting example, as an example, control system 202 can be a field programmable gate array (FPGA). In this regard, control system 202 can include at least a microprocessor, an embedded memory circuit and a communication bus interface. Receive circuit system 208 receives radio frequency signals from one or more base stations via antenna 212 and through antenna switching circuit system 210. Low noise amplifier and filter cooperate to amplify and eliminate broadband interference from received signals for processing. Downconversion and digitization circuitry (not shown) then downconverts the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using an analog-to-digital converter (ADC).

[0084] The baseband processor 204 processes the digitized received signal to extract the information or data bits transmitted in the received signal. Such processing typically includes demodulation, decoding, and error correction operations, which will be discussed in more detail below. The baseband processor 204 is typically implemented in one or more digital signal processors (DSPs) and application specific integrated circuits (ASICs).

[0085] For transmission, the baseband processor 204 receives digitized data, which may represent voice, data, or control information, from the control system 202, and encodes the digitized data for transmission. The encoded data is output to the transmit circuit system 206, where a digital / analog converter (DAC) converts the digital encoded data into an analog signal, and a modulator modulates the analog signal onto a carrier signal at one or more desired transmit frequencies. The power amplifier amplifies the modulated carrier signal to a level suitable for transmission and delivers the modulated carrier signal to the antenna 212 through the antenna switching circuit system 210. Multiple antennas 212 and duplicate transmit circuit systems 206 and receive circuit systems 208 can provide spatial diversity. Those skilled in the art will understand the modulation and processing details.

[0086] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the claims below.

Claims

1. A power management integrated circuit PMIC (12), comprising: Voltage output (14), the modulation voltage (V CC ) is output to a power amplifier circuit (16) to amplify the power at multiple time intervals (S N-1 , S N ) modulated radio frequency RF signal (18); The voltage processing circuit (22) is configured to N-1 , S N ) in each of the corresponding voltage levels (V CC(N-1) 、V CC(N) ) generates the modulation voltage (V CC ); as well as The control circuit (24) is configured to: Receive the modulated target voltage (V TGT ), the modulated target voltage indicates the modulation voltage (V CC ) need to be from the multiple time intervals (S N-1 , S N ) in the current time interval (S N-1 ) in the current voltage level (V CC(N-1) ) to the plurality of time intervals (S N-1 , S N ) immediately following the current time interval (S N-1 ) after the upcoming time interval (S N ) in the future voltage level (V CC(N) ); as well as The voltage processing circuit (22) is controlled to convert the modulation voltage (V CC ) from the current voltage level (V CC(N-1) ) changes to the future voltage level (V CC(N) ).

2. The PMIC according to claim 1, wherein: The control circuit is further configured to: controlling the voltage processing circuit to change the modulation voltage from the current voltage level to the future voltage level based on the first voltage transition scheme when any one of the following conditions is met: The current voltage level and the future voltage level are both higher than or equal to a threshold voltage; as well as The present voltage level and the future voltage level are both lower than or equal to the threshold voltage; as well as controlling the voltage processing circuit to change the modulation voltage from the current voltage level to the future voltage level based on the second voltage transition scheme when any one of the following conditions is met: The present voltage level is above the threshold voltage and the future voltage level is below the threshold voltage; and The present voltage level is lower than the threshold voltage and the future voltage level is higher than the threshold voltage.

3. The PMIC according to claim 1, wherein: The voltage processing circuit (22) comprises: The voltage amplifier (28) is configured to SUP ) and the modulated target voltage (V TGT ) generates the initial voltage for modulation (V AMP ); An offset circuit (30) is coupled between the voltage amplifier (28) and the voltage output (14) and is configured to shift the modulated initial voltage (V AMP ) increases the modulated offset voltage (V OFF ) to generate the modulation voltage (V CC ); A switch circuit (32) configured to cause the offset circuit (30) to provide the modulated offset voltage (V OFF );as well as A power supply voltage circuit (34) is configured to generate the power supply voltage (V SUP ).

4. The PMIC according to claim 3, wherein: In the first voltage conversion scheme, the control circuit is further configured to: determining that the future voltage level of the modulation voltage is higher than the current voltage level of the modulation voltage; controlling the offset circuit to maintain the modulated offset voltage at a constant voltage level between the current time interval and the upcoming time interval; controlling the supply voltage circuit to increase the supply voltage at the beginning of the upcoming time interval; as well as The voltage amplifier is controlled to increase the modulated initial voltage at the beginning of the upcoming time interval based on the increased supply voltage.

5. The PMIC according to claim 3, wherein: In the first voltage conversion scheme, the control circuit is further configured to: determining that the future voltage level of the modulation voltage is lower than the current voltage level of the modulation voltage; controlling the offset circuit to maintain the modulated offset voltage at a constant voltage level between the current time interval and the upcoming time interval; controlling the supply voltage circuit to reduce the supply voltage at the beginning of the upcoming time interval; as well as The voltage amplifier is controlled to reduce the modulated initial voltage at the beginning of the upcoming time interval based on the reduced supply voltage.

6. The PMIC according to claim 3, wherein: In the second voltage conversion scheme, the control circuit is further configured to: determining a start and an end of a transition interval based on the present voltage level and the future voltage level of the modulation voltage; determining an amplifier target voltage equal to the sum of the future voltage level and a mark voltage; activating the voltage amplifier at the beginning of the transition interval; and The voltage amplifier is deactivated at the end of the transition interval.

7. The PMIC according to claim 6, wherein: The control circuit is further configured to: determining that the future voltage level of the modulation voltage is higher than the current voltage level of the modulation voltage; determining a start of the transition interval at a boundary between the current time interval and the upcoming time interval; determining that an end of the transition interval is later than the boundary between the current time interval and the upcoming time interval; Determining that the mark voltage is equal to the headroom voltage; as well as The offset circuit is caused to increase the modulation voltage from the present voltage level to the future voltage level by the end of the transition interval.

8. The PMIC according to claim 6, wherein: The control circuit is further configured to: determining that the future voltage level of the modulation voltage is lower than the present voltage level of the modulation voltage and that a headroom voltage is lower than a difference between the present voltage level and the future voltage level; determining that a start of the transition interval is earlier than a boundary between the current time interval and the upcoming time interval; determining an end of the transition interval at the boundary between the current time interval and the upcoming time interval; Determining that the marking voltage is equal to zero; as well as The offset circuit is caused to reduce the modulation voltage from the present voltage level to the future voltage level by the end of the transition interval.

9. The PMIC according to claim 6, wherein: The control circuit is further configured to: determining that the future voltage level of the modulation voltage is lower than the present voltage level of the modulation voltage and that a headroom voltage is higher than or equal to a difference between the present voltage level and the future voltage level; determining that a start of the transition interval is earlier than a boundary between the current time interval and the upcoming time interval; determining an end of the transition interval at the boundary between the current time interval and the upcoming time interval; determining the mark voltage to be equal to the headroom voltage minus the difference between the present voltage level and the future voltage level; as well as The offset circuit is caused to reduce the modulation voltage from the present voltage level to the future voltage level by the end of the transition interval.

10. The PMIC according to claim 1, wherein: Each of the plurality of time intervals corresponds to an Orthogonal Frequency Division Multiplexing (OFDM) symbol.

11. A method for switching the modulation voltage (V CC ) methods, including: Receive the modulated target voltage (V TGT ), the modulated target voltage indicates the modulation voltage (V CC ) requires multiple time intervals (S N-1 , S N ) in the current time interval (S N-1 ) in the current voltage level (V CC(N-1) ) to the plurality of time intervals (S N-1 , S N ) immediately following the current time interval (S N-1 ) after the upcoming time interval (S N ) in the future voltage level (V CC(N) );as well as The modulation voltage (V CC ) from the current voltage level (V CC(N-1) ) changes to the future voltage level (V CC(N) ).

12. The method according to claim 11, further comprising: The modulation voltage is changed from the current voltage level to the future voltage level based on the first voltage transition scheme when any one of the following conditions is met: The current voltage level and the future voltage level are both higher than or equal to a threshold voltage; as well as The present voltage level and the future voltage level are both lower than or equal to the threshold voltage; as well as The modulation voltage is changed from the current voltage level to the future voltage level based on the second voltage transition scheme when any one of the following conditions is met: The present voltage level is above the threshold voltage and the future voltage level is below the threshold voltage; and The present voltage level is lower than the threshold voltage and the future voltage level is higher than the threshold voltage.

13. The method according to claim 11, further comprising: Based on the power supply voltage (V SUP ) and the modulated target voltage (V TGT ) generates the initial voltage for modulation (V AMP );as well as The initial voltage of the modulation (V AMP ) increases the modulated offset voltage (V OFF ) to generate the modulation voltage (V CC ).

14. The method according to claim 13, further comprising: determining that the future voltage level of the modulation voltage is higher than the current voltage level of the modulation voltage; maintaining the modulated offset voltage at a constant voltage level between the current time interval and the upcoming time interval; increasing the supply voltage at the beginning of the upcoming time interval; as well as The modulated initial voltage is increased at the beginning of the upcoming time interval based on the increased supply voltage.

15. The method according to claim 13, further comprising: determining that the future voltage level of the modulation voltage is lower than the current voltage level of the modulation voltage; maintaining the modulated offset voltage at a constant voltage level between the current time interval and the upcoming time interval; reducing the supply voltage at the beginning of the upcoming time interval; as well as The modulated initial voltage is reduced at the beginning of the upcoming time interval based on the reduced supply voltage.

16. The method according to claim 13, further comprising: determining a start and an end of a transition interval based on the present voltage level and the future voltage level of the modulation voltage; determining an amplifier target voltage equal to the sum of the future voltage level and a mark voltage; generating an initial voltage for said modulation at the beginning of said transition interval; as well as The generation of the modulated initial voltage is stopped at the end of the transition interval.

17. The method according to claim 16, further comprising: determining that the future voltage level of the modulation voltage is higher than the current voltage level of the modulation voltage; determining a start of the transition interval at a boundary between the current time interval and the upcoming time interval; determining that an end of the transition interval is later than the boundary between the current time interval and the upcoming time interval; Determining that the mark voltage is equal to the headroom voltage; as well as The modulation voltage is increased from the present voltage level to the future voltage level by the end of the transition interval.

18. The method according to claim 16, further comprising: determining that the future voltage level of the modulation voltage is lower than the present voltage level of the modulation voltage and that a headroom voltage is lower than a difference between the present voltage level and the future voltage level; determining that a start of the transition interval is earlier than a boundary between the current time interval and the upcoming time interval; determining an end of the transition interval at the boundary between the current time interval and the upcoming time interval; Determining that the marking voltage is equal to zero; as well as The modulation voltage is reduced from the present voltage level to the future voltage level by the end of the transition interval.

19. The method according to claim 16, further comprising: determining that the future voltage level of the modulation voltage is lower than the present voltage level of the modulation voltage and that a headroom voltage is higher than or equal to a difference between the present voltage level and the future voltage level; determining that a start of the transition interval is earlier than a boundary between the current time interval and the upcoming time interval; determining an end of the transition interval at the boundary between the current time interval and the upcoming time interval; determining the mark voltage to be equal to the headroom voltage minus the difference between the present voltage level and the future voltage level; as well as The modulation voltage is reduced from the present voltage level to the future voltage level by the end of the transition interval.

20. The method according to claim 11, wherein: Each of the plurality of time intervals corresponds to an Orthogonal Frequency Division Multiplexing (OFDM) symbol.

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