Power supply control circuit of chip and chip

Abstract

The embodiment of the invention provides a power supply control circuit of a chip and the chip. The power supply control circuit comprises a node voltage generation module, a comparison module and a control module, the node voltage generation module establishes a stable first internal node voltage according to a power supply port voltage and establishes a stable second internal node voltage according to an internal circuit voltage, and the comparison module compares the first internal node voltage with the power supply port voltage and controls the control module. The first internal node voltage and the power port voltage are compared to obtain a first comparison signal, the second internal node voltage and the power port voltage are compared to obtain a second comparison signal, and the control module controls connection and disconnection between the power port and the power end of the internal circuit according to the first comparison signal and the second comparison signal so as to prevent grounding rebound noise in the external power signal from entering the internal circuit. The stability of the chip can be improved. The power supply control circuit can prevent grounding rebound noise from entering an internal circuit, so that the stability of a chip is improved, the complexity of the circuit can be reduced, and the area of the chip is reduced.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the technical field of integrated circuits, and in particular to a power control circuit of a chip and a chip. Background Art

[0002] In order to support large-scale power supply, the chip usually needs to be configured with an off-chip capacitor for power stabilization. The negative end of the off-chip capacitor is usually connected to the ideal ground of the printed circuit board (PCB), that is, the negative end of the off-chip capacitor is connected to the PCB ground. The PCB routing and packaging have parasitic inductance, and the ground at the chip end will be affected by ground bounce noise, that is, the chip ground is affected by ground bounce noise. Since the power supply of the internal circuit of the chip is composed of the positive end of the off-chip capacitor and the chip ground, the ground bounce voltage is equivalent to superimposed on the power supply voltage of the internal circuit, causing the internal circuit of the chip to be subject to a lot of noise, and the key performance of the chip is deteriorated, for example, the reference voltage is offset, the feedback loop loses control, etc. The low-voltage circuit of the chip is also at risk of damage due to contact with excessively high voltage.

[0003] In the prior art, the output signal of the power stage is usually collected and transmitted to the power port accessories, and a shielding signal is generated based on the output signal of the power stage and the conduction logic of the power supply is controlled to shield the energy transmission of the ground bounce noise device. However, the collection and transmission of the power stage output signal requires the setting of additional circuits, resulting in a larger chip area. Summary of the invention

[0004] The present disclosure provides a power control circuit and a chip of a chip, which can prevent ground bounce noise from entering the internal circuit, thereby improving the stability of the chip, and can also reduce circuit complexity, thereby reducing the chip area.

[0005] In a first aspect, the present disclosure provides a power control circuit of a chip, wherein the chip comprises a power port and an internal circuit, and the power control circuit comprises a node voltage generation module, a comparison module and a control module.

[0006] The node voltage generating module is configured to establish a stable first internal node voltage according to a power port voltage, and to establish a stable second internal node voltage according to an internal circuit voltage, wherein the power port voltage is the voltage of an external power signal received by the power port, and the internal circuit voltage is the power voltage of the internal circuit.

[0007] The comparison module is configured to compare the first internal node voltage with the power port voltage to obtain a first comparison signal; and compare the second internal node voltage with the power port voltage to obtain a second comparison signal.

[0008] The control module is configured to control the connection and disconnection between the power port and the power terminal of the internal circuit according to the first comparison signal and the second comparison signal, so as to prevent the ground bounce noise in the external power signal from entering the internal circuit.

[0009] In some embodiments of the present disclosure, the comparison module includes a positive comparison unit and a negative comparison unit, the first input end of the positive comparison unit is connected to the first output end of the node voltage generating module, the second input end of the positive comparison unit is connected to the power supply port, the output end of the positive comparison unit is connected to the first input end of the control module, the first input end of the negative comparison unit is connected to the power supply port, the second input end of the negative comparison unit is connected to the second output end of the node voltage generating module, and the output end of the negative comparison unit is connected to the second input end of the control module.

[0010] The forward comparison unit is configured to output a first level signal when the power port voltage is greater than or equal to the sum of the first internal node voltage and the first preset voltage; and to output a second level signal when the power port voltage is less than the sum of the first internal node voltage and the preset voltage.

[0011] The negative comparison unit is configured to output the first level signal when the sum of the power port voltage and the second preset voltage is less than or equal to the second internal node voltage; and to output the second level signal when the sum of the power port voltage and the second preset voltage is greater than the second internal node voltage.

[0012] In some embodiments of the present disclosure, the forward comparison unit includes a first transistor and a first resistor, the control end of the first transistor is connected to the first output end of the node voltage generating module, the first end of the first transistor is connected to the power supply port, the second end of the first transistor is connected to the first input end of the control module and the first end of the first resistor, and the second end of the first resistor is connected to the chip ground.

[0013] In some embodiments of the present disclosure, the negative comparison unit includes a second transistor, a second resistor, a third resistor and a first capacitor, the control end of the second transistor is connected to the first plate of the first capacitor and the first end of the third resistor, the second plate of the first capacitor is connected to the power supply port, the second end of the third resistor is connected to the power supply end of the internal circuit, the first end of the second transistor is connected to the second output end of the node voltage generation module, the second end of the second transistor is connected to the second input end of the control module and the first end of the second resistor, and the second end of the second resistor is connected to the chip ground.

[0014] In some embodiments of the present disclosure, the control module includes a positive signal generating unit, a negative signal generating unit and a control unit, the input end of the positive signal generating unit is connected to the first output end of the comparison module, the output end of the positive signal generating unit is connected to the first control end of the control unit, the input end of the negative signal generating unit is connected to the second output end of the comparison module, the output end of the negative signal generating unit is connected to the second control end of the control unit, the input end of the control unit is connected to the power port, and the output end of the control unit is connected to the power end of the internal circuit.

[0015] The positive signal generating unit is configured to generate a positive control signal according to the first comparison signal, wherein the positive control signal includes a positive conduction control signal and a positive disconnection control signal. The negative signal generating unit is configured to generate a negative control signal according to the second comparison signal, wherein the negative control signal includes a negative conduction control signal and a negative disconnection control signal.

[0016] The control unit is configured to, when the positive control signal is the positive conduction control signal and the negative control signal is the negative conduction control signal, conduct the power port and the power end of the internal circuit; and when the positive control signal is the positive disconnection control signal or the negative control signal is the negative disconnection control signal, disconnect the power port and the power end of the internal circuit to prevent the ground bounce noise from entering the internal circuit.

[0017] In some embodiments of the present disclosure, the forward signal generating unit includes a third transistor, a fourth transistor, a fifth transistor and a fourth resistor, the control end of the third transistor and the control end of the fourth transistor are connected to the first output end of the comparison module, the first end of the third transistor and the first end of the fifth transistor are connected to the power supply port, the second end of the third transistor is connected to the second end of the fourth transistor and the control end of the fifth transistor, the second end of the fifth transistor is connected to the first end of the fourth resistor and the first control end of the control unit, and the second end of the fourth resistor and the first end of the fourth transistor are connected to the chip ground.

[0018] In some embodiments of the present disclosure, the negative signal generating unit includes a sixth transistor, a seventh transistor, an eighth transistor and a fifth resistor, the control end of the sixth transistor and the control end of the seventh transistor are connected to the second output end of the comparison module, the first end of the sixth transistor and the first end of the eighth transistor are connected to the power supply end of the internal circuit, the second end of the sixth transistor is connected to the second end of the seventh transistor and the control end of the eighth transistor, the second end of the eighth transistor is connected to the first end of the fifth resistor and the second control end of the control unit, and the second end of the fifth resistor and the second end of the seventh transistor are connected to the chip ground.

[0019] In some embodiments of the present disclosure, the control unit includes a ninth transistor and a tenth transistor, the control end of the ninth transistor is connected to the output end of the positive signal generating unit, the control end of the tenth transistor is connected to the output end of the negative signal generating unit, the first end of the ninth transistor is connected to the power supply port, the first end of the tenth transistor is connected to the power supply end of the internal circuit, and the second end of the ninth transistor is connected to the second end of the tenth transistor.

[0020] In some embodiments of the present disclosure, the node voltage generating module includes a sixth resistor, a seventh resistor, a second capacitor and a third capacitor, the first end of the sixth resistor is connected to the power port, the second end of the sixth resistor is connected to the first plate of the second capacitor and the first input terminal of the comparison module, the first end of the seventh resistor is connected to the power terminal of the internal circuit, the second end of the seventh resistor is connected to the first plate of the third capacitor and the second input terminal of the comparison module, and the second plate of the second capacitor and the second plate of the third capacitor are connected to the chip ground.

[0021] In a second aspect, the present disclosure provides a chip, comprising a power port, an internal circuit, and any power control circuit provided in the first aspect.

[0022] The technical solution disclosed in the present invention provides a power control circuit of a chip, including a node voltage generation module, a comparison module and a control module, wherein the node voltage generation module establishes a stable first internal node voltage according to the power port voltage, and establishes a stable second internal node voltage according to the internal circuit voltage, wherein the power port voltage is the voltage of the external power signal received by the power port, and the internal circuit voltage is the power supply voltage of the internal circuit, and the comparison module compares the first internal node voltage and the power port voltage to obtain a first comparison signal, and compares the second internal node voltage and the power port voltage to obtain a second comparison signal, and the control module controls the on-off between the power port and the power supply end of the internal circuit according to the first comparison signal and the second comparison signal, so as to avoid the ground bounce noise in the external power signal from entering the internal circuit, and the stability of the chip can be improved. In this way, the power control circuit can adaptively determine whether the external power signal contains ground bounce noise based on the amplitude and duration of the ground bounce noise, and there is no need to collect the power level output signal, so there is no need to set up an additional circuit to monitor the chip power level working state, and there is no need to set up an additional circuit to monitor, collect and transmit the power level output signal, which can reduce the circuit complexity, thereby reducing the chip area. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. It should be noted that the drawings described below only relate to some embodiments of the present disclosure, rather than limiting the present disclosure, wherein:

[0024] Figure 1 A schematic diagram of the structure of a switching power supply chip provided by the prior art.

[0025] Figure 2 A control timing diagram of a switching power supply chip provided by the prior art.

[0026] Figure 3 A schematic diagram of the structure of a chip provided in an embodiment of the present disclosure.

[0027] Figure 4 A schematic diagram of the structure of a power control circuit provided in an embodiment of the present disclosure.

[0028] Figure 5 A circuit diagram of a power control circuit provided by an embodiment of the present disclosure.

[0029] Figure 6 A schematic diagram of voltages at various nodes in a power control circuit provided by the present disclosure. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0031] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the disclosed subject matter belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" together shall mean that the parts are joined together directly or through one or more intermediate components.

[0032] Reference to "embodiments" in this disclosure means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase "embodiments" in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described in this disclosure may be combined with other embodiments.

[0033] In addition, the terms "first", "second", etc. in the specification and claims of the present disclosure or the above-mentioned drawings are used to distinguish different objects rather than to describe a specific order, and may explicitly or implicitly include one or more of the features.

[0034] The term "and / or" in this disclosure is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists, A and B exist at the same time, and B exists. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0035] In the description of the present disclosure, unless otherwise specified, "plurality" and "at least two" mean more than two (including two), and similarly, "multiple groups" and "at least two groups" mean more than two groups (including two).

[0036] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings.

[0037] Figure 1 A schematic diagram of the structure of a switching power supply chip provided by the prior art, such as Figure 1 As shown, the chip includes a power port VCC and an internal circuit, the negative power terminal of the internal circuit and the first plate of the capacitor C are connected to the chip ground GND_CHIP, the second plate of the capacitor C is connected to the positive power terminal AVDD of the internal circuit, and the positive power terminal AVDD of the internal circuit is connected to the power port VCC through the first switch tube K1 and the second switch tube K2 in sequence, the power port VCC is also connected to the first plate of the off-chip capacitor Co, and the second plate of the off-chip capacitor Co is connected to the PCB ground GND_PCB.

[0038] The internal circuit includes a high-side driver circuit High-Side Driver, a low-side driver circuit Low-Side Driver, an upper tube Hs and a lower tube LS. The high-side driver circuit High-Side Driver receives the upper tube control signal PWM, and the low-side driver circuit Low-Side Driver receives the lower tube control signal Lower tube control signal It is the inverted signal of the upper tube control signal PWM.

[0039] There is parasitic inductance Lpar between PCB routing and package. The chip ground GND_CHIP is connected to the PCB ground GND_PCB through parasitic inductance Lpar, so the chip ground GND_CHIP will be affected by ground bounce noise. Since the power supply of the internal circuit of the chip is composed of the power port VCC and the chip ground GND_CHIP, the ground bounce voltage will be equivalently superimposed on the power supply voltage of the internal circuit, causing the internal circuit of the chip to be subjected to a lot of noise, and the key performance of the chip will be deteriorated, for example, the reference voltage will be offset, the feedback loop will lose control, etc. The low-voltage circuit of the chip is also at risk of being damaged due to contact with excessively high voltage, resulting in reduced chip stability.

[0040] In order to solve the above problems, it is usually necessary to monitor the power stage upper tube control signal PWM. When the upper tube control signal PWM is pulled high, that is, when the upper tube HS is turned on, the shielding signal BLANK is pulled high and delayed for the shielding time Tblank before being pulled low. When the upper tube control signal PWM is pulled low, that is, when the lower tube LS is turned on, the shielding signal BLANK is pulled high and delayed for the shielding time Tblank before being pulled low. Figure 2 As shown, Figure 2 A control timing diagram of a switching power supply chip provided by the prior art.

[0041] The control end of the first switch tube K1 and the control end of the second switch tube K2 receive the shielding signal BLANK, and connect the power port VCC and the power terminal AVDD of the internal circuit when the shielding signal BLANK is a low level signal, and disconnect the connection between the power port VCC and the power terminal AVDD of the internal circuit when the shielding signal BLANK is a high level signal to shield the energy transmission during the ground bounce noise.

[0042] The speed of ground bounce noise is fast, usually up to the order of 10V / ns. If the power stage output signal is used to control the conduction and disconnection of the power path, the control signal needs to be collected from the power stage and transmitted to the vicinity of the power port very quickly. However, the control signal is not easy to collect in many cases.

[0043] For example, in the Peak Current Mode (PCM), the upper tube disconnection control signal is generated by the high-voltage circuit of the chip, and the control signal needs to be transferred to the low voltage through the level shifter, and then transmitted to the power port control circuit. The level transfer process and the delay in the transmission process of the control signal cannot be ignored, so it is difficult to ensure the shielding effect of the ground bounce noise.

[0044] For another example, in a multiphase or distributed power stage circuit, there are multiple output control signals that can generate ground bounce noise. These signals need to be logically integrated to control the conduction and disconnection states of the power ports. However, there is overlap between the multiple control signals, which makes the power supply disconnection logic more complicated. In addition, the simultaneous acquisition and transmission of the output signals of multiple power stages requires more acquisition circuits and routing space, which takes up additional chip area.

[0045] In addition, the waveform amplitude and duration of ground bounce noise are not fixed, which are related to multiple factors such as load current, power stage switching rate and parasitic inductance. The triggering time of ground bounce noise is also different. For example, when the load current is positive, the ground bounce noise is triggered when the upper tube Hs switches, and when the load current is negative, the ground bounce noise is triggered when the lower tube Ls switches.

[0046] If the shielding time is too short and / or the shielding timing is delayed, it will not be enough to shield the ground bounce noise. If the shielding time is too long and / or the shielding timing is advanced, it will shorten the charging time of the power supply within the cycle, thereby reducing the power supply voltage of the chip's internal circuits and weakening key chip performance such as power stage on-resistance. When dealing with ground bounce noise of different durations and / or different triggering timings, additional circuits are required to monitor the positive and negative load current and the speed of the power stage switching, and complex logic is also required to adjust the shielding timing for various situations.

[0047] In summary, in the existing ground bounce noise shielding solution, additional circuits need to be set up to monitor the power stage output signal, collect the power stage output signal and transmit the power stage output signal. Additional circuits need to be set up to monitor the positive and negative of the load current and the speed of the power stage switching rate. Complex logic circuits need to be set up to adjust the shielding timing according to different situations, resulting in a larger chip area.

[0048] In view of this, the present disclosure provides a power control circuit of a chip, including a node voltage generation module, a comparison module and a control module, wherein the node voltage generation module establishes a stable first internal node voltage according to the power port voltage, and establishes a stable second internal node voltage according to the internal circuit voltage, wherein the power port voltage is the voltage of the external power signal received by the power port, and the internal circuit voltage is the power supply voltage of the internal circuit, and the comparison module compares the first internal node voltage and the power port voltage to obtain a first comparison signal, and compares the second internal node voltage and the power port voltage to obtain a second comparison signal, and the control module controls the on-off between the power port and the power supply end of the internal circuit according to the first comparison signal and the second comparison signal, so as to avoid the ground bounce noise in the external power signal from entering the internal circuit, and the stability of the chip can be improved. In this way, the power control circuit can adaptively determine whether the external power signal contains ground bounce noise based on the amplitude and duration of the ground bounce noise, and there is no need to collect the power level output signal, so there is no need to set an additional circuit to monitor the chip power level working state, and there is no need to set an additional circuit to monitor, collect and transmit the power level output signal, which can reduce the circuit complexity, thereby reducing the chip area.

[0049] The technical solution of the present disclosure is described in detail below with reference to several specific embodiments.

[0050] Figure 3 A schematic diagram of the structure of a chip provided in an embodiment of the present disclosure is shown in FIG. Figure 3 As shown, the chip may be a switching power supply chip, which includes a power control circuit 100 , a power port VCC and an internal circuit 200 , wherein the power port VCC is connected to a positive power terminal AVDD of the internal circuit 200 through the power control circuit 100 .

[0051] Among them, the first plate of the off-chip capacitor Co is connected to the power port VCC, and the second plate of the off-chip capacitor Co is connected to the PCB ground GND_PCB to stabilize the power port voltage Vcc. The chip also includes an internal capacitor Ci, the first plate of the internal capacitor Ci is connected to the positive power terminal AVDD of the internal circuit 200, and the second plate of the internal capacitor Ci and the negative power terminal of the internal circuit 200 are connected to the chip ground GND_CHIP to stabilize the power supply voltage Vdd of the internal circuit 200.

[0052] Figure 4A schematic diagram of a power control circuit provided by an embodiment of the present disclosure is shown in FIG. Figure 4 As shown, the power control circuit 100 includes a node voltage generating module 110 , a comparing module 120 and a controlling module 130 .

[0053] Among them, the first input end of the node voltage generating module 110 is connected to the power port VCC, the second input end of the node voltage generating module 110 is connected to the positive power end AVDD of the internal circuit, the first output end of the node voltage generating module 110 is connected to the first input end of the comparison module 120, and the second output end of the node voltage generating module 110 is connected to the second input end of the comparison module 120.

[0054] The third input terminal of the comparison module 120 is connected to the power port VCC, the first output terminal of the comparison module 120 is connected to the first control terminal of the control module 130, the second output terminal of the comparison module 120 is connected to the second control terminal of the control module 130, the input terminal of the control module 130 is connected to the power port VCC, and the output terminal of the control module 130 is connected to the positive power terminal AVDD of the internal circuit.

[0055] The node voltage generating module 110 is configured to establish a stable first internal node voltage Vnode1 according to the power port voltage Vcc, and to establish a stable second internal node voltage Vnode2 according to the internal circuit voltage Vdd, wherein the power port voltage Vcc is the voltage of the external power signal received by the power port VCC, and the internal circuit voltage Vdd is the power voltage of the internal circuit.

[0056] The comparison module 120 is configured to compare the first internal node voltage Vnode1 with the power port voltage Vcc to obtain a first comparison signal CMP1 , and compare the second internal node voltage Vnode2 with the power port voltage Vcc to obtain a second comparison signal CMP2 .

[0057] The control module 130 is configured to control the connection between the power port VCC and the positive power terminal AVDD of the internal circuit according to the first comparison signal CMP1 and the second comparison signal CMP2 to prevent the ground bounce noise in the external power signal from entering the internal circuit.

[0058] For example, see Figure 4 The node voltage generating module 110 includes a first node voltage generating unit 111 and a second node voltage generating unit 112. The input of the first node voltage generating unit 111 is connected to the power port VCC, and the output of the first node voltage generating unit 111 is connected to the first input of the comparison module 120. The first node voltage generating unit 111 can stabilize the power port voltage Vcc to obtain a first internal node voltage Vnode1.

[0059] The input of the second node voltage generating unit 112 is connected to the positive power port AVDD of the internal circuit, and the output of the second node voltage generating unit 112 is connected to the second input terminal of the comparison module 120. The second node voltage generating unit 112 can stabilize the internal circuit voltage Vdd to obtain a second internal node voltage Vnode2.

[0060] Continue to see Figure 4 The comparison module 120 includes a positive comparison unit 121 and a negative comparison unit 122, a first input terminal of the positive comparison unit 121 is connected to a first output terminal of the node voltage generation module 111, a second input terminal of the positive comparison unit 121 is connected to a power supply port VCC, and an output terminal of the positive comparison unit 121 is connected to a first input terminal of the control module 130.

[0061] A first input terminal of the negative comparison unit 122 is connected to the power port VCC, a second input terminal of the negative comparison unit 122 is connected to the second output terminal of the node voltage generation module 110 , and an output terminal of the negative comparison unit 122 is connected to a second input terminal of the control module 130 .

[0062] Exemplarily, the first input terminal of the forward comparison unit 121 is connected to the output terminal of the first node voltage generating unit 111, and the forward comparison unit 121 compares the power port voltage Vcc and the first internal node voltage Vnode1 to determine whether the power port voltage Vcc is less than the sum of the first internal node voltage Vnode1 and the first preset voltage Vth1, thereby obtaining the first comparison signal CMP1.

[0063] When the external power signal received by the power port VCC contains positive ground bounce noise, the positive ground bounce noise voltage is superimposed on the power port voltage Vcc. At this time, the power port voltage Vcc is greater than or equal to the sum of the first internal node voltage Vnode1 and the first preset voltage Vth1, and the obtained first comparison signal CMP1 is a first level signal.

[0064] When the external power signal received by the power port VCC does not contain the positive ground bounce noise, the power port voltage Vcc is not superimposed with the positive ground bounce noise voltage, and at this time, the power port voltage Vcc is less than the sum of the first internal node voltage Vnode1 and the first preset voltage Vth1, and the obtained first comparison signal CMP1 is a second level signal. For example, the first level signal is a high level signal, and the second level signal is a low level signal, or the first level signal is a low level signal, and the second level signal is a high level signal.

[0065] In this way, the forward comparison unit 111 outputs a first level signal when the power port voltage Vcc is greater than or equal to the sum of the first internal node voltage Vnode1 and the first preset voltage Vth1, and outputs a second level signal when the power port voltage Vcc is less than the sum of the first internal node voltage Vnode1 and the first preset voltage Vth1.

[0066] The first input terminal of the negative comparison unit 122 is connected to the output terminal of the second node voltage generating unit 112. The negative comparison unit 122 compares the power port voltage Vcc and the second internal node voltage Vnode2 to determine whether the sum of the power port voltage Vcc and the second preset voltage Vth2 is greater than the second internal node voltage Vnode2, thereby obtaining a second comparison signal CMP2.

[0067] When the external power signal received by the power port VCC contains reverse ground bounce noise, the reverse ground bounce noise voltage is superimposed on the power port voltage Vcc. At this time, the sum of the power port voltage Vcc and the second preset voltage Vth2 is less than or equal to the second internal node voltage Vnode2, and the obtained second comparison signal CMP2 is a first level signal.

[0068] When the external power signal received by the power port VCC does not contain reverse ground bounce noise, the power port voltage Vcc is not superimposed with the reverse ground bounce noise voltage. At this time, the sum of the power port voltage Vcc and the second preset voltage Vth2 is greater than the second internal node voltage Vnode2, and the obtained second comparison signal CMP2 is a second level signal.

[0069] In this way, the negative comparison unit 122 outputs a first level signal when the sum of the power port voltage Vcc and the second preset voltage Vth2 is less than or equal to the second internal node voltage Vnode2, and outputs a second level signal when the sum of the power port voltage Vcc and the second preset voltage Vth2 is greater than the second internal node voltage Vnode2.

[0070] Continue to see Figure 4 The control module 130 includes a positive signal generating unit 131, a negative signal generating unit 132 and a control unit 133. The input end of the positive signal generating unit 131 is connected to the first output end of the comparison module 120, the output end of the positive signal generating unit 131 is connected to the first control end of the control unit 133, the input end of the negative signal generating unit 132 is connected to the second output end of the comparison module 120, the output end of the negative signal generating unit 132 is connected to the second control end of the control unit 133, the input end of the control unit 133 is connected to the power port VCC, and the output end of the control unit 133 is connected to the positive power end AVDD of the internal circuit.

[0071] Exemplarily, the input end of the forward signal generating unit 131 is connected to the output end of the forward comparison unit 121. When the external power signal received by the power port VCC contains positive ground bounce noise, the first comparison signal CMP1 output by the forward comparison unit 121 is a first level signal. At this time, the forward signal generating unit 131 can generate a forward disconnection control signal according to the first comparison signal CMP1.

[0072] When the external power signal received by the power port VCC does not contain forward ground bounce noise, the first comparison signal CMP1 output by the forward comparison unit 121 is a second level signal. At this time, the forward signal generation unit 131 can generate a forward conduction control signal according to the first comparison signal CMP1.

[0073] In this way, the forward signal generating unit 131 can generate a forward control signal according to the first comparison signal CMP1 , wherein the forward control signal includes a forward on control signal and a forward off control signal.

[0074] The input end of the negative signal generating unit 132 is connected to the output end of the negative comparing unit 122. When the external power signal received by the power port VCC contains negative ground bounce noise, the second comparison signal CMP2 output by the negative comparing unit 122 is a first level signal. At this time, the negative signal generating unit 132 can generate a negative disconnection control signal according to the second comparison signal CMP2.

[0075] When the external power signal received by the power port VCC does not contain negative ground bounce noise, the second comparison signal CMP2 output by the negative comparison unit 122 is a second level signal. At this time, the negative signal generation unit 132 can generate a negative conduction control signal according to the second comparison signal CMP2.

[0076] In this way, the negative signal generating unit 132 can generate a negative control signal according to the second comparison signal CMP2 , wherein the negative control signal includes a negative turn-on control signal and a negative turn-off control signal.

[0077] When the external power signal received by the power port VCC contains positive ground bounce noise, the positive control signal generated by the positive signal generating unit 131 is a positive disconnection control signal. At this time, the negative control signal generated by the negative signal generating unit 132 is a negative conduction control signal. The control unit 133 can disconnect the connection between the power port VCC and the positive power terminal AVDD of the internal circuit to prevent the positive ground bounce noise from entering the internal circuit.

[0078] When the external power signal received by the power port VCC contains negative ground bounce noise, the negative control signal generated by the negative signal generating unit 132 is a negative disconnection control signal. At this time, the positive control signal generated by the positive signal generating unit 131 is a forward conduction control signal. The control unit 133 can disconnect the connection between the power port VCC and the positive power terminal AVDD of the internal circuit to prevent the reverse ground bounce noise from entering the internal circuit.

[0079] When the external power signal received by the power port VCC does not contain ground bounce noise, that is, does not contain negative ground bounce noise and positive ground bounce noise, the positive control signal generated by the positive signal generating unit 131 is a positive conduction control signal, and the negative control signal generated by the negative signal generating unit 132 is a negative conduction control signal, and the control unit 133 can conduct the power port VCC and the positive power terminal AVDD of the internal circuit.

[0080] In this way, the control unit 133 turns on the power port VCC and the positive power terminal AVDD of the internal circuit when the positive control signal is a positive conduction control signal and the negative control signal is a negative conduction control signal, and disconnects the connection between the power port VCC and the positive power terminal AVDD of the internal circuit when the positive control signal is a positive disconnection control signal or the negative control signal is a negative disconnection control signal, so as to prevent ground bounce noise from entering the internal circuit.

[0081] In summary, the power control circuit provided by the present disclosure determines whether the external power signal received by the power port contains ground bounce noise based on the voltage difference between the internal node voltage and the power port voltage, and when the external power signal received by the power port contains ground bounce noise, the connection between the power port and the power end of the internal circuit is disconnected to prevent the ground bounce noise from entering the internal circuit, which can improve the stability of the chip. In addition, the power control circuit can adaptively determine whether the external power signal contains ground bounce noise based on the amplitude and duration of the ground bounce noise, without collecting the power level output signal, so there is no need to set up additional circuits to monitor the chip power level working state, and there is no need to set up additional circuits to monitor, collect and transmit the power level output signal, which can reduce the circuit complexity, thereby reducing the chip area.

[0082] In some embodiments, Figure 5 A circuit diagram of a power control circuit provided by an embodiment of the present disclosure is shown in FIG. Figure 5As shown, the forward comparison unit 121 includes a first transistor M1 and a first resistor R1. Among them, the control terminal of the first transistor M1 is connected to the first output terminal of the node voltage generation module 110, the first terminal of the first transistor M1 is connected to the power supply port VCC, the second terminal of the first transistor M1 is connected to the first input terminal of the control module 130 and the first terminal of the first resistor R1, and the second terminal of the first resistor R1 is connected to the chip ground GND_CHIP.

[0083] Exemplarily, the first transistor M1 may be a P-type metal oxide semiconductor field effect transistor (P-Metal Oxide Semiconductor Field Effect Transistor, PMOS). The gate of the first transistor M1 is connected to the output terminal of the first node voltage generation unit 111. Then, the gate voltage of the first transistor M1 is the first internal node voltage Vnode1, the source of the first transistor M1 is connected to the power supply port VCC, so the source voltage of the first transistor M1 is the power supply port voltage Vcc, and the drain of the first transistor M1 is connected to the input terminal of the forward signal generation unit 131 and the first terminal of the first resistor R1. Then, the drain voltage of the first transistor M1 is the first comparison signal.

[0084] The first preset voltage Vth1 is the threshold voltage of the first transistor M1. When the external power supply signal received by the power supply port VCC contains positive ground bounce noise, Vcc - Vnode1 ≥ Vth1, that is, Vcc ≥ Vnode1 + Vth1. The first transistor M1 is in the conducting state, and the drain voltage of the first transistor M1 is pulled up to the power supply port voltage Vcc. Then, the first comparison signal provided by the forward comparison unit 121 to the forward signal generation unit 131 is the first level signal to disconnect the connection between the power supply port VCC and the positive power supply terminal AVDD of the internal circuit.

[0085] When the external power supply signal received by the power supply port VCC does not contain positive ground bounce noise, Vcc - Vnode1 < Vth1, that is, Vcc < Vnode1 + Vth1. The first transistor M1 is in the off state, and the drain voltage of the first transistor M1 is pulled down to the chip ground GND_CHIP. Then, the first comparison signal provided by the forward comparison unit 121 to the forward signal generation unit 131 is the second level signal to support the conduction of the connection between the power supply port VCC and the positive power supply terminal AVDD of the internal circuit.

[0086] In some embodiments, continue to refer to Figure 5The negative comparison unit 122 includes a second transistor M2, a second resistor R2, a third resistor R3 and a first capacitor C1, the control end of the second transistor M2 is connected to the first plate of the first capacitor C1 and the first end of the third resistor R3, the second plate of the first capacitor C1 is connected to the power port VCC, the second end of the third resistor R3 is connected to the positive power supply end AVDD of the internal circuit, the first end of the second transistor M2 is connected to the second output end of the node voltage generating module 110, the second end of the second transistor M2 is connected to the second input end of the control module 130 and the first end of the second resistor R2, and the second end of the second resistor R2 is connected to the chip ground GND_CHIP.

[0087] Exemplarily, the second transistor M2 may be a PMOS, and the gate of the second transistor M2 is connected to the first plate of the first capacitor C1 and the first end of the third resistor R3. When the power port voltage Vcc changes, the presence of the first capacitor C1 causes the gate voltage of the second transistor M2 to follow the power port voltage Vcc. It can be considered that the gate voltage of the second transistor M2 is equal to the power port voltage Vcc in a transient state. When the power port voltage Vcc does not change, the gate voltage of the second transistor M2 is the internal circuit voltage Vdd, and Vdd=Vcc. The gate voltage of the second transistor M2 is equal to the internal circuit voltage Vdd or the power port voltage Vcc in a static state.

[0088] The source of the second transistor M2 is connected to the output end of the second node voltage generating unit 112, and the source voltage of the second transistor M1 is the second internal node voltage Vnode2. The drain of the second transistor M2 is connected to the input end of the negative signal generating unit 132 and the first end of the second resistor R2, and the drain voltage of the second transistor M2 is the second comparison signal.

[0089] The second preset voltage Vth2 is the threshold voltage of the second transistor M2. When the external power signal received by the power port VCC contains negative ground bounce noise, the power port voltage Vcc changes. At this time, the gate voltage of the second transistor M2 is the power port voltage Vcc, Vnode2-Vcc≥Vth2, that is, Vcc+Vth2≤Vnode2, the second transistor M2 is in the on state, and the drain voltage of the second transistor M2 is pulled up to the power port voltage Vcc. The second comparison signal provided by the negative comparison unit 122 to the negative signal generation unit 132 is a first level signal to disconnect the power port VCC from the positive power supply terminal AVDD of the internal circuit.

[0090] When the external power supply signal received by the power supply port VCC does not contain negative ground bounce noise, if the power supply port VCC is used as an input and the positive power supply terminal AVDD of the internal circuit is used as an output, the gate voltage of the second transistor M2 is the power supply port voltage Vcc, and Vnode2 - Vcc < Vth2, that is, Vcc + Vth2 > Vnode2. The second transistor M2 is in an off state, and the drain voltage of the second transistor M2 is pulled down to the chip ground GND_CHIP. Then, the second comparison signal provided by the negative comparison unit 122 to the negative signal generation unit 132 is a second-level signal to support conducting the power supply port VCC and the positive power supply terminal AVDD of the internal circuit.

[0091] When the external power supply signal received by the power supply port VCC does not contain negative ground bounce noise, if the power supply port VCC is used as an output and the positive power supply terminal AVDD of the internal circuit is used as an input, the gate voltage of the second transistor M2 is the internal circuit voltage Vdd, and Vnode2 - Vdd < Vth2, that is, Vdd + Vth2 > Vnode2. The second transistor M2 is in an off state, and the drain voltage of the second transistor M2 is pulled down to the chip ground GND_CHIP. Then, the second comparison signal provided by the negative comparison unit 122 to the negative signal generation unit 132 is a second-level signal to support conducting the power supply port VCC and the positive power supply terminal AVDD of the internal circuit.

[0092] In some embodiments, continue to refer to Figure 5 , the positive signal generation unit 131 includes a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a fourth resistor R4.

[0093] Among them, the control terminal of the third transistor M3 and the control terminal of the fourth transistor M4 are connected to the first output terminal of the comparison module 120. The first terminal of the third transistor M3 and the first terminal of the fifth transistor M5 are connected to the power supply port VCC. The second terminal of the third transistor M3 is connected to the second terminal of the fourth transistor M4 and the control terminal of the fifth transistor M5. The second terminal of the fifth transistor M5 is connected to the first terminal of the fourth resistor R4 and the first control terminal of the control unit 133. The second terminal of the fourth resistor R4 and the first terminal of the fourth transistor M4 are connected to the chip ground GND_CHIP.

[0094] Exemplarily, the third transistor M3 and the fifth transistor M5 are PMOS, and the fourth transistor M4 is NMOS. The source of the third transistor M3 and the source of the fifth transistor M5 are connected to the power supply port VCC. The gate of the third transistor M3 and the gate of the fourth transistor M4 are connected to the output terminal of the positive comparison unit 121. Then, the gate voltage of the third transistor M3 and the gate voltage of the fourth transistor M4 are the first comparison signal.

[0095] The drain of the third transistor M3 is connected to the drain of the fourth transistor M4 and the gate of the fifth transistor M5, the source of the fourth transistor M4 is connected to the chip ground GND_CHIP, the drain of the fifth transistor M5 is connected to the first end of the fourth resistor R4 and the first control end of the control unit 133, and the drain voltage of the fifth transistor M5 is a positive control signal.

[0096] When the external power signal received by the power port VCC contains positive ground bounce noise, the gate voltage of the third transistor M3 and the gate voltage of the fourth transistor M4 are the power port voltage Vcc, the third transistor M3 is in the off state and the fourth transistor M4 is in the on state, and the drain voltage of the fourth transistor M4 is pulled down to the chip ground GND_CHIP. At this time, the gate voltage of the fifth transistor M5 is pulled down to the chip ground GND_CHIP, the fifth transistor M5 is in the on state, and the drain voltage of the fifth transistor M5 is pulled up to the power port voltage Vcc, then the forward control signal provided by the forward signal generating unit 131 to the control unit 133 is a forward disconnection control signal.

[0097] When the external power signal received by the power port VCC does not contain forward ground bounce noise, the gate voltage of the third transistor M3 and the gate voltage of the fourth transistor M4 are the chip ground GND_CHIP, the third transistor M3 is in the on state and the fourth transistor M4 is in the off state, and the drain voltage of the third transistor M3 is pulled up to the power port voltage Vcc. At this time, the gate voltage of the fifth transistor M5 is pulled up to the power port voltage Vcc, the fifth transistor M5 is in the off state, and the drain voltage of the fifth transistor M5 is pulled down to the chip ground GND_CHIP, then the forward control signal provided by the forward signal generation unit 131 to the control unit 133 is a forward conduction control signal.

[0098] In some embodiments, see Figure 5 , the negative signal generating unit 132 includes a sixth transistor M6, a seventh transistor M7, an eighth transistor M8 and a fifth resistor R5.

[0099] Among them, the control end of the sixth transistor M6 and the control end of the seventh transistor M7 are connected to the second output end of the comparison module 120, the first end of the sixth transistor M6 and the first end of the eighth transistor M8 are connected to the positive power supply end AVDD of the internal circuit, the second end of the sixth transistor M6 is connected to the second end of the seventh transistor M7 and the control end of the eighth transistor M8, the second end of the eighth transistor M8 is connected to the first end of the fifth resistor R5 and the second control end of the control unit 133, and the second end of the fifth resistor R5 and the second end of the seventh transistor M7 are connected to the chip ground GND_CHIP.

[0100] Exemplarily, the sixth transistor M6 and the eighth transistor M8 are PMOS, and the seventh transistor M7 is NMOS. The source of the sixth transistor M6 and the source of the eighth transistor M8 are connected to the positive power supply terminal AVDD of the internal circuit, and the gate of the sixth transistor M6 and the gate of the seventh transistor M7 are connected to the output terminal of the negative comparison unit 122, then the gate voltage of the sixth transistor M6 and the gate voltage of the seventh transistor M7 are the second comparison signal.

[0101] The drain of the sixth transistor M6 is connected to the drain of the seventh transistor M7 and the gate of the eighth transistor M8, the source of the seventh transistor M7 is connected to the chip ground GND_CHIP, the drain of the eighth transistor M8 is connected to the first end of the fifth resistor R5 and the second control end of the control unit 133, and the drain voltage of the eighth transistor M8 is a negative control signal.

[0102] When the external power signal received by the power port VCC contains negative ground bounce noise, the gate voltage of the sixth transistor M6 and the gate voltage of the seventh transistor M7 are the internal circuit voltage Vdd, the sixth transistor M6 is in the off state and the seventh transistor M7 is in the on state, and the drain voltage of the seventh transistor M7 is pulled down to the chip ground GND_CHIP. At this time, the gate voltage of the eighth transistor M8 is pulled down to the chip ground GND_CHIP, the eighth transistor M8 is in the on state, and the drain voltage of the eighth transistor M8 is pulled up to the internal circuit voltage Vdd, then the negative control signal provided by the negative signal generating unit 132 to the control unit 133 is a negative disconnection control signal.

[0103] When the external power signal received by the power port VCC does not contain negative ground bounce noise, the gate voltage of the sixth transistor M6 and the gate voltage of the seventh transistor M7 are the chip ground GND_CHIP, the sixth transistor M6 is in the on state and the seventh transistor M7 is in the off state, and the drain voltage of the sixth transistor M6 is pulled up to the internal circuit voltage Vdd. At this time, the gate voltage of the eighth transistor M8 is pulled up to the internal circuit voltage Vdd, the eighth transistor M8 is in the off state, and the drain voltage of the eighth transistor M8 is pulled down to the chip ground GND_CHIP, then the negative control signal provided by the negative signal generating unit 132 to the control unit 133 is a negative conduction control signal.

[0104] In some embodiments, see Figure 5The control unit 133 includes a ninth transistor M9 and a tenth transistor M10. The control end of the ninth transistor M9 is connected to the output end of the positive signal generating unit 131, the control end of the tenth transistor M10 is connected to the output end of the negative signal generating unit 132, the first end of the ninth transistor M9 is connected to the power supply port VCC, the first end of the tenth transistor M10 is connected to the positive power supply terminal AVDD of the internal circuit, and the second end of the ninth transistor M9 is connected to the second end of the tenth transistor M10.

[0105] Exemplarily, the ninth transistor M9 and the tenth transistor M10 are PMOS, the gate of the ninth transistor M9 is connected to the output end of the positive signal generating unit 131, then the gate voltage of the ninth transistor M9 is the positive control signal, the gate of the tenth transistor M10 is connected to the output end of the negative signal generating unit 132, then the gate voltage of the tenth transistor M10 is the negative control signal.

[0106] The source of the ninth transistor M9 is connected to the power port VCC, the source of the tenth transistor M10 is connected to the positive power terminal AVDD of the internal circuit, and the drain of the ninth transistor M9 is connected to the drain of the tenth transistor M10.

[0107] Figure 6 A schematic diagram of voltages at various nodes in a power control circuit provided by the present disclosure, such as Figure 6 As shown, in the time period T0-T1, the external power signal received by the power port VCC does not contain ground bounce noise, the gate voltage of the ninth transistor M9 and the gate voltage of the tenth transistor M10 are pulled down to the chip ground GND_CHIP, and the source-gate voltage VSG_M9 of the ninth transistor M9 and the source-gate voltage VSG_M10 of the tenth transistor M10 are maintained at 5V.

[0108] At this time, the source-gate voltage VSG_M9 of the ninth transistor M9 is greater than the threshold voltage of the ninth transistor M9, the source-gate voltage VSG_M10 of the tenth transistor M10 is greater than the threshold voltage of the tenth transistor M10, the ninth transistor M9 and the tenth transistor M10 are in the on state, so that the power port VCC is connected to the positive power terminal AVDD of the internal circuit, and the internal circuit voltage Vdd is equal to the power port voltage Vcc.

[0109] like Figure 6 As shown, in the time period T1 to T2, the external power signal received by the power port VCC contains negative ground bounce noise, the gate voltage of the tenth transistor M10 is pulled up to the internal circuit voltage Vdd, and the source-gate voltage VSG_M10 of the tenth transistor M10 is reduced to 0, then the source-gate voltage VSG_M10 of the tenth transistor M10 is less than the threshold voltage of the tenth transistor M10, and the tenth transistor M10 is in a disconnected state.

[0110] At this time, the gate voltage of the ninth transistor M9 gradually increases from the chip ground GND_CHIP, and the source-gate voltage VSG_M10 of the ninth transistor M9 gradually decreases, but the ninth transistor M9 still maintains the on state. Since the ninth transistor M9 and the tenth transistor M10 are connected in series, the disconnection of the tenth transistor M10 can disconnect the connection between the power port VCC and the positive power terminal AVDD of the internal circuit, thereby preventing reverse ground bounce noise from entering the internal circuit, and the internal circuit voltage Vdd maintains the voltage of the previous state.

[0111] like Figure 6 As shown, in the time period T2 to T3, the external power signal received by the power port VCC contains positive ground bounce noise, the gate voltage of the ninth transistor M9 is pulled up to the power port voltage Vcc, and the source-gate voltage VSG_M9 of the ninth transistor M9 is reduced to 0, then the source-gate voltage VSG_M9 of the ninth transistor M9 is less than the threshold voltage of the ninth transistor M9, and the ninth transistor M9 is in a disconnected state.

[0112] At this time, the source-gate voltage VSG_M10 of the tenth transistor M10 maintains 0, and the tenth transistor M10 is in a disconnected state, so that the connection between the power port VCC and the positive power terminal AVDD of the internal circuit is disconnected, preventing positive ground bounce noise from entering the internal circuit, and the internal circuit voltage Vdd maintains the voltage of the previous state.

[0113] like Figure 6 As shown, in the time period T3-T4, the external power signal does not contain negative ground bounce noise, the gate voltage of the ninth transistor M9 and the gate voltage of the tenth transistor M10 are pulled down to the chip ground GND_CHIP, and the source-gate voltage VSG_M9 of the ninth transistor M9 and the source-gate voltage VSG_M10 of the tenth transistor M10 gradually rise to 5V.

[0114] In some embodiments, see Figure 5 The first node voltage generating unit 111 includes a sixth resistor R6 and a second capacitor C2, a first end of the sixth resistor R6 is connected to the power port VCC, a second end of the sixth resistor R6 is connected to a first plate of the second capacitor C2 and a first input end of the comparison module 120, and a second plate of the second capacitor C2 is connected to a chip ground GND_CHIP.

[0115] Exemplarily, the second end of the sixth resistor R6 is connected to the input end of the forward comparison unit 121, and the second end of the sixth resistor R6 is connected to the chip ground GND_CHIP through the second capacitor C2, then the second capacitor C2 can stabilize the second end voltage of the sixth resistor R6, that is, it can stabilize the power port voltage Vcc, thereby obtaining the first internal node voltage Vnode1, so as to provide a stable first internal node voltage Vnode1 to the forward comparison unit 121.

[0116] In some embodiments, see Figure 5 The second node voltage generating unit 112 includes a seventh resistor R7 and a third capacitor C3, a first end of the seventh resistor R7 is connected to the positive power supply terminal AVDD of the internal circuit, a second end of the seventh resistor R7 is connected to the first plate of the third capacitor C3 and the second input terminal of the comparison module 120, and a second plate of the third capacitor C3 is connected to the chip ground GND_CHIP.

[0117] Exemplarily, the second end of the seventh resistor R7 is connected to the input end of the negative comparison unit 122, and the second end of the seventh resistor R7 is connected to the chip ground GND_CHIP through the third capacitor C3, then the third capacitor C3 can stabilize the second end voltage of the seventh resistor R7, that is, it can stabilize the internal circuit voltage Vdd, thereby obtaining the second internal node voltage Vnode2, to provide a stable second internal node voltage Vnode2 to the negative comparison unit 122.

[0118] Unless the context clearly indicates otherwise, the singular form of the words used herein and in the appended claims includes the plural form and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the words "comprise" and "include" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive, unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, the "example" is merely illustrative and should not be considered exclusive or comprehensive.

[0119] Several embodiments of the present disclosure are described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the attached claims.

Claims

1. A power control circuit for a chip, characterized in that: The chip includes a power port and an internal circuit, and the power control circuit includes: a node voltage generation module, a comparison module and a control module; The node voltage generating module is configured to establish a stable first internal node voltage according to a power port voltage, and to establish a stable second internal node voltage according to an internal circuit voltage, wherein the power port voltage is a voltage of an external power signal received by the power port, and the internal circuit voltage is a power supply voltage of the internal circuit; The comparison module is configured to compare the first internal node voltage with the power port voltage to obtain a first comparison signal; and compare the second internal node voltage with the power port voltage to obtain a second comparison signal; The control module is configured to control the connection and disconnection between the power port and the power terminal of the internal circuit according to the first comparison signal and the second comparison signal, so as to prevent the ground bounce noise in the external power signal from entering the internal circuit.

2. The power control circuit according to claim 1, characterized in that: The comparison module includes a positive comparison unit and a negative comparison unit; The first input terminal of the forward comparison unit is connected to the first output terminal of the node voltage generation module, the second input terminal of the forward comparison unit is connected to the power port, and the output terminal of the forward comparison unit is connected to the first input terminal of the control module; The first input end of the negative comparison unit is connected to the power port, the second input end of the negative comparison unit is connected to the second output end of the node voltage generation module, and the output end of the negative comparison unit is connected to the second input end of the control module; The forward comparison unit is configured to output a first level signal when the power port voltage is greater than or equal to the sum of the first internal node voltage and a first preset voltage; When the power port voltage is less than the sum of the first internal node voltage and the preset voltage, outputting a second level signal; The negative comparison unit is configured to output the first level signal when the sum of the power port voltage and the second preset voltage is less than or equal to the second internal node voltage; When the sum of the power port voltage and the second preset voltage is greater than the second internal node voltage, the second level signal is output.

3. The power control circuit according to claim 2, characterized in that: The forward comparison unit includes a first transistor and a first resistor; The control end of the first transistor is connected to the first output end of the node voltage generating module, the first end of the first transistor is connected to the power supply port, the second end of the first transistor is connected to the first input end of the control module and the first end of the first resistor, and the second end of the first resistor is connected to the chip ground.

4. The power control circuit according to claim 2, characterized in that: The negative comparison unit includes a second transistor, a second resistor, a third resistor and a first capacitor; The control end of the second transistor is connected to the first plate of the first capacitor and the first end of the third resistor, the second plate of the first capacitor is connected to the power port, the second end of the third resistor is connected to the power end of the internal circuit, the first end of the second transistor is connected to the second output end of the node voltage generating module, the second end of the second transistor is connected to the second input end of the control module and the first end of the second resistor, and the second end of the second resistor is connected to the chip ground.

5. The power control circuit according to claim 1, characterized in that: The control module includes a positive signal generating unit, a negative signal generating unit and a control unit; The input end of the positive signal generating unit is connected to the first output end of the comparison module, the output end of the positive signal generating unit is connected to the first control end of the control unit, the input end of the negative signal generating unit is connected to the second output end of the comparison module, the output end of the negative signal generating unit is connected to the second control end of the control unit, the input end of the control unit is connected to the power port, and the output end of the control unit is connected to the power end of the internal circuit; The forward signal generating unit is configured to generate a forward control signal according to the first comparison signal, wherein the forward control signal includes a forward on control signal and a forward off control signal; The negative signal generating unit is configured to generate a negative control signal according to the second comparison signal, wherein the negative control signal includes a negative conduction control signal and a negative disconnection control signal; The control unit is configured to, when the positive control signal is the positive conduction control signal and the negative control signal is the negative conduction control signal, conduct the power port and the power end of the internal circuit; and when the positive control signal is the positive disconnection control signal or the negative control signal is the negative disconnection control signal, disconnect the power port and the power end of the internal circuit to prevent the ground bounce noise from entering the internal circuit.

6. The power control circuit according to claim 5, characterized in that: The forward signal generating unit includes a third transistor, a fourth transistor, a fifth transistor and a fourth resistor; The control end of the third transistor and the control end of the fourth transistor are connected to the first output end of the comparison module, the first end of the third transistor and the first end of the fifth transistor are connected to the power supply port, the second end of the third transistor is connected to the second end of the fourth transistor and the control end of the fifth transistor, the second end of the fifth transistor is connected to the first end of the fourth resistor and the first control end of the control unit, and the second end of the fourth resistor and the first end of the fourth transistor are connected to the chip ground.

7. The power control circuit according to claim 5, characterized in that: The negative signal generating unit includes a sixth transistor, a seventh transistor, an eighth transistor and a fifth resistor; The control end of the sixth transistor and the control end of the seventh transistor are connected to the second output end of the comparison module, the first end of the sixth transistor and the first end of the eighth transistor are connected to the power supply end of the internal circuit, the second end of the sixth transistor is connected to the second end of the seventh transistor and the control end of the eighth transistor, the second end of the eighth transistor is connected to the first end of the fifth resistor and the second control end of the control unit, and the second end of the fifth resistor and the second end of the seventh transistor are connected to the chip ground.

8. The power control circuit according to claim 5, characterized in that: The control unit includes a ninth transistor and a tenth transistor; The control end of the ninth transistor is connected to the output end of the positive signal generating unit, the control end of the tenth transistor is connected to the output end of the negative signal generating unit, the first end of the ninth transistor is connected to the power supply port, the first end of the tenth transistor is connected to the power supply end of the internal circuit, and the second end of the ninth transistor is connected to the second end of the tenth transistor.

9. The power control circuit according to any one of claims 1 to 8, characterized in that: The node voltage generating module includes a sixth resistor, a seventh resistor, a second capacitor and a third capacitor; The first end of the sixth resistor is connected to the power port, the second end of the sixth resistor is connected to the first plate of the second capacitor and the first input end of the comparison module, the first end of the seventh resistor is connected to the power end of the internal circuit, the second end of the seventh resistor is connected to the first plate of the third capacitor and the second input end of the comparison module, and the second plate of the second capacitor and the second plate of the third capacitor are connected to the chip ground.

10. A chip, characterized in that: It comprises a power port, an internal circuit and the power control circuit according to any one of claims 1 to 9.

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