Direct modulation laser array chip and manufacturing method thereof

Abstract

The invention discloses a direct modulation laser array chip and a manufacturing method thereof, and relates to the technical field of semiconductor laser manufacturing, the direct modulation laser array chip is internally provided with at least two input paths and one output path, and all the input paths are jointly coupled to one output path to form a laser array. Each input path is internally provided with a laser unit and a grating structure capable of forming an equivalent FP feedback cavity with the laser unit, the grating structure is formed by etching a grating material according to a preset pattern, and the grating material is etched to penetrate through the grating structure and extend into the spacing layer below the grating structure; according to the technical scheme, the optical resonance effect can be introduced into the laser array, meanwhile, a plurality of grating structures with different reflectivity are obtained in single etching in a mode of combining electron beam exposure and dry etching, and the process complexity of chip manufacturing is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor laser manufacturing, and in particular to a directly modulated laser array chip and a manufacturing method thereof. Background Art

[0002] High-speed modulated semiconductor lasers are the core components of large-capacity fiber-optic communication systems. There are two important means to improve the capacity of fiber-optic communication systems. One is to use wavelength division multiplexing (WDM) technology, and the other is to increase the modulation bandwidth of semiconductor lasers. Compared with lasers with multiple different wavelengths packaged independently, the use of monolithic integrated multi-wavelength laser chips in fiber-optic communication systems using WDM technology can effectively reduce system power consumption and improve system reliability. The modulation of semiconductor lasers can be achieved through direct modulation and external modulation. Compared with external modulation, directly modulated semiconductor lasers have the advantages of low power consumption, high power and low cost, and are widely used in fiber-optic communication systems. The modulation bandwidth of directly modulated lasers is limited by the relaxation oscillation frequency of the laser. In order to break through this limitation, optical-optical resonance effects or offset load effects can be introduced into the laser to improve the modulation capability of the laser. However, the introduction of effects such as optical-optical resonance requires precise control of parameters such as the reflectivity of the device end face, which is difficult to be compatible with the manufacturing requirements of monolithic integrated multi-wavelength laser array chips. Summary of the invention

[0003] The purpose of the present application is to provide a method for manufacturing a high-speed directly modulated multi-wavelength laser array chip with a bandwidth enhancement effect, in order to solve the problem that the introduction of effects such as optical-optical resonance in the prior art is difficult to be compatible with the manufacturing requirements of a monolithically integrated multi-wavelength laser array chip.

[0004] The technical solution of the present application is: to provide a method for manufacturing a directly modulated laser array chip, the method comprising:

[0005] Step 1, preparing a substrate, setting at least two input paths and one output path on the substrate, all the input paths are coupled to the output path, and a first distributed Bragg reflection area, a laser area, a passive waveguide area and a second distributed Bragg reflection area are sequentially set on a single input path starting from an end far from the coupling position, and the area where the remaining input path is connected to the output path is used as a combiner area;

[0006] Step 2, sequentially growing a quantum well layer, a first spacer layer and a first grating layer on the substrate, and selectively removing the materials grown in the passive waveguide region, the second distributed Bragg reflection region and the combiner region;

[0007] Step 3, in the whole area where the passive waveguide area, the second distributed Bragg reflection area and the combiner area are located, a waveguide layer, a second spacer layer and a second grating layer are sequentially butt-jointedly grown from bottom to top;

[0008] Step 4, using an electron beam to set a predetermined pattern on the first grating layer and the second grating layer, etching downward from the first grating layer and the second grating layer respectively according to the predetermined pattern, etching through the first grating layer and the second grating layer and extending to the first spacer layer and the second spacer layer below respectively, to form a first patterned grating layer and a second patterned grating layer;

[0009] Step 5, sequentially growing a cladding layer and a contact layer on the entire functional layer;

[0010] Step 6: fabricate a first electrode on the contact layer of the laser region, and fabricate a second electrode on the contact layer of the second distributed Bragg reflection region.

[0011] Furthermore, step 4 specifically includes: coating a layer of photoresist at least above the functional layer in the area where the input path is located, using an electron beam to expose and scan the surface of the photoresist according to a predetermined pattern, performing a development operation after exposure to form a predetermined pattern, and then etching the material layer not protected by the photoresist by dry etching, so that the material layer protected by the photoresist forms a patterned structure consistent with the predetermined pattern, and removing the remaining photoresist after the etching is completed.

[0012] Furthermore, step 2 also includes: growing a buffer layer on the substrate, wherein the buffer layer is located between each functional layer and the substrate.

[0013] Furthermore, step 6 also includes: removing the contact layer material of the first distributed Bragg reflection region.

[0014] Furthermore, in step 1, at least 3, 4 or 5 input paths are set.

[0015] Furthermore, the thickness of the second patterned grating layer is smaller than the thickness of the first patterned grating layer.

[0016] The technical solution of the present application also provides a directly modulated laser array chip, the chip comprising: a substrate, a quantum well layer, a first spacer layer, a first patterned grating layer, a waveguide layer, a second spacer layer and a second patterned grating layer;

[0017] The quantum well layer, the first spacer layer and the first patterned grating layer are sequentially arranged from bottom to top in the overall area where the first distributed Bragg reflection region and the laser region are located, wherein the first patterned grating layer is formed by etching the grating material arranged above the first spacer layer according to a predetermined pattern;

[0018] The waveguide layer, the second spacer layer and the second patterned grating layer are sequentially arranged from bottom to top in the overall area where the passive waveguide area, the second distributed Bragg reflection area and the combiner area are located by butt-jointed growth, wherein the second patterned grating layer is formed by etching the grating material arranged above the second spacer layer according to a predetermined pattern.

[0019] Furthermore, the thickness of the second patterned grating layer is smaller than the thickness of the first patterned grating layer.

[0020] Furthermore, the directly modulated laser array chip further includes: a cladding layer and a contact layer, and the cladding layer and the contact layer are sequentially arranged above other functional layers from bottom to top.

[0021] Furthermore, the directly modulated laser array chip further includes a buffer layer, a first electrode and a second electrode;

[0022] The buffer layer is arranged between the substrate and other functional layers;

[0023] The first electrode and the second electrode are respectively arranged above the contact layer, wherein the first electrode is located in the laser region and the second electrode is located in the second distributed Bragg reflection region. The first electrode and the second electrode are respectively used to connect different external power supply terminals and inject current into the functional layer.

[0024] The beneficial effects of this application are:

[0025] First, the technical solution in the present application arranges laser units with different grating periods in different input paths by combining electron beam exposure technology and dry etching technology, and arranges the corresponding second patterned grating layer according to the working wavelength of the laser unit, wherein an equivalent FP feedback cavity can be formed between the second patterned grating layer and the laser unit, providing a basis for introducing the optical-optical resonance effect; the technical solution in the present application can introduce the optical-optical resonance effect in a monolithic integrated multi-wavelength laser array chip by arranging different laser units and corresponding second patterned grating layers, wherein for a single input path, the wavelength of the light wave emitted by the laser unit resonates with one of the multiple wavelengths existing in the FP feedback cavity, which can produce the optical-optical resonance effect, and effectively improve the modulation bandwidth of the direct-modulated laser.

[0026] The technical solution in the present application can accurately control the reflectivity of the grating structure by controlling the thickness of its material layer when setting the second patterned grating layer, and the control process does not affect its integration process with the combiner; the technical solution in the present application can be compatible with the manufacturing requirements of a monolithically integrated multi-wavelength laser array chip, and introduces an optical-optical resonance effect in the laser array unit by providing feedback using a DBR reflector, thereby realizing the monolithic integration of a high-bandwidth directly modulated laser array and a passive waveguide combiner; compared with the prior art process that requires the grating matched with the laser unit to be individually controlled and etched multiple times, the technical solution in the present application can set grating layers of different thicknesses according to specific needs, so as to obtain grating structures with different reflectivities in a single etching, which is beneficial to reducing the process complexity of chip manufacturing and simplifying the steps of the entire manufacturing process.

[0027] Second, the technical solution in this application not only introduces the optical resonance effect in the laser array of the chip, but also sets the reflectivity of the grating in the DBR2 area between 2% and 10%, so that the reflectivity of this part of the grating structure is lower than that of the grating in the DBR1 and DFB areas, enhancing the optical resonance effect and maximizing the available optical power of the chip. The technical solution in this application also sets a grating structure with the same period as the laser grating in the DBR1 area, and uses the grating structure in the DBR1 area to provide optical feedback, thereby improving the side mode suppression ratio and modulation bandwidth of the laser, and providing a high-efficiency and high-reliability solution for the optical fiber communication system. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The advantages of the above and / or additional aspects of the present application will become apparent and easily understood in the description of the embodiments in conjunction with the following drawings, in which:

[0029] Figure 1 is a schematic structural diagram of a directly modulated laser array chip according to an embodiment of the present application;

[0030] Figure 2 It is a chip structure in different steps prepared by a method for manufacturing a directly modulated laser array chip according to an embodiment of the present application.

[0031] Among them, 10-substrate, 20-buffer layer, 30-quantum well layer, 41-first spacer layer, 51-first patterned grating layer, 60-waveguide layer, 42-second spacer layer, 52-second patterned grating layer, 70-cladding layer, 80-contact layer, 91-first electrode, 92-second electrode. DETAILED DESCRIPTION

[0032] In order to more clearly understand the above-mentioned purposes, features and advantages of the present application, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. It should be noted that the embodiments of the present application and the features in the embodiments can be combined with each other without conflict.

[0033] In the following description, many specific details are elaborated to facilitate a full understanding of the present application. However, the present application may also be implemented in other ways different from those described herein. Therefore, the protection scope of the present application is not limited to the specific embodiments disclosed below.

[0034] Taking the InP-based material system as an example, a direct modulation laser array chip and a manufacturing method thereof in an embodiment of the present invention are generally introduced below.

[0035] like Figure 1 to Figure 2 As shown, this embodiment provides a directly modulated laser array chip, which directly modulated laser array chip includes: a substrate 10, a quantum well layer 30, a spacer layer 41, a first patterned grating layer (G1) 51, a waveguide layer 60, a second spacer layer 42, a second patterned grating layer (G2) 52, a cladding layer 70 and a contact layer 80.

[0036] At least two input paths and one output path are divided on the substrate 10, and all the input paths are coupled to one output path. A single input path is divided into a first distributed Bragg reflection (DBR1) region, a laser (DFB) region, a passive waveguide (WG) region, and a second distributed Bragg reflection (DBR2) region in sequence from the end far away from the coupling position. The region where the input path is connected to the output path is a combiner (CB) region, wherein adjacent regions are closely connected.

[0037] The quantum well layer 30, the first spacer layer 41 and the first patterned grating layer 51 are sequentially arranged from bottom to top in the overall area where the first distributed Bragg reflection region and the laser region are located, wherein the first patterned grating layer 51 is formed by etching the grating material arranged above the first spacer layer 41 according to a predetermined pattern.

[0038] The waveguide layer 60, the second spacer layer 42 and the second patterned grating layer 52 are sequentially arranged from bottom to top in the overall area where the passive waveguide area, the second distributed Bragg reflection area and the combiner area are located by a butt-jointed growth method, wherein the second patterned grating layer 52 is formed by etching a grating material arranged above the second spacer layer 42 according to a predetermined pattern, and the thickness of the second patterned grating layer 52 is less than the thickness of the first patterned grating layer 51.

[0039] It should be noted that before setting each functional layer, the thickness of the first patterned grating layer 51 and the second patterned grating layer 52 need to be determined first. In this embodiment, the thickness of the second patterned grating layer 52 is set to be smaller than the thickness of the first patterned grating layer 51. When the second spacer layer 42 and the second patterned grating layer 52 are sequentially butt-grown, the thickness of the second spacer layer 42 can be adjusted according to the thickness of the second patterned grating layer 52, so that the upper ends of the first patterned grating layer 51 and the second patterned grating layer 52 are flush with each other, so that when the grating materials of the two layers are subsequently etched, the position reached by the lower end of the etched structure can be accurately controlled.

[0040] The cladding layer 70 and the contact layer 80 are sequentially arranged on top of other functional layers from bottom to top.

[0041] The directly modulated laser array chip further includes a buffer layer 20 , a first electrode 91 and a second electrode 92 .

[0042] The buffer layer 20 is arranged between the substrate 10 and other functional layers, that is, the buffer layer 20 is arranged on the substrate 10 and is located below the quantum well layer 30 and the waveguide layer 60; the buffer layer 20 is used to alleviate the problem of lattice mismatch between the substrate 10 and the functional layer, and reduce stress and manufacturing defects.

[0043] The first electrode 91 and the second electrode 92 are respectively arranged above the contact layer 80, wherein the first electrode 91 is located in the laser region and the second electrode 92 is located in the second distributed Bragg reflection region; the first electrode 91 and the second electrode 92 are respectively used to connect to different external power supply terminals and provide current to the laser to excite the gain material below, thereby realizing the generation of photons and light amplification.

[0044] In this embodiment, the functional layer refers to various material layers with certain functions arranged on the substrate 10, namely, the buffer layer 20, the quantum well layer 30, the spacer layer 41, the first patterned grating layer 51, the waveguide layer 60, the second spacer layer 42, the second patterned grating layer 52, the cladding layer 70 and the contact layer 80, and these material layers are all functional layers.

[0045] In this embodiment, the butt-joint growth is to grow another different material on the edge of the already grown material layer by using a specific epitaxial growth technology so that the two materials are seamlessly joined together.

[0046] It should be noted that when an InP-based material system is selected, the substrate 10 is an InP substrate, the buffer layer 20 is an InP buffer layer material, the quantum well layer 30 is an InGaAsP (indium gallium arsenic phosphide) or InGaAlAs (indium gallium aluminum arsenic) quantum well material, the first spacer layer 41 and the second spacer layer 42 are both InP spacer materials, the first patterned grating layer 51 and the second patterned grating layer 52 are both InGaAsP grating materials, the waveguide layer 60 is an InGaAsP waveguide core material, the cladding is 70InP cladding material, and the contact layer 80 is an InGaAs contact layer material.

[0047] like Figure 2 (a) to Figure 2 As shown in (d) in the figure, this embodiment provides a method for manufacturing a directly modulated laser array chip, comprising:

[0048] Step 1, preparing a substrate 10, dividing at least two input paths and one output path on the substrate 10, all the input paths are coupled to the output path, and a closely connected first distributed Bragg reflection area, a laser area, a passive waveguide area, and a second distributed Bragg reflection area are sequentially arranged on a single input path from an end far from a coupling position, and the area where the remaining input path is connected to the output path is used as a combiner area;

[0049] Step 2, growing a long buffer layer 20, a quantum well layer 30, a first spacer layer 41 and a first grating layer on the substrate 10 from bottom to top, and selectively removing materials of the quantum well layer 30, the first spacer layer 41 and the first grating layer in the passive waveguide region, the second distributed Bragg reflection region and the combiner region;

[0050] Step 3, in the whole area where the passive waveguide area, the second distributed Bragg reflection area and the combiner area are located, the waveguide layer 60, the second spacer layer 42 and the second grating layer are sequentially butt-jointedly grown from bottom to top, wherein the thickness of the second grating layer is smaller than the thickness of the first grating layer;

[0051] Step 4, using electron beam exposure technology to set a predetermined grating pattern on the first grating layer and the second grating layer, and etching downward from the first grating layer and the second grating layer respectively according to the predetermined grating pattern, etching through the first grating layer and the second grating layer and extending to the first spacer layer 41 and the second spacer layer 42 below, respectively, to form a first patterned grating layer 51 and a second patterned grating layer 52;

[0052] Specifically, a layer of photoresist is coated on at least the functional layer in the area where the input path is located, and an electron beam is used to expose and scan the surface of the photoresist according to a predetermined pattern. After exposure, a development operation is performed to form a predetermined pattern (i.e., the required grating pattern), and then the material layer not protected by the photoresist is etched by dry etching, and the material layer protected by the photoresist forms a patterned structure consistent with the predetermined pattern. After the etching is completed, the remaining photoresist is removed.

[0053] Step 5, growing a cladding layer 70 and a contact layer 80 sequentially from bottom to top over the entire functional layer;

[0054] Step 6: For each input path, a first electrode 91 is formed on the contact layer 80 of the laser region, a second electrode 92 is formed on the contact layer 80 of the second distributed Bragg reflection region, and the contact layer material of the first distributed Bragg reflection region is removed.

[0055] In this embodiment, electron beam lithography (EBL) is a high-resolution processing method for manufacturing micro-nano structures, which is commonly used in the fields of semiconductor manufacturing and nanotechnology. When using electron beam lithography to make a pattern on a certain material layer, photoresist can be used as an auxiliary, and a high-energy electron beam is used to scan the photoresist. After development, the desired pattern is formed. Electron beam lithography can engrave very small feature sizes, which makes it suitable for the manufacture of grating structures.

[0056] In the above step 3, the thickness of the first patterned grating layer 51 and the second patterned grating layer 52 can be set according to the specific required reflectivity, wherein the reflectivity increases when the thickness of the grating layer increases. In this embodiment, when multiple input paths are set on the substrate 10, a chip with a grating structure array with different reflectivities can be obtained by setting grating layers of different thicknesses on different input paths of the substrate 10. It can be seen that the method of the present invention can achieve grating structures with different reflectivities in a single etching, which is conducive to reducing the process complexity of chip manufacturing.

[0057] Since the substrate 10 is provided with at least two input paths, the laser units in the prepared chip (i.e., the unit structure formed by the materials of the DBR1 region and the DFB region on a single input path) are array-divided. In the above step 4, for each laser unit in the array, during the preparation process, the grating periods of the DBR1 region and the DFB region are set to a consistent period, and the grating periods between different laser units are set to a gradually changing period, so that a chip with lasers having different Bragg wavelengths (i.e., the emission wavelength or working wavelength of the laser) can be obtained; a reasonable grating period is designed so that the Bragg wavelengths of the gratings in the DBR2 region are respectively aligned with the working wavelengths of the laser units; specifically, after the working wavelength of the laser unit is determined, the grating period of the gratings in the DBR2 region is set based on the working wavelength, so that the Bragg wavelength of the gratings in the DBR2 region is matched with the working wavelength of the laser unit (i.e., the Bragg wavelength of the gratings in the DBR2 region is consistent with or close to the working wavelength of the corresponding laser unit), so that the gratings in the DBR2 region can reflect the light waves of a specific wavelength emitted by the laser, ensuring that each laser unit can stably emit light waves of a desired wavelength.

[0058] In this embodiment, for each laser unit of the chip, the Bragg wavelength of the grating in the DFB laser region is used to determine the operating wavelength of the laser unit (i.e., the light emission wavelength of the laser), and the grating in the DBR1 region is used to provide optical feedback (the grating structure in the DBR1 region will reflect part of the light emitted by the laser back to the gain medium, which can enhance the light intensity in the gain medium, thereby improving the luminous efficiency and output power of the laser unit). All the provided optical feedback is conducive to improving the side mode suppression ratio of the laser spectrum (the side mode suppression ratio is an important indicator for evaluating laser performance. The higher the side mode suppression ratio, the purer the output signal of the laser and the smaller the interference). An equivalent FP feedback cavity (Fabry-Pérot, Fabry-Pérot cavity, which is an optical feedback structure, usually composed of two parallel reflectors or gratings, and used to enhance the light output of a specific wavelength in lasers and optical devices) can be formed between the DBR2 region grating and the DFB laser. Since the laser units are distributed in an array, there are a series of FP modes in the corresponding device spectrum, in which each input path in the laser array chip is independent. For a single input path, when the DFB emission wavelength (mode) of the laser resonates with one of the multiple wavelengths (modes) in one of the FP feedback cavities, a so-called optical-optical resonance effect will be generated. Such an optical-optical resonance effect can effectively improve the modulation bandwidth of the direct-modulated laser.

[0059] In this embodiment, the reflectivity of the grating in the DBR2 region is between 2% and 10%, which is lower than the reflectivity of the grating in the DBR1 and DFB regions. At this time, the optical resonance effect is most significant. At the same time, such a low reflectivity is conducive to improving the available optical power of the device. The reflectivity of the grating in the DBR1 and DFB regions can be set according to actual needs, and it is ensured to be higher than the reflectivity of the grating in the DBR2 region. The electrode made in the DBR2 region is used to tune its reflection peak wavelength by injecting current, so that the laser can better adapt to the external environment or changing application requirements.

[0060] During the entire manufacturing process, the patterned grating structure on the input path of the array distribution can be obtained by a single etching method after growing the material, which is beneficial to reducing the process complexity of chip manufacturing.

[0061] In this embodiment, for a single input path, the electrode of the laser zone can be connected to the external current input end path. Under the action of the external current, the laser unit generates a light wave, and the signal of the light wave can be transmitted to the waveguide output through the waveguide layer 60 for output; the number of laser channels in the device is greater than or equal to 2, preferably, greater than or equal to 3, 4, 5, 6, 7, 8, 9 or 10.

[0062] The steps in this application can be adjusted in order, combined, and deleted according to actual needs.

[0063] The units in the device of the present application can be combined, divided and deleted according to actual needs.

[0064] Although the present application is disclosed in detail with reference to the accompanying drawings, it should be understood that these descriptions are merely exemplary and are not intended to limit the application of the present application. The scope of protection of the present application is defined by the appended claims and may include various modifications, alterations and equivalents made to the invention without departing from the scope and spirit of the present application.

Claims

1. A method for manufacturing a directly modulated laser array chip, characterized in that: The method includes: Step 1, preparing a substrate (10), setting at least two input paths and one output path on the substrate (10), all the input paths are coupled to the output path, and a first distributed Bragg reflection area, a laser area, a passive waveguide area and a second distributed Bragg reflection area are sequentially set on a single input path starting from an end far from the coupling position, and the area where the remaining input path is connected to the output path is used as a combiner area; Step 2, sequentially growing a quantum well layer (30), a first spacer layer (41) and a first grating layer on the substrate (10), and selectively removing materials grown in the passive waveguide region, the second distributed Bragg reflection region and the combiner region; Step 3, in the whole area where the passive waveguide area, the second distributed Bragg reflection area and the combiner area are located, a waveguide layer (60), a second spacer layer (42) and a second grating layer are sequentially butt-jointedly grown from bottom to top; Step 4, using an electron beam to set a predetermined pattern on the first grating layer and the second grating layer, etching downwards from the first grating layer and the second grating layer respectively according to the predetermined pattern, etching through the first grating layer and the second grating layer and extending to the first spacer layer (41) and the second spacer layer (42) below respectively, to form a first patterned grating layer (51) and a second patterned grating layer (52); Step 5, sequentially growing a cladding layer (70) and a contact layer (80) on the entire functional layer; Step 6: For each input path, a first electrode (91) is formed on the contact layer (80) of the laser region, and a second electrode (92) is formed on the contact layer (80) of the second distributed Bragg reflection region.

2. The method for manufacturing a directly modulated laser array chip according to claim 1, characterized in that: The step 4 specifically includes: A layer of photoresist is coated on at least the functional layer in the area where the input path is located, and an electron beam is used to expose and scan the surface of the photoresist according to a predetermined pattern. After exposure, a development operation is performed to form a predetermined pattern, and then the material layer not protected by the photoresist is etched by dry etching. The material layer protected by the photoresist forms a patterned structure consistent with the predetermined pattern. After the etching is completed, the remaining photoresist is removed.

3. The method for manufacturing a directly modulated laser array chip according to claim 1, characterized in that: The step 2 further comprises: growing a buffer layer (20) on the substrate (10), wherein the buffer layer (20) is located between each functional layer and the substrate (10).

4. The method for manufacturing a directly modulated laser array chip according to claim 1, characterized in that: The step 6 also includes: removing the contact layer material in the first distributed Bragg reflection region.

5. The method for manufacturing a directly modulated laser array chip according to claim 1, characterized in that: In step 1, at least 3, 4 or 5 input paths are set.

6. The method for manufacturing a directly modulated laser array chip according to claim 1, characterized in that: The thickness of the second patterned grating layer (52) is smaller than the thickness of the first patterned grating layer (51).

7. A directly modulated laser array chip manufactured by the manufacturing method of the directly modulated laser array chip according to any one of claims 1 to 6, characterized in that: The directly modulated laser array chip comprises: a substrate (10), a quantum well layer (30), a first spacer layer (41), a first patterned grating layer (51), a waveguide layer (60), a second spacer layer (42) and a second patterned grating layer (52); The quantum well layer (30), the first spacer layer (41) and the first patterned grating layer (51) are sequentially arranged from bottom to top in the overall area where the first distributed Bragg reflection area and the laser area are located, wherein the first patterned grating layer (51) is formed by etching a grating material arranged above the first spacer layer (41) according to a predetermined pattern; The waveguide layer (60), the second spacer layer (42) and the second patterned grating layer (52) are sequentially arranged from bottom to top in the overall area where the passive waveguide area, the second distributed Bragg reflection area and the combiner area are located by a butt-jointed growth method, wherein the second patterned grating layer (52) is formed by etching a grating material arranged above the second spacer layer (42) according to a predetermined pattern.

8. The directly modulated laser array chip according to claim 7, characterized in that: The thickness of the second patterned grating layer (52) is smaller than the thickness of the first patterned grating layer (51).

9. The directly modulated laser array chip according to claim 7, characterized in that: The directly modulated laser array chip further comprises: a cladding layer (70) and a contact layer (80), wherein the cladding layer (70) and the contact layer (80) are sequentially arranged above each other functional layer from bottom to top.

10. The directly modulated laser array chip according to claim 9, characterized in that: The directly modulated laser array chip further comprises a buffer layer (20), a first electrode (91) and a second electrode (92); The buffer layer (20) is arranged between the substrate (10) and other functional layers; The first electrode (91) and the second electrode (92) are respectively arranged above the contact layer (80), wherein the first electrode (91) is located in the laser region, and the second electrode (92) is located in the second distributed Bragg reflection region, and the first electrode (91) and the second electrode (92) are respectively used to connect to different external power supply terminals and inject current into the functional layer.

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