General continuous working test device for IGBT (Insulated Gate Bipolar Translator)

Abstract

An IGBT general continuous work test device mainly comprises a host, a mother board, a daughter board, a load inductor, a general DC power supply, an oscilloscope and a current probe. And the host is connected with the mother board to realize power supply to the mother board and communication with the mother board. The mother board mainly comprises an FPGA (Field Programmable Gate Array) part, a voltage conditioning circuit and three groups of level conversion amp; a double-path isolation driving circuit and a resistor amp; amp of a TVS chain; and the module identification circuit and the daughter board interface are simultaneously connected with the oscilloscope, so that the transmission of the conditioned voltage signal is realized. And the daughter board is connected with the mother board to realize transmission of low-voltage control signals and high-voltage electricity, and is connected with the load inductor to realize transmission of inverted high-voltage alternating current. The IGBT general continuous work test device provided by the invention can be compatible with IGBTs of different models to carry out full-bridge and half-bridge continuous work tests, the voltage conditioning proportion and the variable pulse width PWM wave frequency required to be loaded by the tests can be set in a program control manner, and meanwhile, the device has an error prevention function.

Description

Technical Field

[0001] The invention relates to an IGBT universal continuous operation test device, belonging to the technical field of IGBT testing. Background Art

[0002] IGBT (Insulated Gate Bipolar Transistor) is an important power electronic device because of its high input impedance and fast switching speed. As a power semiconductor device, IGBT can be used to control current amplitude, current frequency, electronic switching, etc., and is an important component in the field of power conversion and application. In recent years, IGBT has been widely used in new energy vehicles, photovoltaics, energy storage and other fields, and has huge market economic prospects. Therefore, it is important to establish a universal and reliable IGBT verification device.

[0003] At present, the verification devices and verification methods for IGBT are mainly focused on double pulse tests, which are mainly used to test the switch characteristics of IGBT such as on-time, on-delay time, off-time, and off-delay time. However, there are few studies on the verification devices and verification methods for IGBT working stability and reliability. At the same time, the verification devices are mainly for specific IGBT models, which are special devices and lack universality. Therefore, a universal IGBT reliability verification device that is compatible with full-bridge, half-bridge and multiple IGBT models is needed. Summary of the invention

[0004] The technical problem to be solved by the present invention is: to overcome the shortcomings of the prior art and provide an IGBT universal continuous operation test device, which not only realizes continuous operation tests on full-bridge and half-bridge IGBTs to verify the reliability and stability of the IGBT, but also makes the device compatible with multiple IGBT models through circuit design and has universality.

[0005] The purpose of the present invention is achieved through the following technical solutions:

[0006] The invention discloses an IGBT universal continuous operation test device, comprising a host, a motherboard, a daughterboard, a load inductor, an integrated control cable, a DC power cable, a short power cable, a load cable, a universal DC power supply, an oscilloscope, a current probe, a 220VAC power wire and a power cord.

[0007] The 220VAC power cord supplies power to the host and oscilloscope respectively, and the power cord is powered by a DC power supply. The host is connected to the motherboard through an integrated control cable to realize power supply to the motherboard and communication with the motherboard. The motherboard is connected to the oscilloscope through an SMA cable to realize the transmission of conditioned voltage signals. The daughterboard is connected to the motherboard through a connector to realize the transmission of low-voltage control signals and high-voltage electricity, and is connected to the load inductor through a load cable to realize the transmission of high-voltage AC power after inversion. The DC power supply is connected to the daughterboard through a DC power cable and a short power cable to realize the transmission of high-voltage DC power. The current probe connects the load cable and the oscilloscope to realize the monitoring of the load current. When conducting a full-bridge IGBT continuous operation test, only one full-bridge daughterboard is connected to the motherboard; when conducting a half-bridge IGBT continuous operation test, two identical half-bridge daughterboards are connected to the motherboard at the same time.

[0008] Preferably, the host includes: a human-machine interface, an industrial control computer, and a programmable power supply.

[0009] The human-machine interface consists of a keyboard, a monitor, and a mouse. The industrial computer is used to load the application software of the test device. It uses a common single-board computer or an embedded industrial computer on the market. It is small in size and light in weight, laying the foundation for the miniaturization of the host. It has the same communication interface as the programmable power supply and the motherboard communication circuit. The programmable power supply provides the motherboard with the 24VDC power required for operation. The start and stop of the programmable power supply, as well as the output voltage and current, are all realized under the control of the industrial computer.

[0010] Preferably, the motherboard includes: a DC / DC power supply circuit, a reset circuit, a communication circuit, an FPGA part, a status indication circuit, a temperature monitoring circuit, a voltage conditioning circuit, 3 sets of level conversion & dual-channel isolation drive circuits, a resistor & TVS chain & module identification circuit, and a daughterboard interface.

[0011] The DC / DC power supply circuit has an isolated 24VDC to 5VDC circuit, which provides working power for each part of the motherboard, as well as other power supply circuits required for 5VDC conversion to FPGA. The communication circuit realizes data interaction between the motherboard FPGA and the host, and the FPGA part is the control core of the motherboard.

[0012] The status indication circuit is controlled by FPGA to display whether each arm of the full-bridge or half-bridge IGBT has any fault during the test, as well as the fault status. When a bridge arm is in normal state, short circuit fault, or undervoltage fault, the corresponding indicator light is off, always on, or flashing.

[0013] The temperature monitoring circuit consists of a current source, an operational amplifier, a voltage reference, AD acquisition, etc. It is used to monitor the temperature of the full-bridge IGBT with an NTC resistor under the control of the FPGA to ensure that the full-bridge IGBT with an NTC resistor is protected and shut down when the temperature is too high.

[0014] Preferably, the reset circuit is implemented by a push button switch, one end of the switch is grounded, and the other end is simultaneously connected to a pull-up resistor and a general IO pin of the FPGA.

[0015] The reset circuit is used to reset the FPGA and the status indicator circuit by manually pressing the switch when the FPGA detects a full-bridge or half-bridge IGBT test fault and controls the status indicator to work. For this key reset circuit, the FPGA program is designed with a debounce function. When the FPGA detects that the reset pin is at a low level and the duration reaches 0.5s, the program is reset and the status indicator is turned off.

[0016] Preferably, the voltage conditioning circuit includes: a full-bridge IGBT voltage conditioning circuit, a half-bridge IGBT voltage conditioning circuit, and a standard SMA interface.

[0017] The full-bridge IGBT voltage conditioning circuit includes one set of conditioning circuits for the U phase, V phase, and W phase to the high-voltage DC power supply ground. Each set of conditioning circuits can be programmed to set the conditioning ratio, and the conditioning ratio is preferably 1 / 40 or 1 / 60 to adapt to the output voltage collection of full-bridge IGBTs of different models and rated voltages during continuous operation.

[0018] The half-bridge IGBT voltage conditioning circuit includes a voltage conditioning circuit between the first half-bridge IGBT output point and the second half-bridge IGBT output point. The conditioning circuit can programmably set the conditioning ratio, and the conditioning ratio is preferably 1 / 60 or 1 / 80 to adapt to the output voltage collection of half-bridge IGBTs of different models and different rated voltages during continuous operation.

[0019] The standard SMA interface enables the high voltage on the motherboard to be conditioned and then output to the oscilloscope through the SMA cable.

[0020] Preferably, the level conversion & dual-channel isolation drive circuit includes: 1#, 2#, and 3# level conversion & dual-channel isolation drive circuits.

[0021] Circuit 1# is used to realize the switch control of the first upper and lower bridge arms of the full-bridge IGBT, or the switch control of the upper and lower bridge arms of the first half-bridge IGBT; circuit 2# is used to realize the switch control of the second upper and lower bridge arms of the full-bridge IGBT; circuit 3# is used to realize the switch control of the third upper and lower bridge arms of the full-bridge IGBT, or the switch control of the upper and lower bridge arms of the second half-bridge IGBT. In this way, the universality of the drive control of the full-bridge IGBT and the half-bridge IGBT is realized.

[0022] Preferably, the resistor & TVS chain & module identification circuit includes: an on-resistance circuit, an off-resistance circuit, a protection resistor circuit, a TVS chain circuit, and a module identification circuit;

[0023] In order to take into account the continuous working test of full-bridge, half-bridge and different types of IGBTs, the resistor & TVS chain & module identification circuit functions are integrated on an independent small board. The board matches the jack on the motherboard through the pins to achieve flexible replacement of the board. A set of universal test equipment corresponds to multiple resistor & TVS chain & module identification circuit boards. The turn-on resistor, turn-off resistor, protection resistor, TVS chain, and module identification circuit on each board are determined according to the parameters of the full-bridge or half-bridge IGBT to be tested, thereby being compatible with the tests of full-bridge and half-bridge IGBTs of different models, and realizing the versatility of the test equipment.

[0024] The module identification circuit is designed to support 6-bit high and low level generation circuits. The FPGA can thus recognize that the board has 2 to the power of 6 states, that is, it supports the testing of 64 different types of full-bridge and half-bridge IGBTs. The module identification circuit can also be designed as 8-bit, 10-bit, or even more-bit high and low level generation circuits as needed.

[0025] Preferably, the daughter board interface includes: 1# full-bridge daughter board interface, 2# and 3# half-bridge daughter board interfaces.

[0026] The daughterboard interface is a pin-type or hole-type connector. There is one connector related to the full-bridge daughterboard, which is designed as a hole type; there are two connectors related to the half-bridge daughterboard, which are designed as pin-type. The two connector models are exactly the same, which is convenient for the random insertion of two half-bridge daughterboards of the same model. The connectors related to the full-bridge and half-bridge daughterboards are designed with different hole and pin types respectively to avoid mis-insertion between the full-bridge daughterboard and the half-bridge daughterboard.

[0027] All full-bridge daughter boards are full-bridge IGBTs soldered on the full-bridge daughter board PCB, and the connectors on the daughter boards are designed to be the same type of pins. All half-bridge daughter boards are half-bridge IGBTs fastened on the half-bridge daughter board PCB by bolts, and the connectors on the daughter boards are designed to be the same type of holes. The connectors between the motherboard and the daughterboard are unified to ensure the universality of the test device.

[0028] The software components of the FPGA control module on the motherboard of the present invention mainly include a serial port transceiver module, a receiving FIFO, a data analysis module, an AD acquisition module, a test execution module, a framing module, and a sending FIFO. The control process is as follows:

[0029] (1) The host sends the test command frame in the form of serial data to the serial port transceiver module through RS422, completes clock synchronization and serial-to-parallel conversion and sends it to the receiving FIFO. The receiving FIFO sends the clock-converted data to the data analysis module.

[0030] (2) Data analysis: The full-bridge or half-bridge IGBT model, output PWM frequency and other test information are analyzed from the control instructions. When the experiment type is a full-bridge continuous working experiment, it is also necessary to enable the AD module for temperature monitoring so that the IGBT can be turned off to protect it from overheating when the operating temperature reaches a certain value.

[0031] (3) The test execution module receives the test information from the data analysis module and executes the test content.

[0032] (4) The framing module receives the level information monitored by the test execution module and determines whether the working status of the IGBT is normal. If a fault occurs, it is also necessary to determine its fault status based on the level information and light up the corresponding fault indicator light. The information related to its working status is framed and sent to the serial port transceiver module through the sending FIFO, and then sent to the host through the RS422 serial port.

[0033] Preferably, the control flow of executing the test content in step (3) is as follows:

[0034] (1) Based on the test information parsed by the data parsing module, the monitoring module identifies the level status of the pins on the circuit to confirm whether the "resistor & TVS chain & module identification board" currently installed on the motherboard matches the IGBT type and model in the test instruction. If they match, execute (2); if not, exit the test and wait for the next test instruction to be sent;

[0035] (2) According to the voltage adjustment ratio in the test instruction, the corresponding relay is attracted;

[0036] (3) Wait for 1 second to allow the state of the voltage conditioning related relays to remain stable;

[0037] (4) Using the DDS function of the FPGA, output a variable pulse width PWM wave of a specified frequency on the product and bridge arm required by the test instruction;

[0038] (5) Monitor the low-level time on the bridge arm of the corresponding test type. Start counting when a falling edge is generated and stop counting when a rising edge appears. Calculate the low-level time by combining the module clock frequency and the low-level continuous count to monitor the working status of the IGBT.

[0039] Preferably, the control process of outputting a variable pulse width PWM wave of a specified frequency in step (4) is as follows:

[0040] (1) The sine wave signal is translated in the positive direction of the y-axis to a position symmetrical to the amplitude center of the carrier signal triangle wave to ensure that the sine wave and the triangle wave generate two amplitude intersection points in both the first and second half cycles of the sine wave.

[0041] (2) Compare the amplitudes of the shifted sine wave and triangle wave. When the sine wave amplitude is smaller than the triangle wave amplitude, PWM_P outputs a high level and PWM_N outputs a low level; when the sine wave and triangle wave reach the amplitude intersection point, the outputs of PWM_P and PWM_N are both 0; as the loaded address increases, the sine wave amplitude is greater than the triangle wave amplitude, PWM_P outputs a low level and PWM_N outputs a high level; when the sine wave and triangle wave reach the amplitude intersection point again, the outputs of PWM_P and PWM_N are both 0. Repeat the above process until a sine wave cycle ends, and two variable pulse width PWM signals with opposite polarities and a duty cycle of 50% are obtained within a sine wave cycle.

[0042] (3) When PWM_P and PWM_N switch between high and low levels, an interval time is added. The interval time is usually selected to be tens of ns to prevent the upper and lower bridge arms from being turned on at the same time and causing a power short circuit.

[0043] (4) When a PWM signal of a specified frequency needs to be generated, a sine wave signal of that frequency is used to compare its amplitude with the high-frequency triangle wave carrier signal. By using the DDS function of the FPGA, two waveforms of different frequencies can be obtained by changing the update frequency of the sine wave signal and the triangle wave loading address.

[0044] Using a high-frequency triangle wave as a carrier signal, two variable-width PWM signals with specified frequencies and opposite polarities are generated by comparing the amplitude with a sine wave of a specified frequency. At the same time, a time interval of tens of nanoseconds is set when the two PWM signals are flipped to prevent the upper and lower bridge arms of the IGBT from being turned on at the same time during operation, causing a power short circuit.

[0045] Preferably, the step (4) of obtaining two waveforms of different frequencies by changing the updating frequency of the sine wave signal and the triangle wave loading address is specifically implemented as follows for the half-bridge continuous working experiment:

[0046] (1) Calculate the frequency division coefficient N = triangle wave frequency / sine wave frequency;

[0047] (2) When the triangle wave loading address increases by N addresses, the sine wave loading address increases by 1.

[0048] Preferably, the step (4) of obtaining two waveforms of different frequencies by changing the updating frequency of the sine wave signal and the triangle wave loading address is implemented as follows for the full-bridge continuous working experiment:

[0049] (1) Load a high-frequency triangle wave;

[0050] (2) Calculate the frequency division coefficient and start loading the U-phase sine wave signal;

[0051] (3) When the U-phase sine wave loading address reaches one-third of the address cycle, the V-phase sine wave signal begins to be loaded, and the V-phase frequency division coefficient is the same as the U-phase frequency division coefficient;

[0052] (4) When the U-phase sine wave loading address reaches two-thirds of the address cycle, the W-phase sine wave signal begins to be loaded, and the W-phase frequency division coefficient is the same as the U-phase frequency division coefficient.

[0053] Compared with the prior art, the present invention has the following beneficial effects:

[0054] (1) The present invention supports full-bridge and half-bridge continuous operation tests of IGBTs of different models. The resistor, TVS chain circuit, and module identification circuit are determined according to the parameters of the full-bridge or half-bridge IGBT to be tested, thereby being compatible with tests of full-bridge and half-bridge IGBTs of different models, and realizing the versatility of the test device;

[0055] (2) The conditioning ratio in the voltage conditioning circuit of the present invention can be set programmably, thereby supporting the testing of full-bridge and half-bridge IGBTs with different bus voltage levels;

[0056] (3) The module identification circuit of the present invention can be designed as a 6-bit, 8-bit, 10-bit, or even more-bit high and low level generating circuit as required, thereby supporting the testing of more different types of IGBTs;

[0057] (4) The present invention supports variable pulse width PWM waves of different frequencies and can be set online according to the communication protocol;

[0058] (5) The present invention has an anti-misinsertion function between the full-bridge and half-bridge daughter boards and the motherboard. The full-bridge daughter board is connected to the hole-type daughter board interface on the motherboard through a pin-type connector, and the half-bridge daughter board is connected to the pin-type daughter board interface on the motherboard through a hole-type connector, thereby avoiding misinsertion between the full-bridge and half-bridge daughter boards and the motherboard. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1 is a system block diagram of the present invention;

[0060] Figure 2 The motherboard composition and interconnection principle of the present invention;

[0061] Figure 3 It is the voltage conditioning circuit diagram related to the full-bridge IGBT;

[0062] Figure 4 It is the voltage conditioning circuit diagram related to the half-bridge IGBT;

[0063] Figure 5 Identify the circuit diagram for the module;

[0064] Figure 6 It is the software module diagram;

[0065] Figure 7 This is the continuous working principle diagram of the full-bridge IGBT;

[0066] Figure 8 This is the continuous working principle diagram of the half-bridge IGBT;

[0067] Fig. 9 To execute the test module flow chart;

[0068] Fig.10 Generate a flow chart for variable pulse width PWM signal. DETAILED DESCRIPTION

[0069] To make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0070] like Figure 1 As shown, the IGBT universal continuous working test device proposed by the present invention includes a host, a motherboard, a daughterboard, a load inductor, an integrated control cable, a DC power cable, a short power cable, a load cable, and a universal DC power supply, an oscilloscope, a current probe, a 220VAC power cord and a power line.

[0071] The 220VAC power cord supplies power to the host and oscilloscope respectively, and the power cord is powered by a DC power supply. The host is connected to the motherboard through an integrated control cable to realize power supply to the motherboard and communication with the motherboard. The motherboard is connected to the oscilloscope through an SMA cable to realize the transmission of conditioned voltage signals. The daughterboard is connected to the motherboard through a connector to realize the transmission of low-voltage control signals and high-voltage electricity, and is connected to the load inductor through a load cable to realize the transmission of high-voltage AC power after inversion. The DC power supply is connected to the daughterboard through a DC power cable and a short power cable to realize the transmission of high-voltage DC power. The current probe connects the load cable and the oscilloscope to realize the monitoring of the load current. When conducting a full-bridge IGBT continuous operation test, only one full-bridge daughterboard is connected to the motherboard; when conducting a half-bridge IGBT continuous operation test, two identical half-bridge daughterboards are connected to the motherboard at the same time.

[0072] The host mainly includes a human-machine interface, an industrial computer, and a programmable power supply. The human-machine interface consists of a keyboard, a monitor, and a mouse; the industrial computer is used to load the application software of the test device. It uses a common single-board computer or an embedded industrial computer on the market. It is small in size and light in weight, laying the foundation for the miniaturization of the host. It has the same communication interface as the programmable power supply and the motherboard communication circuit; the programmable power supply provides the motherboard with the 24VDC power supply required for work. The start and stop of the programmable power supply, as well as the output voltage and current, are all realized under the control of the industrial computer.

[0073] The motherboard mainly includes DC / DC power supply circuit, reset circuit, communication circuit, FPGA part, status indication circuit, temperature monitoring circuit, voltage conditioning circuit, 3 groups of level conversion & dual-channel isolation drive circuit, resistor & TVS chain & module identification circuit, daughter board interface, such as Figure 2 shown.

[0074] The DC / DC power supply circuit has an isolated 24VDC to 5VDC circuit, which provides working power for each part of the motherboard, as well as other power supply circuits required for 5VDC conversion to FPGA. The communication circuit realizes data interaction between the motherboard FPGA and the host. The FPGA part is the control core of the motherboard. Under the control of the FPGA, the status indication circuit is used to display whether each bridge arm of the full-bridge or half-bridge IGBT has a fault during the test, as well as the fault status. When a bridge arm is in normal, short-circuit fault, or undervoltage fault, the corresponding indicator light is off, always on, and flashing. The temperature monitoring circuit consists of a current source, an operational amplifier, a voltage reference, and an AD acquisition. It is used to monitor the temperature of the full-bridge IGBT with an NTC resistor under the control of the FPGA to ensure that the full-bridge IGBT with an NTC resistor is protected and shut down when the temperature is too high. The reset circuit is implemented by a push button switch, one end of the switch is grounded, and the other end is connected to the pull-up resistor and a general IO pin of the FPGA at the same time. The reset circuit is used to reset the FPGA and the status indicator circuit by manually pressing the switch when the FPGA detects a full-bridge or half-bridge IGBT test fault and controls the status indicator to work. For this key reset circuit, the FPGA program is designed with a debounce function. When the FPGA detects that the reset pin is at a low level and the duration reaches 0.5s, the program is reset and the status indicator is turned off.

[0075] The voltage conditioning circuit in the motherboard includes: a full-bridge IGBT voltage conditioning circuit, a half-bridge IGBT voltage conditioning circuit, and a standard SMA interface.

[0076] like Figure 3 As shown, the full-bridge IGBT voltage conditioning circuit has one set of conditioning circuits for the U phase, V phase, and W phase to the high-voltage DC power supply ground. Each set of conditioning circuits can be programmed to set the conditioning ratio, and the conditioning ratio is preferably 1 / 40 or 1 / 60 to adapt to the output voltage collection of full-bridge IGBTs of different models and rated voltages during continuous operation.

[0077] Taking the U phase as an example, the method of setting the regulation ratio by program control is explained. The relay K2A is closed through the FPGA software, and the regulation ratio is 1 / 40, and the regulation ratio is 1 / 60 when it is opened. In this way, the voltage of several hundred V is reduced to 1 / 40 or 1 / 60, and sent to the oscilloscope for observation. For the V phase and the W phase, the FPGA software is used to control the closing and opening of the corresponding relays K2B and K2C to complete the setting of the regulation ratio.

[0078] Half-bridge IGBT voltage conditioning circuit Figure 4 As shown, it includes a voltage conditioning circuit between the output point of the first half-bridge IGBT and the output point of the second half-bridge IGBT. The conditioning circuit can set the conditioning ratio by program control, and the conditioning ratio is preferably 1 / 60 or 1 / 80 to adapt to the output voltage acquisition of half-bridge IGBTs of different models and rated voltages during continuous operation. When the relay K3A is closed, the conditioning ratio is 1 / 60, and when it is disconnected, the conditioning ratio is 1 / 80. In this way, the voltage of several hundred V is reduced to 1 / 60 or 1 / 80 and sent to the oscilloscope for observation.

[0079] The standard SMA interface enables the high voltage on the motherboard to be conditioned and then output to the oscilloscope through the SMA cable.

[0080] The level conversion & dual-channel isolation driving circuit in the motherboard includes: 1#, 2#, 3# level conversion & dual-channel isolation driving circuits.

[0081] Circuit 1# is used to realize the switch control of the first upper and lower bridge arms of the full-bridge IGBT, or the switch control of the upper and lower bridge arms of the first half-bridge IGBT; circuit 2# is used to realize the switch control of the second upper and lower bridge arms of the full-bridge IGBT; circuit 3# is used to realize the switch control of the third upper and lower bridge arms of the full-bridge IGBT, or the switch control of the upper and lower bridge arms of the second half-bridge IGBT. In this way, the universality of the drive control of the full-bridge IGBT and the half-bridge IGBT is realized.

[0082] The resistor & TVS chain & module identification circuit in the motherboard includes: an on-resistance circuit, an off-resistance circuit, a protection resistor circuit, a TVS chain circuit, and a module identification circuit.

[0083] In order to take into account the continuous working test of full-bridge, half-bridge and different types of IGBTs, the resistor & TVS chain & module identification circuit functions are integrated on an independent small board. The board matches the jack on the motherboard through the pins to achieve flexible replacement of the board. A set of universal test equipment corresponds to multiple resistor & TVS chain & module identification circuit boards. The turn-on resistor, turn-off resistor, protection resistor, TVS chain, and module identification circuit on each board are determined according to the parameters of the full-bridge or half-bridge IGBT to be tested. This makes it compatible with the tests of full-bridge and half-bridge IGBTs of different models, achieving the versatility of the test equipment. Figure 5As shown in the figure, the module identification circuit is designed to support 6-bit high and low level generation circuit, read the high and low levels of the 6 input pins F_A1 / A2 / B1 / B2 / C1 / C2, form 6-bit high and low levels or 000000~111111, a total of 64 states, representing 64 different types of devices. The FPGA can thus recognize that the board has 64 states, that is, it supports 64 different types of full-bridge and half-bridge IGBT tests. The module identification circuit can also be designed as an 8-bit, 10-bit, or even more high and low level generation circuit as needed.

[0084] The daughterboard interfaces in the motherboard include 1# full-bridge daughterboard interface, 2# and 3# half-bridge daughterboard interfaces.

[0085] The daughterboard interface is a pin-type or hole-type connector: there is one connector related to the full-bridge daughterboard, which is designed as a hole type; there are two connectors related to the half-bridge daughterboard, which are designed as pin-type. The two pin-type connectors related to the half-bridge daughterboard are exactly the same, which facilitates the random insertion of two half-bridge daughterboards of the same model. The connectors related to the full-bridge and half-bridge daughterboards are designed with different hole and pin types respectively to avoid mis-insertion between the full-bridge daughterboard and the half-bridge daughterboard.

[0086] All full-bridge daughter boards are full-bridge IGBTs that are soldered on the full-bridge daughter board PCB, and the connectors on the daughter boards are designed to be the same type of pins; all half-bridge daughter boards are half-bridge IGBTs that are fastened to the half-bridge daughter board PCB by bolts, and the connectors on the daughter boards are designed to be the same type of holes; the connectors between the motherboard and the daughter board are of a unified type to ensure the universality of the test device.

[0087] The software components of the FPGA control module on the motherboard of the present invention are as follows: Figure 6 As shown, it mainly includes serial port transceiver module, receiving FIFO, data analysis module, AD acquisition module, test execution module, framing module, and sending FIFO. The control flow is as follows:

[0088] (1) The host sends the test command frame in the form of serial data to the serial port transceiver module through RS422, completes clock synchronization and serial-to-parallel conversion and sends it to the receiving FIFO. The receiving FIFO sends the clock-converted data to the data analysis module.

[0089] (2) Data analysis: The control instructions are used to parse out test information such as the full-bridge or half-bridge IGBT model, the start or end of the test, and the frequency of the output PWM. When the experiment type is a full-bridge continuous working experiment, the AD module needs to be enabled to collect the resistance value of the NTC resistor to obtain the operating temperature of the IGBT so that the IGBT can be turned off to protect it from overheating when the operating temperature reaches a certain value.

[0090] (3) The test execution module receives the test information from the data analysis module and executes the test content, that is, it loads the PWM waveform of the specified frequency to the corresponding bridge arms G-TOP and G-BOT of the product under test through the path of level conversion & dual-channel isolation drive module → resistance & TVS chain & module identification part of the opening and closing resistance part → daughter board interface → daughter board. The working principle diagram of the full-bridge IGBT is shown in the figure. Figure 7 As shown, the working principle diagram of the half-bridge IGBT is as follows Figure 8 As shown, G-TOP represents the upper bridge arm driving signal of a certain phase, and G-BOT represents the lower bridge arm driving signal of a certain phase. At the same time, the level states of the signals FLT-TOP and FLT-BOT representing the working states of the upper and lower bridge arms on the isolation driver module are monitored through the path of daughter board → daughter board interface → protection resistor and TVS chain in the module identification part → level conversion & dual-channel isolation driver module, where FLT-TOP represents the working state of the upper bridge arm of a certain phase, and FLT-BOT represents the working state of the lower bridge arm of a certain phase.

[0091] (4) The framing module receives the level information monitored by the test execution module and determines whether the working status of the IGBT is normal. If a fault occurs, it is also necessary to determine its fault status based on the level information and light up the corresponding fault indicator light. The information related to its working status is framed and sent to the serial port transceiver module through the sending FIFO, and then sent to the host through the RS422 serial port.

[0092] The test execution module determines whether the "resistor & TVS chain & module identification board" currently installed on the motherboard matches the IGBT type and model in the test instruction, completes the voltage conditioning ratio and loading of the variable pulse width PWM wave according to the test instruction, and monitors the working status of the IGBT.

[0093] Among them, Fig. 9 As shown, the control flow in step (3) is as follows:

[0094] S1: Based on the test information parsed by the data parsing module, the monitoring module identifies the level status of the F_A1, F_A2, F_B1, F_B2, F_C1, and F_C2 pins on the circuit to confirm whether the "resistor & TVS chain & module identification board" currently installed on the motherboard matches the IGBT type and model in the test instruction. If they match, S2 is executed. If not, the test is exited and waits for the next test instruction to be sent.

[0095] S2: According to the voltage adjustment ratio in the test instruction, the corresponding relay is attracted; Figure 3 When the relays K2A, K2B, and K2C shown are turned on or off, the voltages of the U-phase, V-phase, and W-phase outputs of the full-bridge IGBT are adjusted to 1 / 40 and 1 / 60, respectively; or the control Figure 4The relay K3A shown is turned on and off, which means that the voltage output by the half-bridge IGBT is adjusted to 1 / 60 and 1 / 80 respectively.

[0096] S3: Wait for 1S to allow the status of the relays related to voltage conditioning to remain stable.

[0097] S4: Using the DDS function of FPGA, output the variable pulse width PWM wave of the specified frequency on the product and bridge arm required by the test instruction. Figure 2 → Figure 1 → Figure 7 As shown, or as Figure 2 → Figure 1 → Figure 8 As shown, the PWM wave is loaded to the corresponding bridge arm G-TOP and G-BOT of the full bridge or half bridge through the path of FPGA→level conversion & dual-channel isolation drive module→resistance & TVS chain & module identification part of the opening and closing resistance part→daughter board interface→daughter board, and controls the full bridge or half bridge IGBT to work at the specified frequency. Among them, G-TOP represents the upper bridge arm drive signal of a certain phase, and G-BOT represents the lower bridge arm drive signal of a certain phase.

[0098] S5: Monitor the low level time on the bridge arm of the corresponding test type, start counting when a falling edge is generated, stop counting when a rising edge appears, and calculate the low level time by combining the module clock frequency and the low level continuous count. Figure 1 → Figure 2 As shown, the FPGA monitors the level states of the signals FLT-TOP and FLT-BOT representing the working states of the upper and lower bridge arms on the isolation driver module through the path of daughter board → daughter board interface → protection resistor and TVS chain in the resistor & TVS chain & module identification part → level conversion & dual-path isolation driver module. Among them, FLT-TOP represents the working state of the upper bridge arm of a certain phase, and FLT-BOT represents the working state of the lower bridge arm of a certain phase. There are three working states: normal, undervoltage, and short circuit; when the IGBT works normally, FLT is high level; when the upper bridge arm of the IGBT has short circuit and undervoltage faults, FLT-TOP appears low level for 20ms and 80ms respectively; when the lower bridge arm of the IGBT has short circuit and undervoltage faults, FLT-BOT appears low level for 40ms and 80ms respectively; thus, the FPGA monitors the working state of the IGBT through the level state of the FLT signal.

[0099] The specific process of using DDS to output a variable pulse width PWM wave of a specified frequency in S4 is as follows:

[0100] The basic principle of waveform modulation using DDS is to sample the waveform and then save it in ROM. By changing the timing and phase, waveforms of different frequencies can be generated. The common method of using DDS to generate PWM signals is to set an amplitude threshold value for the sinusoidal signal. When the sinusoidal signal is higher than the threshold value, 0 is output, and when it is lower than the threshold value, 1 is output. Although this method is simple and easy to implement, it is difficult to ensure that the duty cycle of each cycle of the sine wave is 50% because the threshold value is a fixed value. In the present invention, a high-frequency triangular wave is used instead of a fixed threshold value, that is, a high-frequency triangular wave is used as a carrier signal, and two variable pulse width PWM signals of specified frequencies with opposite polarities are generated by comparing the amplitude with the sine wave of the specified frequency.

[0101] To simplify the explanation, assume that the PWM wave frequency to be generated is half of the carrier signal frequency. Fig.10 To illustrate the specific method of generating a PWM wave signal of a specified frequency.

[0102] like Fig.10 As shown in (a), when the minimum sampling values ​​of the sine wave and the triangle wave are both 0, the amplitudes of the sine wave and the triangle wave will inevitably be equal at the ordinate 0, resulting in the inability to switch the PWM level. Therefore, the sine wave signal needs to be translated to the positive direction of the y-axis to a position symmetrical to the center of the carrier signal triangle wave amplitude to ensure that the sine wave and the triangle wave have two amplitude intersections in the first and second half cycles of the sine wave, as shown in Figure 1. Fig.10 (b) as shown.

[0103] Compare the amplitudes of the shifted sine wave and triangle wave. When the sine wave amplitude is smaller than the triangle wave amplitude, PWM_P outputs a high level and PWM_N outputs a low level. When the sine wave and triangle wave reach the amplitude intersection point, the outputs of PWM_P and PWM_N are both 0. As the loaded address increases, the sine wave amplitude is greater than the triangle wave amplitude, PWM_P outputs a low level, and PWM_N outputs a high level. When the sine wave and triangle wave reach the amplitude intersection point again, the outputs of PWM_P and PWM_N are both 0. Repeat the above process until a sine wave cycle ends, and two PWM signals with opposite polarities and a duty cycle of 50% are obtained within a sine wave cycle, such as Fig.10 (c) as shown.

[0104] Considering the characteristics of IGBT, there is a dead time for the turning off and on of the upper and lower bridge arms. To prevent the upper and lower bridge arms from being turned on at the same time during IGBT operation, which may cause a short circuit in the power supply, PWM_N changes from low level to high level after a certain time T1 (T1 is usually tens of ns) after PWM_P changes from high level to low level. Similarly, after PWM_N changes from high level to low level, PWM_P changes from low level to high level after a time T1. That is, ensure that one bridge arm is turned off first, and then the other bridge arm is turned on. Fig.10 (d) as shown.

[0105] Depend on Fig.10 It can be seen that the frequency of PWM generation is the frequency of the sine wave signal. Therefore, when a PWM signal of a specific frequency needs to be generated, the sine wave signal of this frequency is used to compare the amplitude with the high-frequency triangle wave carrier signal. Since the amplitude of the waveform sampling is stored in the ROM, the input of the ROM is the loading address and the output is the amplitude. The ROM itself does not involve the frequency signal, so it is necessary to change the update frequency of the sine wave signal and the triangle wave loading address to obtain two waveforms of different frequencies. The specific implementation process is:

[0106] (1) Calculate the frequency division coefficient N = triangle wave frequency / sine wave frequency;

[0107] (2) When the triangle wave loading address increases by N addresses, the sine wave loading address increases by 1.

[0108] The half-bridge IGBT continuous operation test process is as follows: Fig.10 The PWM_P and PWM_N waveforms shown in (d) are converted from 0V and 3.3V to 0V and 5V respectively after passing through the level conversion circuit, and then converted from 0V and 5V to -8V and 15V respectively after passing through the dual-channel isolation drive circuit, and then passed through the resistor & TVS chain & module identification board on the opening and closing resistor circuit, the daughter board interface, and the daughter board, and then loaded to the upper and lower bridge arms of the half-bridge IGBT respectively. The -8V reverse shutdown voltage ensures that a bridge arm of the IGBT is reliably turned off and is not mistakenly turned on due to interference.

[0109] Combination Figure 8 The continuous working principle of the half-bridge IGBT shown in the figure, PWM_P is loaded on G-TOP1 and G-BOT3 at the same time, PWM_N is loaded on G-BOT1 and G-TOP3 at the same time, ensuring that the upper arm of half-bridge 1 and the lower arm of half-bridge 2 act at the same time, and the lower arm of half-bridge 1 and the upper arm of half-bridge 2 act at the same time.

[0110] In the full-bridge continuous working time test, three PWM waves with opposite polarities need to be loaded in the three-phase bridge arms respectively, and the PWM wave phases of the three-phase bridge arms of phase U, phase V, and phase W are delayed by one-third of a cycle in turn. The phases of the sine wave signals of the three PWM waves need to be delayed by one-third of a cycle in turn, so as to obtain PWM waves with phases delayed by one-third of a cycle in turn. The specific implementation process is:

[0111] (1) Load a high-frequency triangle wave;

[0112] (2) Calculate the frequency division coefficient and start loading the U-phase sine wave signal;

[0113] (3) When the U-phase sine wave loading address reaches one-third of the address cycle, the V-phase sine wave signal begins to be loaded, and the V-phase frequency division coefficient is the same as the U-phase frequency division coefficient;

[0114] (4) When the U-phase sine wave loading address reaches two-thirds of the address cycle, the W-phase sine wave signal begins to be loaded, and the W-phase frequency division coefficient is the same as the U-phase frequency division coefficient.

[0115] The full-bridge IGBT continuous working test process is as follows: Fig.10 (d) Based on the PWM_P and PWM_N signals shown in Figure 2, combined with the description of the half-bridge IGBT continuous operation test process and Figure 7 The full-bridge IGBT continuous working principle shown in the figure, PWM_P and PWM_N signals are loaded into the board after level conversion, isolation drive, turn-on resistor and turn-off resistor, daughter board interface, and daughter board. Figure 7 The upper and lower bridge arms G-TOP1 and G-BOT1 of the first or U phase are shown. PWM_P and PWM_N are delayed by one third of the sine wave cycle and loaded into Figure 7 The upper and lower bridge arms G-TOP2 and G-BOT2 of the second or V phase are shown. After delaying PWM_P and PWM_N by two-thirds of the sine wave cycle, they are loaded into Figure 7 As shown, the upper and lower bridge arms G-TOP3 and G-BOT3 of the third or W phase.

[0116] The contents not described in detail in the specification of the present invention belong to the common knowledge of those skilled in the art.

[0117] Although the present invention has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A general IGBT continuous operation test device, characterized in that: Including host, motherboard, daughterboard, load inductor, and universal DC power supply, oscilloscope, and current probe; The host is connected to the motherboard to realize power supply to the motherboard and communication with the motherboard; the motherboard is connected to the oscilloscope to realize the transmission of conditioned voltage signals; the daughter board is connected to the motherboard through a connector to realize the transmission of low-voltage control signals and high-voltage electricity, and the daughter board is connected to the load inductor to realize the transmission of high-voltage AC power after inversion; the DC power supply is connected to the daughter board to realize the transmission of high-voltage DC power; the oscilloscope monitors the current of the load inductor through a current probe.

2. The IGBT universal continuous operation test device according to claim 1, characterized in that: When conducting a full-bridge IGBT continuous operation test, only one full-bridge daughter board is connected to the motherboard; when conducting a half-bridge IGBT continuous operation test, two identical half-bridge daughter boards are connected to the motherboard at the same time.

3. The IGBT universal continuous operation test device according to claim 1, characterized in that: The host includes a human-machine interface, an industrial computer, and a programmable power supply; the human-machine interface is used for interaction; the industrial computer is used to load the application software of the test device, and has the same communication interface as the programmable power supply and the motherboard communication circuit; the programmable power supply provides the motherboard with the 24VDC power required for operation, and the start and stop of the programmable power supply, as well as the output voltage and current, are all realized under the control of the industrial computer.

4. The IGBT universal continuous operation test device according to claim 1, characterized in that: The motherboard includes DC / DC power supply circuit, reset circuit, communication circuit, FPGA, status indication circuit, temperature monitoring circuit, voltage conditioning circuit, 3 sets of level conversion & dual-channel isolation drive circuit, resistor & TVS chain & module identification circuit, and daughterboard interface; The DC / DC power supply circuit has an isolated 24VDC to 5VDC circuit, which provides working power for various parts of the motherboard, as well as 5VDC conversion to other power supply circuits required by the FPGA; The communication circuit realizes the data interaction between the motherboard FPGA and the host; the status indication circuit is used to display whether each bridge arm of the full-bridge or half-bridge IGBT has a fault during the test, and the fault status under the control of the FPGA; the temperature monitoring circuit is used to monitor the temperature of the full-bridge IGBT with NTC resistor under the control of the FPGA to ensure that the full-bridge IGBT with NTC resistor is protected and shut down when the temperature is too high; the reset circuit is used to reset the FPGA and the status indication circuit when the FPGA detects a full-bridge or half-bridge IGBT test fault and controls the status indicator to work; The voltage conditioning circuit includes: full-bridge IGBT voltage conditioning circuit, half-bridge IGBT voltage conditioning circuit, and standard SMA interface; the full-bridge IGBT voltage conditioning circuit has one set of conditioning circuits for U phase, V phase, and W phase relative to the high-voltage DC power supply ground, and each set of conditioning circuits can be programmed to set the conditioning ratio; the half-bridge IGBT voltage conditioning circuit includes one set of voltage conditioning circuits between the output point of the first half-bridge IGBT and the output point of the second half-bridge IGBT, and the conditioning circuit can be programmed to set the conditioning ratio; the standard SMA interface enables the high voltage on the motherboard to be output to the oscilloscope after conditioning; The level conversion & dual-channel isolation drive circuit includes: 1#, 2#, and 3# level conversion & dual-channel isolation drive circuits; the 1# circuit is used to realize the switch control of the first upper and lower bridge arms of the full-bridge IGBT, or the switch control of the upper and lower bridge arms of the first half-bridge IGBT; the 2# circuit is used to realize the switch control of the second upper and lower bridge arms of the full-bridge IGBT; the 3# circuit is used to realize the switch control of the third upper and lower bridge arms of the full-bridge IGBT, or the switch control of the upper and lower bridge arms of the second half-bridge IGBT; The resistor & TVS chain & module identification circuit are integrated on a separate small board, which matches the jack on the motherboard through the pins to achieve flexible replacement of the board; The daughter board interface includes 1# full-bridge daughter board interface, 2# and 3# half-bridge daughter board interfaces.

5. The IGBT universal continuous operation test device according to claim 4, characterized in that: A set of universal test equipment corresponds to multiple resistor & TVS chain & module identification circuit boards. The on-resistance, off-resistance, protection resistor, TVS chain and module identification circuit on each board are determined according to the parameters of the full-bridge or half-bridge IGBT to be tested. This makes it compatible with tests of full-bridge and half-bridge IGBTs of different models, thus realizing the universality of the test equipment.

6. The IGBT universal continuous operation test device according to claim 4, characterized in that: In the daughterboard interface, there is one connector related to the full-bridge daughterboard, which is designed as a hole type; there are two connectors related to the half-bridge daughterboard, which are designed as pin type; the two pin-type connectors related to the half-bridge daughterboard are exactly the same in model, which facilitates the random insertion of two half-bridge daughterboards of the same model.

7. The IGBT universal continuous operation test device according to claim 4, characterized in that: The serial port transceiver module, receiving FIFO, data analysis module, AD acquisition module, test execution module, framing module, and sending FIFO are configured on the FPGA; the control process of the FPGA includes: (1) The host sends the test command frame in the form of serial data to the serial port transceiver module through RS422, completes clock synchronization and serial-to-parallel conversion and sends it to the receiving FIFO, and the receiving FIFO sends the clock-converted data to the data analysis module; (2) The data analysis module analyzes the test information from the control instructions. When the experiment type is a full-bridge continuous working experiment, the AD module needs to be enabled to collect the NTC resistor value to obtain the operating temperature of the IGBT so that the IGBT can be turned off to protect it from overheating when the operating temperature reaches a certain value. (3) The test module receives the test information from the data analysis module and executes the test content; (4) The framing module receives the level information monitored by the test execution module and determines whether the working status of the IGBT is normal. If a fault occurs, it is also necessary to determine its fault status based on the level information and light up the corresponding fault indicator light. The information related to its working status is framed and sent to the serial port transceiver module through the sending FIFO, and then sent to the host through the RS422 serial port.

8. The IGBT universal continuous operation test device according to claim 7, characterized in that: Step (3) specifically includes the following process: S1: Based on the test information parsed by the data parsing module, the monitoring module identifies the level status of each pin on the circuit to confirm whether the "resistor & TVS chain & module identification board" currently installed on the motherboard matches the IGBT type and model in the test instruction. If they match, S2 is executed. If not, the test is exited and the next test instruction is sent. S2: Adjust the voltage regulation ratio according to the test instructions; S3: Wait for a predetermined time to allow the state of the relays related to voltage conditioning to remain stable; S4: Using the DDS function of FPGA, output the variable pulse width PWM wave of the specified frequency on the product and bridge arm required by the test instruction; S5: Monitor the low level time on the bridge arm of the corresponding test type, start counting when a falling edge is generated, and stop counting when a rising edge appears. The low level time is calculated by combining the module clock frequency and the low level continuous count.

9. The IGBT universal continuous operation test device according to claim 8, characterized in that: The specific process of using DDS to output a variable pulse width PWM wave of a specified frequency in S4 is as follows: The basic principle of waveform modulation using DDS is used to sample the waveform and then save it in ROM. Waveforms of different frequencies can be generated by changing the timing and phase. A high-frequency triangular wave is used instead of a fixed threshold value, that is, a high-frequency triangular wave is used as a carrier signal, and the amplitude is compared with a sine wave of a specified frequency to generate two variable pulse width PWM signals of a specified frequency with opposite polarity.

10. The IGBT universal continuous operation test device according to claim 9, characterized in that: By changing the update frequency of the sine wave signal and the triangle wave loading address, two waveforms with different frequencies are obtained. The specific implementation process is as follows: (1) Calculate the frequency division coefficient N = triangle wave frequency / sine wave frequency; (2) When the triangle wave loading address increases by N addresses, the sine wave loading address increases by 1.

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