Output buffer layout structure and output buffer circuit

Abstract

The present application provides a layout structure of an output buffer and an output buffer circuit, wherein the layout structure includes a first layout area and a second layout area, the first layout area is arranged at the edge of the layout and surrounds the second layout area; the second layout area includes a first sub-layout area for receiving an input signal from a corresponding input pad; the second sub-layout area is provided with a comparison unit; the third sub-layout area is provided with a logic circuit unit; the fourth sub-layout area is provided with an output unit, including a first end extending along a first direction and a second end extending along a second direction, the first end is adjacent to the third sub-layout area, and the second end is adjacent to the first layout area. By comparing the input signal level with the reference voltage, the problem that the logic circuit unit composed of an inverter cannot correctly identify the input high and low levels after irradiation, thereby causing the device to fail, and its input end can be suspended and compatible with the TTL level, and the layout is reasonable, easy to wire and has high reliability.

Description

Technical Field

[0001] The present application relates to the technical field of CMOS integrated circuits, and in particular to a layout structure of an output buffer, and an output buffer circuit including the output buffer. Background Art

[0002] CMOS (Complementary Metal Oxide Semiconductor) open-drain output buffer is an open-drain output buffer circuit manufactured using CMOS technology. It is mainly used as an interface circuit to buffer the input signal or shift the logic level (high to low or low to high). In addition, due to its large absorption current, CMOS open-drain output buffer can also be directly used for driving TTL logic circuits, relays or display devices.

[0003] Existing output buffers often use multiple inverters connected in series, and the commonly used CMOS inverter input structure, in order to be compatible with TTL (Transistor-Transistor Logic) levels (VIL is 0.8V, VIH is 2V), the channel width of its NMOS is usually larger than the channel width of the PMOS, so that the internal resistance of the NMOS tube is smaller than the internal resistance of the PMOS, thereby achieving the purpose of lowering the flip level. However, after a long period of irradiation, the turn-on voltage (threshold voltage) of the NMOS tube of the CMOS inverter using this structure will decrease, resulting in a decrease in the flip level.

[0004] Especially for CMOS integrated circuits including CMOS open-drain output buffers, in order to meet the voltage resistance requirements, thick gate oxide layers are usually used, and the thicker the gate oxide layer, the better the voltage resistance performance. However, under the action of space radiation, the gate oxide layer is ionized to produce a large number of electron-hole pairs. Even at room temperature, the electrons in SiO2 are mobile and can move quickly and leave the SiO2 layer toward the positively biased gate electrode. On the other hand, the holes in the SiO2 layer will generate oxidation charges Q OX , at this time, the positive oxide layer charge will cause the turn-on voltage to drift, and the drift of the turn-on voltage is proportional to the square of the SiO2 thickness. Therefore, when the MOS tube with a thick gate oxide layer is in an irradiated environment for a long time, the turn-on voltage (threshold voltage) drifts, wherein the NMOS threshold voltage decreases, and the PMOS threshold voltage (negative value) also decreases (i.e., the absolute value increases). The existing output buffer generally includes multiple cascaded CMOS inverters. If the threshold voltage of the MOS tube shifts, it may cause a significant decrease in the flip level of the CMOS inverter.

[0005] Especially in CMOS integrated circuits compatible with TTL logic levels, the flip level itself is relatively low (assuming the original flip point level is 1.4V). If it drifts negatively by more than 1V, the flip point level will be less than 0.4V, resulting in failure of the low-level input voltage test and even functional failure.

[0006] Therefore, providing a CMOS open-drain output buffer that is radiation-resistant, TTL-level compatible, and high-voltage resistant is a problem that needs to be solved. Summary of the invention

[0007] In order to solve the above problems existing in the prior art, the first aspect of the embodiment of the present application provides a layout structure of an output buffer, wherein the layout structure specifically includes a first layout area and at least one second layout area, wherein the first layout area is arranged at the edge of the chip and surrounds the at least one second layout area;

[0008] The first layout area is provided with input pads and output pads corresponding to at least one second layout area one by one, and is also provided with power pads and ground pads;

[0009] The second layout area includes:

[0010] A first sub-layout area, adjacent to the first layout area, for receiving an input signal from a corresponding input pad;

[0011] The second sub-layout area is provided with a comparison unit, which is adjacent to the first sub-layout area; the comparison unit is configured to compare the input signal with the reference voltage and provide a control signal based on the comparison result;

[0012] The third sub-layout area is provided with a logic circuit unit, which is adjacent to the second sub-layout area; the logic circuit unit is configured to receive and enhance the driving capability of the control signal and provide a processed control signal;

[0013] The fourth sub-layout area is provided with an output unit, including a first end extending along a first direction and a second end extending along a second direction, the first direction and the second direction being perpendicular; and the first end is adjacent to the third sub-layout area, and the second end is adjacent to the first sub-layout area; the output unit is configured to provide an output signal to a corresponding output pad based on a processed control signal.

[0014] In the above scheme, since the second sub-layout area including the comparison unit is newly added, by comparing the input signal with the reference voltage, it is possible to improve the problem of the circuit input terminal level flip point being too low due to the excessive drift of the MOS tube turn-on voltage threshold when the integrated circuit of the high-voltage CMOS process with a relatively thick gate oxide layer is exposed to radiation for a long time, resulting in parameter deviation or functional failure.

[0015] Optionally, the first ends of the third sub-layout area and the fourth sub-layout area are both arranged at an end of the second layout area away from the first layout area along the second direction.

[0016] Optionally, the first sub-layout area and the second sub-layout area are arranged along the first direction; the second ends of the first sub-layout area, the second sub-layout area, and the fourth sub-layout area are all arranged at an end of the second layout area close to the first layout area along the second direction.

[0017] Optionally, there are multiple second layout areas and they are arranged in an array, and two adjacent second layout areas along the second direction are symmetrically arranged.

[0018] In the aforementioned optional solution, the fourth sub-layout area includes a first end and a second end extending in different directions. In other words, the fourth sub-layout area is L-shaped as a whole, which can effectively utilize the chip area to a greater extent, increase the area of ​​the output unit, such as the area of ​​the MOS tube, thereby increasing the output driving capability. In addition, the fourth sub-layout area is L-shaped as a whole, which can facilitate the arrangement of its two ends adjacent to the second sub-layout area and the third sub-layout area, thereby facilitating the reduction of the routing distance and the smooth transmission of the signal.

[0019] In addition, the first sub-layout area is arranged at the outermost side of the second layout area, close to the first layout area, which is helpful for metal wiring and can reduce the routing distance during input wiring. Specifically, it is convenient for wiring with the input pad in the first layout area.

[0020] The second sub-layout area is adjacent to the first sub-layout area, which is convenient for receiving signals from the first sub-layout area. At the same time, the shape and position of the second sub-layout area can make one side of the input end of the comparison unit close to the first sub-layout area, and the output end can be set on the side of the second sub-layout area adjacent to the third sub-layout area, which is convenient for controlling the signal to enter the third sub-layout area.

[0021] Optionally, the spacing between the plurality of second layout areas is 15 μm to 20 μm. Optionally, the spacing between the first layout area and the adjacent sub-layout area of ​​the second layout area is 20 μm to 30 μm; the spacing between the first sub-layout area and the second sub-layout area is 6 μm to 10 μm; the spacing between the second sub-layout area and the third sub-layout area is 6 μm to 10 μm; the spacing between the third sub-layout area and the fourth sub-layout area is 6 μm to 10 μm.

[0022] The preset spacings in the aforementioned optional schemes can meet the requirements for the circuit electrical performance indicators, and also meet the requirements of the process processing for the layout design. On this basis, the layout of each layout and sub-layout is coordinated to facilitate metal wiring, and can also make the signal flow more smooth and effective, reducing the space waste caused by unnecessary metal wiring and the reliability risks caused by long-distance routing.

[0023] Optionally, a first resistor is provided in the first sub-layout area, one end of the first resistor is connected to the power pad, and the other end is connected to the corresponding input pad; the comparison unit includes a comparator, the non-inverting input end of the comparator is connected to the corresponding input pad, and the inverting input end is used to access the reference voltage; the logic circuit unit includes a plurality of cascaded inverters, and the input end of the logic circuit unit is connected to the output end of the comparison unit; the output unit includes a first NMOS tube, the gate of the first NMOS tube is connected to the output end of the logic circuit unit, the source and substrate are connected to the ground pad, the drain is connected to the corresponding output pad, and the drain is used to connect to the pull-up resistor.

[0024] When the input signal is connected, the power supply voltage is connected through the first resistor and the input pad to the signal input terminal (the non-inverting input terminal of the comparator) to form a path and generate input current. At this time, the voltage of the signal input terminal is the voltage of the input signal connected. In addition, the current size of the signal input terminal can be controlled by adjusting the resistance value of the aforementioned first resistor.

[0025] Optionally, the second sub-layout area is also provided with a second resistor and a third resistor; one end of the second resistor is connected to the power pad, and the other end is connected to the inverting input of the comparator; one end of the third resistor is connected to the inverting input, and the other end is connected to the ground pad.

[0026] The two resistors connected in series, namely the second resistor and the third resistor, can play a role in voltage division and provide the required reference voltage for the comparison unit. By adjusting the resistance values ​​of the two resistors respectively, different reference voltage values ​​can be generated to meet different usage requirements; for example, in order to be compatible with TTL level, the reference voltage can be adjusted to 1.4V.

[0027] Optionally, the second resistor and the third resistor both include a plurality of resistors connected in series; the plurality of resistors in the second resistor and the plurality of resistors in the third resistor have the same specifications, and the quantities are the same or different.

[0028] In the aforementioned optional scheme, when radiation occurs, since the resistor specifications are the same, the change in resistance of each resistor is also the same. In this way, the reference voltage is only related to the number of resistors that make up the second resistor and the third resistor, and the reference voltage can be basically unaffected by radiation and remain stable.

[0029] Optionally, the comparator includes a first PMOS tube and a second PMOS tube of the same specification, the gate of the first PMOS tube serves as a non-inverting input terminal, and the gate of the second PMOS tube serves as an inverting input terminal.

[0030] In this optional solution, since the first PMOS tube and the second PMOS tube have the same specifications, even if the threshold voltages of the two PMOS tubes drift negatively by more than 1V after irradiation, they are still less than the power supply voltage minus the reference level. The PMOS tubes can still work normally and the function of the comparator will not be affected.

[0031] Optionally, the comparator further comprises:

[0032] The third PMOS tube has a source and a substrate connected to a power pad, a gate connected to a ground pad via a resistor, and a drain connected to the sources of the first PMOS tube and the second PMOS tube; the second NMOS tube has a drain connected to the drain of the first PMOS tube, and a source and a substrate connected to a ground pad; the third NMOS tube has a drain connected to the drain of the second PMOS tube, and a source and a substrate connected to a ground pad; wherein the gates of the second NMOS tube and the third NMOS tube are both connected to the drain of the first PMOS tube; the substrates of the first PMOS tube and the second PMOS tube are both connected to the power pad, and the drain of the second PMOS tube serves as the output end of the comparator.

[0033] Optionally, the number of inverters in the logic circuit unit is an odd number. This is because the NMOS tube in the output unit itself is equivalent to an inverter, and this optional solution is intended to provide a non-inverting buffer, so the logic circuit unit contains an odd number of inverter chains.

[0034] Optionally, the power pad and the ground pad are symmetrically arranged at two ends of the first layout area along the first direction; and the input pad and the output pad corresponding to the same second layout area are arranged adjacent to each other.

[0035] Optionally, a second layout area includes six array arrangements.

[0036] Optionally, in the first layout area, three groups of input pads / output pads are set on both sides of the connection line between the power pad and the ground pad, that is, a total of six groups of input / output pads, corresponding to the six aforementioned second layout areas, respectively, to provide signal input / output for the six channels in the output buffer.

[0037] Optionally, in the first layout area, electrostatic protection structures are provided on both sides of each input pad or output pad.

[0038] In the second aspect of the embodiment of the present application, an output buffer circuit is also provided, and the circuit product includes an output buffer, and the output buffer adopts the layout structure provided in the aforementioned technical solution and any one of the optional and preferred solutions thereof, and an external resistor unit; the external resistor unit includes a fourth resistor, one end of the fourth resistor is used to connect to an external power supply, and the other end is connected to an output pad, and is used to provide a pull-up resistor for the output unit. By adjusting the resistance value of the fourth resistor and the voltage value of the external power supply, the output level can be pulled up to a high level such as 30V output.

[0039] In summary, compared with the prior art, the output buffer of the layout structure provided in the embodiment of the present application, and the output buffer circuit including the output buffer, are additionally provided with two sub-layout areas including a first resistor and a comparison unit, which can not only make the signal input terminal suspended, but also improve the problem of the circuit input terminal level flip point being too low due to the excessive drift of the MOS tube start-up voltage after long-term irradiation in the high-voltage CMOS process integrated circuit with a relatively thick gate oxide layer, resulting in parameter deviation or functional failure, thereby ensuring the correctness of signal transmission and the reliability of chip functions, as well as compatibility with TTL levels.

[0040] At the same time, the technical solution of the present application can realize the function of the improved circuit by rationally laying out each layout area, especially optimizing and adjusting the position and shape of each sub-layout area in the second layout area. On the other hand, the position and placement of each sub-layout area are adapted to the signal flow, while meeting the requirement of being close to the pad, thereby facilitating metal wiring and reducing the area, and improving the reliability of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments of the present application will be described below.

[0042] Figure 1 is a circuit schematic diagram of an output buffer provided in an embodiment of the present application;

[0043] Figure 2 An exemplary circuit structure of a comparator in an output buffer provided by an embodiment of the present application is shown;

[0044] Figure 3 It is a layout structure of an output buffer provided in an embodiment of the present application;

[0045] Figure 4 The diagram shows the layout of a layout area within one channel in the layout structure of an output buffer provided in an embodiment of the present application.

[0046] Note in the figure:

[0047] 1: first layout area, 2: second layout area;

[0048] 201: first sub-layout area, 202: second sub-layout area, 203: third sub-layout area, 204: fourth sub-layout area;

[0049] 2041: first end, 2042: second end. DETAILED DESCRIPTION

[0050] In this specification, it will also be understood that when a component / module / unit is referred to as being relative to other components / modules / units, such as being "connected to" other components / modules / units, the component / module / unit may be directly connected to or directly coupled to other components / modules / units, or there may also be a third component / module / unit in between; in addition, in the embodiments of the present application, "connected" mainly refers to electrical connection, and "adjacent" and "adjacent" refer to two layout areas being connected to each other, or two layout areas being directly close to each other (excluding a third chip layout structure in between) and separated by a preset distance.

[0051] The present application will now be described more fully below with reference to the accompanying drawings, however, the present application can be implemented in many different ways and should not be construed as being limited to the embodiments set forth herein. On the contrary, providing these embodiments herein will make the present application more detailed and complete, and fully convey the scope of the present application to those skilled in the art. The same reference numerals throughout the text represent the same objects.

[0052] In view of the two requirements for output buffers in practical applications, namely: (1) being compatible with TTL levels, and (2) being able to withstand high voltages, as well as the problems in the prior art that the signal input terminal cannot be left floating and is difficult to be compatible with TTL levels after long-term irradiation, the present application provides a CMOS open-drain output buffer that is radiation-resistant, compatible with TTL levels, and able to withstand high voltages. More specifically, a layout structure of a silicon-gate CMOS radiation-resistant open-drain output buffer chip is provided.

[0053] In order to make the embodiments of the present application more fully disclosed, before elaborating on the layout features of the chip in the embodiments of the present application, the circuit principle of the chip provided in the embodiments of the present application is first described as follows.

[0054] like Figure 1As shown, the output buffer chip provided by the present application integrates a comparison unit, a logic circuit unit and an output unit, wherein the comparison unit includes a comparator COMP, and the comparator COMP has a non-inverting input terminal, an inverting input terminal and an output terminal, wherein the non-inverting input terminal serves as a signal input terminal A, the inverting input terminal is used to access a reference voltage, the output terminal is connected to the input terminal of the logic circuit unit, and the output terminal of the logic circuit unit is connected to the input terminal of the output unit; the output terminal of the output unit serves as a signal output terminal Y. The signal is input from the signal input terminal A, passes through the comparison unit, the logic circuit unit and the output unit in sequence, forms an output signal and is output by the signal output terminal Y. In the layout of the actual chip, the signal input terminal A is connected to the corresponding input pad in the interface layout area, and the signal output terminal Y is connected to the corresponding output pad in the interface layout area to realize the transmission of signals inside and outside the chip.

[0055] In an embodiment, Figure 1 As shown, the chip further integrates a first resistor R1 , one end of the first resistor R1 is connected to the signal input terminal A, and the other end is used to access the power supply voltage VCC.

[0056] Compared with the prior art, the aforementioned circuit structure adds a comparison unit and a first resistor R1. When no input signal is connected, the signal input terminal A is connected to the power supply voltage VCC through the first resistor R1. At this time, the signal input terminal A is kept at a high level, and the voltage is kept at the power supply voltage VCC. Therefore, the signal input terminal A of the circuit can be suspended. When the input signal is connected, the power supply voltage VCC forms a path through the first resistor R1 to the signal input terminal A and outputs current to the signal input terminal A. The voltage of the signal input terminal A is the voltage of the connected input signal.

[0057] The current at the input signal input terminal A can be controlled by adjusting the resistance of the first resistor R1.

[0058] In an embodiment, the reference voltage may be provided by a preset, adjustable constant voltage source, or, in a typical implementation, as Figure 1 As shown, the comparison unit further includes a second resistor R2 and a third resistor R3 connected in series.

[0059] One end of the second resistor R2 is used to access the power supply voltage, and the other end is connected to the inverting input terminal of the comparator COMP. One end of the third resistor R3 is connected to the inverting input terminal of the comparator COMP, and the other end is grounded.

[0060] During operation, when the signal input terminal A is connected to the input signal, the input signal enters the non-inverting input terminal of the comparator COMP through the signal input terminal A via the first resistor R1, and the voltage divided by the second resistor R2 and the third resistor R3 is used as the reference voltage V REFConnect to the inverting input of the comparator COMP, where the reference voltage V REF The voltage value is:

[0061]

[0062] Where V CC is the power supply voltage value, R2 and R3 are the resistance values ​​of the second and third resistors respectively.

[0063] Considering that the reference voltage V REF After being irradiated for a long time, the second resistor R2 and the third resistor R3 can be set to be composed of a plurality of resistors connected in series. The specifications of these resistors are exactly the same, and the number of resistors in the second resistor R2 and the third resistor R3 can be the same or different, thereby adjusting the resistance value of the second resistor R2 and the third resistor R3, that is, the number of resistors contained, and further adjusting the reference voltage V REF Since the specifications of the resistors are exactly the same, when they are irradiated, the change in the resistance of each resistor is also the same. In this way, the reference voltage V REF It only depends on the number of resistors constituting the second resistor R2 and the third resistor R3, and can be basically unaffected by the radiation and remain basically stable.

[0064] For example, the second resistor R2 is composed of 6 resistors connected in series, and the third resistor R3 is composed of 2 resistors. The specifications of these 8 resistors are the same. In this way, when the power supply voltage VCC = 5.6V, the reference voltage V REF Able to maintain 1.4V and not easily affected by long-term radiation.

[0065] The comparator COMP in the comparison unit is configured to compare the input signal and the reference voltage V REF A comparison is performed, and a control signal is output based on the comparison result.

[0066] In a typical embodiment, the circuit structure of the comparator COMP is as follows: Figure 2 As shown, the input signal IN and the reference voltage V REF The gates of the two PMOS tubes P1 and P2 are connected respectively, and the specifications and parameters of the two PMOS tubes P1 and P2 are the same. The above setting makes it possible that even if the threshold voltage of the two PMOS tubes drifts negatively by more than 1V after long-term irradiation, it is still less than the power supply voltage minus the reference level, and the PMOS tubes can still work normally, and the function of the comparator COMP is not affected. Therefore, if the voltage of the input signal is higher than the reference voltage, the output of the comparator COMP is a high level, and if the voltage of the input signal is lower than the reference voltage, the output of the comparison unit COMP is a low level.

[0067] In a typical embodiment, the specific circuit structure of the comparator COMP is as follows: Figure 2 As shown, the direction from top to bottom in the figure includes:

[0068] The third PMOS transistor P3 has a source and a substrate for connecting to the power supply voltage VCC, a gate connected to the ground via a resistor, and a drain connected to the sources of the first PMOS transistor P1 and the second PMOS transistor P2 respectively.

[0069] The two PMOS tubes, the first PMOS tube P1 and the second PMOS tube P2, have substrates for connecting to the power supply voltage, and the drain of the second PMOS tube P2 is also used as the output terminal OUT of the comparison unit.

[0070] The drain of the second NMOS transistor N2 is connected to the drain of the first PMOS transistor P1, and the source and substrate are grounded; the drain of the third NMOS transistor N3 is connected to the drain of the second PMOS transistor P2, and the source and substrate are grounded. The gates of the second NMOS transistor N2 and the third NMOS transistor N3 are both connected to the drain of the first PMOS transistor P1.

[0071] In summary, the comparator COMP in the embodiment compares the voltage of the input signal with the reference voltage, thereby avoiding the problem that the CMOS inverter in the logic circuit unit of the next stage cannot correctly identify the high and low levels of the input after irradiation, thereby causing functional failure. In other words, by adding a comparison unit, it is avoided that the external input signal directly enters the CMOS inverter, flips the level shift after irradiation, and cannot correctly identify the high and low levels of the input.

[0072] Furthermore, by increasing or decreasing the number of resistors and adjusting the resistance values ​​of the second resistor R2 and the third resistor R3, different reference voltage values ​​can be generated to meet different usage requirements; for example, in order to be compatible with TTL level, the reference voltage can be adjusted to 1.4V.

[0073] like Figure 1 As shown, the output end of the comparison unit, that is, the output end of the comparator COMP, is connected to the logic circuit unit, and the control signal generated by the comparison unit is output to the logic circuit unit, and the logic circuit unit includes a plurality of cascaded inverters, or an inverter chain. For example, Figure 1 As shown, the logic circuit unit includes n inverters, INV1, INV2 to INVn, which are cascaded in sequence.

[0074] Multiple cascaded inverters perform phase conversion on the aforementioned control signal, because the comparison unit of the previous stage has compared the input signal voltage with the reference voltage, and the obtained control signal is a high level or a low level, so it is no longer necessary to adopt the method of the PMOS tube channel width being smaller than the NMOS tube channel width, that is, the first-stage inverter INV1 in the logic circuit unit can adopt the typical CMOS inverter input mode, that is, the ratio of the PMOS tube and the NMOS tube channel width is 2:1 (WP:WN=2:1). Subsequently, multiple cascaded inverters can process the driving capability of the control signal step by step, and then output the processed control signal to the output unit.

[0075] In an embodiment, the same-phase or anti-phase phase conversion can be achieved by adjusting the number of cascaded inverters, specifically, adjusting the odd and even number of inverters.

[0076] In a typical embodiment, the product needs to realize the function of a common-mode buffer. Since the first NMOS tube N1 included in the output unit itself is equivalent to an inverter, an odd number of cascade inverters, such as 3, 5, or 7 inverters, are set in the logic circuit unit to form an inverter chain.

[0077] like Figure 1 As shown, the output unit is used to receive the control signal processed by the cascade inverter in the logic circuit unit, further process the control signal, and then output it through the output terminal Y. Usually, the output terminal Y is also connected to a pull-up resistor.

[0078] In an embodiment, Figure 1 As shown, the output unit includes a first NMOS transistor N1, and the output buffer provided in the embodiment has a drain open function. The gate of the first NMOS transistor N1 is connected to the output end of the logic circuit unit, the source and the substrate are grounded, the drain serves as the signal output end Y, and the drain is also used to connect the pull-up resistor.

[0079] In an embodiment, Figure 1 As shown, a fourth resistor R4 as a pull-up resistor is also included, one end of the fourth resistor R4 is connected to the external power supply VDD, and the other end is connected to the signal output terminal Y. Preferably, the fourth resistor R4 is an external component, constituting an external resistor unit, and is not integrated into the same chip with the comparison unit, the logic circuit unit, and the output unit.

[0080] According to the above embodiment, if the signal output from the logic circuit unit is at a high level, the first NMOS transistor N1 is turned on and the signal output terminal Y is at a low level; conversely, if the signal output from the logic circuit unit is at a low level, the first NMOS transistor N1 is turned off, and under the joint action of the external power supply VDD and the fourth resistor R4, the signal output terminal Y is at a high level.

[0081] On the premise that the circuit principle of the output buffer provided in the embodiment of the present application has been explained, the embodiment of the present application provides an output buffer having the following layout structure. At the same time, for ease of understanding, in the following description, Figure 3 , Figure 4 The horizontal direction in is recorded as the first direction, and the vertical direction is recorded as the second direction. Figure 3 , Figure 4 The coordinate axes are shown in .

[0082] refer to Figure 3 The layout structure of the output buffer includes a first layout area 1 and a second layout area 2, wherein the first layout area 1 is an interface layout area, which is arranged at the edge of the chip; the second layout area 2 is arranged in the middle area of ​​the layout, and the second layout area 2 is surrounded by the first layout area 1.

[0083] The number of second layout areas 2 depends on the number of channels. Figure 3 In the embodiment shown in FIG. 1 , the number of the second layout areas 2 is six, and they are arranged in two rows, with three second layout areas 2 arranged in each row, and each second layout area 2 is shown by a dotted frame. Of course, the number of the second layout areas 2 is not limited thereto, and in other embodiments, the number of the second layout areas 2 may also be one or other numbers.

[0084] like Figure 3 As shown, the first layout area 1 is provided with input pads (A1, A2...A6) and output pads (Y1, Y2...Y6) corresponding to the second layout area 2 one by one, and the first layout area 1 is also provided with a power pad VCC and a ground pad GND. In other words, the power pad VCC and the ground pad GND in the first layout area 1 can be one each; the number of input pads and output pads is consistent with the number of the second layout area 2, and each second layout area 2 corresponds to one input pad and one output pad.

[0085] like Figure 3 The overall chip layout shown, as well as Figure 4 The view of the second layout area 2 is shown, each second layout area 2 further includes:

[0086] The first sub-layout area 201 is provided with a first resistor R1, which is adjacent to the first layout area 1 and is used to receive an input signal from a corresponding input pad, or to pull up the signal input end of the channel to a power supply voltage when no signal is connected.

[0087] The second sub-layout area 202 is provided with a comparison unit, which is adjacent to the first sub-layout area 201; the comparison unit is configured to compare the input signal with the reference voltage and provide a control signal based on the comparison result.

[0088] The third sub-layout area 203 is provided with a logic circuit unit, which is adjacent to the second sub-layout area 202; the logic circuit unit is configured to receive and enhance the driving capability of the control signal and provide a processed control signal.

[0089] The fourth sub-layout area 204 is provided with an output unit, which includes a first end 2041 extending along the first direction and a second end 2042 extending along the second direction, the first end 2041 is adjacent to the third sub-layout area 203, and the second end 2042 is adjacent to the first layout area 1; the output unit is configured to provide an output signal to the corresponding output pad based on the processed control signal.

[0090] In the above-mentioned embodiment, due to the setting of the first sub-layout area 201, the input signal can be pulled up to a high level even when the input signal is not connected, so the signal input terminal can be left floating. In addition, a second sub-layout area including a comparison unit is set up, and by comparing the input signal level with the reference voltage, the problem that the logic circuit unit composed of CMOS inverters cannot correctly identify the input high and low levels after irradiation, thereby causing functional failure, can be avoided.

[0091] In a preferred embodiment, the first ends 2041 of the third sub-layout area 203 and the fourth sub-layout area 204 are both arranged at one end of the second layout area 2 along the second direction away from the first layout area 1. The second ends 2042 of the first sub-layout area 201, the second sub-layout area 202, and the fourth sub-layout area 204 are all arranged at one end of the second layout area 2 along the second direction close to the first layout area 1.

[0092] In other words, in each second layout area 2, the second ends 2042 of the first sub-layout area 201, the second sub-layout area 202 and the fourth sub-layout area 204 are arranged adjacent to the first layout area 1, that is, close to the edge of the layout; the first ends 2041 of the third sub-layout area 203 and the fourth sub-layout area 204 are arranged away from the first layout area 1, that is, away from the edge of the layout.

[0093] In other words, for each second layout area 2, there is a side that is relatively closer to the layout edge, namely the first layout area 1, namely the outer side, and an inner side that is relatively farther away from the layout edge. The second ends 2042 of the first sub-layout area 201, the second sub-layout area 202 and the fourth sub-layout area 204 are located on the outer side of the second layout area 2, and the first ends 2041 of the third sub-layout area 203 and the fourth sub-layout area 204 are located on the inner side of the layout.

[0094] In a preferred embodiment, the first sub-layout area 201 and the second sub-layout area 202 are arranged along a first direction.

[0095] In a preferred embodiment, the first sub-layout area 201 , the second sub-layout area 202 and the third sub-layout area 203 are all rectangular.

[0096] In a typical embodiment, Figure 4 As shown, the fourth sub-layout area 204 is a right-angle L-shape, the third sub-layout area 203 and the first end 2041 of the fourth sub-layout area 204 are arranged along the first direction, the first sub-layout area 201 and the second sub-layout area 202 are arranged above the first end 2041 of the third sub-layout area 203 and the fourth sub-layout area 204; in other words, the combination of the third sub-layout area 203 and the fourth sub-layout area 204 can also be approximately regarded as a right-angle L-shape, the first sub-layout area 201 and the second sub-layout area 202 are arranged on the inner side of the corner of the fourth sub-layout area 204; that is, the combination of the first sub-layout area 201 and the second sub-layout area 202 is partially surrounded by the combination of the third sub-layout area 203 and the fourth sub-layout area 204, and the unsurrounded part is arranged adjacent to the first layout area 1 and the possible adjacent second layout area 2. The above layout arrangement can effectively utilize the chip area to a greater extent, increase the area of ​​the output unit, such as the MOS tube, and thus increase the output driving capability.

[0097] In addition, the first sub-layout area 201 is arranged at the outermost side of the second layout area 2, close to the first layout area 1, which is helpful for metal wiring and can reduce the routing distance during input wiring. Specifically, it is convenient to wire with the input pad in the first layout area 1.

[0098] The second sub-layout area 202 is adjacent to the first sub-layout area 201, which is convenient for receiving the signal from the first sub-layout area 201. At the same time, the shape and position of the second sub-layout area 202 can make one side of the in-phase input end of the comparison unit close to the first sub-layout area 201, and the output end can be set on the side of the second sub-layout area 202 adjacent to the third sub-layout area 203, which is convenient for controlling the signal to enter the third sub-layout area 203.

[0099] In a typical embodiment, there are multiple second layout areas 2 arranged in an array; among the multiple second layout areas 2, the distance between two adjacent ones is 15 μm to 20 μm.

[0100] In a typical embodiment, the sub-layout area spacing between the first layout area 1 and the adjacent second layout area 2 is 20 μm to 30 μm. For example, the spacing between the first layout area 1 and any of the adjacent first sub-layout area 201, second sub-layout area 202, third sub-layout area 203 and the second end 2042 of the fourth sub-layout area 204 is in the range of 20 μm to 30 μm.

[0101] In a preferred embodiment, for each sub-layout area in the same second layout area 2, the distance between the first sub-layout area 201 and the second sub-layout area 202 is 6 μm to 10 μm; the distance between the second sub-layout area 202 and the third sub-layout area 203 is 6 μm to 10 μm; the distance between the third sub-layout area 203 and the fourth sub-layout area 204 is 6 μm to 10 μm. Of course, the distances between adjacent sub-layout areas can be the same or different.

[0102] The preset spacings in the aforementioned optional schemes can meet the requirements for the circuit's electrical performance indicators, and also meet the requirements for the layout design of the process processing. On this basis, the layout of each layout area and sub-layout area is coordinated to facilitate metal wiring, and can also make the signal flow smoother and more effective, reducing the space waste caused by unnecessary metal wiring and the reliability risks caused by long-distance routing.

[0103] In a preferred embodiment, the first sub-layout area 201 is provided with a first resistor R1, one end of the first resistor R1 is connected to the power pad VCC, and the other end is connected to the corresponding input pad (such as Figure 3 one of A1 to A6 in the table above).

[0104] A comparison unit is provided in the second sub-layout area 202. The comparison unit includes a comparator COMP, whose in-phase input terminal is connected to a corresponding input pad (such as Figure 3 One of A1 to A6 in the figure), the inverting input terminal is used to access the reference voltage.

[0105] The logic circuit unit includes a plurality of cascaded inverters, and an input end thereof is connected to an output end of the aforementioned comparison unit.

[0106] The output unit includes a first NMOS transistor N1, the gate of the first NMOS transistor N1 is connected to the output end of the logic circuit unit, the source and the substrate are connected to the ground pad GND, and the drain is connected to the corresponding output pad (such as Figure 3 The drain can be one of Y1 to Y6, and the drain can also be used to connect a pull-up resistor.

[0107] In a preferred embodiment, the second sub-layout area 202 is also provided with a second resistor R2 and a third resistor R3; one end of the second resistor R2 is connected to the power pad VCC, and the other end is connected to the inverting input terminal of the comparator COMP; one end of the third resistor R3 is connected to the inverting input terminal of the comparator COMP, and the other end is connected to the ground pad GND.

[0108] In a preferred embodiment, the second resistor R2 and the third resistor R3 both include a plurality of resistors connected in series; the plurality of resistors in the second resistor R2 and the plurality of resistors in the third resistor R3 have the same specifications, and the number may be the same or different.

[0109] In a preferred embodiment, the comparator COMP includes a first PMOS transistor P1 and a second PMOS transistor P2 of the same specification. The gate of the first PMOS transistor P1 serves as a non-inverting input terminal, and the gate of the second PMOS transistor P2 serves as an inverting input terminal.

[0110] In a preferred embodiment, the comparator COMP further comprises:

[0111] The third PMOS tube P3 has a source and a substrate connected to the power pad VCC, a gate connected to the ground pad GND via a resistor, and a drain connected to the sources of the first PMOS tube P1 and the second PMOS tube P2; the second NMOS tube N2 has a drain connected to the drain of the first PMOS tube P1, and a source and a substrate connected to the ground pad GND; the third NMOS tube N3 has a drain connected to the drain of the second PMOS tube P2, and a source and a substrate connected to the ground pad GND; wherein the gates of the second NMOS tube N2 and the third NMOS tube N3 are both connected to the drain of the first PMOS tube P1; the substrates of the first PMOS tube P1 and the second PMOS tube P2 are both connected to the power pad VCC, and the drain of the second PMOS tube P2 serves as the output end of the comparator COMP.

[0112] In a preferred embodiment, the number of inverters in the logic circuit unit is an odd number.

[0113] In a preferred embodiment, if Figure 3 As shown, the power pad VCC and the ground pad GND are symmetrically arranged at both ends of the first layout area 1 along the first direction; the input pad and the output pad corresponding to the same second layout area 2 are arranged adjacent to each other, for example Figure 3 A1 and Y1, A2 and Y2 in.

[0114] In an optional embodiment, three groups of input pads / output pads are respectively arranged on both sides of the connection line between the power pad VCC and the ground pad GND in the first layout area 1. That is, a total of six groups of input / output pads are included, corresponding to the aforementioned six second layout areas 2, respectively, to provide signal input / output for the six paths in the output buffer.

[0115] In a preferred embodiment, in the first layout area 1, both sides of each input pad or output pad are provided with electrostatic protection structures (not shown in the figure).

[0116] The embodiments of the present application are not limited to Figure 3 The multi-channel output buffer shown in the figure may also be a single-channel output buffer, that is, the chip layout only includes one second layout area 2.

[0117] The output buffer chip provided in the embodiment, wherein the truth table of any path is shown in Table 1.

[0118] Table 1 Truth table

[0119] Input (A) Output (Y) L L H Z

[0120] In Table 1, H represents a high level, L represents a low level, and Z represents a high impedance state.

[0121] After the chip is packaged, illustratively, the definition of each package pin is as shown in Table 2.

[0122] Table 2 Pin Definition

[0123]

[0124] An embodiment of the present application also provides an output buffer circuit. This circuit product includes an output buffer using the layout structure described in any one of the aforementioned embodiments, and an external resistance unit.

[0125] like Figure 1 As shown, the external resistor unit includes a fourth resistor R4, one end of the fourth resistor R4 is used to connect to the external power supply VDD, and the other end is connected to the output pad to provide a pull-up resistor for the output unit.

[0126] In the specific operation process, when no external input signal is connected to the output buffer of the above layout, or the output buffer circuit including the output buffer, the circuit input terminal in each channel is equivalent to being connected to a high level, so the input pad can be left floating. When an external input signal is connected, the signal enters the comparison unit in the second sub-layout area 202 via the input pad of the first layout area 1 and the pull-up resistor (i.e., the first resistor R1) in the first sub-layout area 201. The comparison unit compares the external signal with the reference voltage and generates a control signal.

[0127] The control signal is output to the logic circuit unit in the third sub-layout area 203. The logic circuit unit performs logic processing on the received control signal and outputs it to the output unit in the fourth sub-layout area 204, wherein the NMOS tube N1 processes the received signal and connects it to the external pull-up resistor (fourth resistor R4) through the output pad of the first layout area 1, and outputs it through the output pad.

[0128] In summary, compared with the prior art, the output buffer of the layout structure provided in the embodiment of the present application, and the circuit including the output buffer, are additionally provided with two sub-layout areas including a first resistor and a comparison unit, which can not only make the signal input terminal suspended, but also improve the problem of the circuit input terminal level flip point being too low due to the excessive drift of the MOS tube turn-on voltage after a long period of irradiation in the high-voltage CMOS process integrated circuit with a relatively thick gate oxide layer, resulting in parameter deviation or functional failure, thereby ensuring the correctness of signal transmission and the reliability of chip functions, as well as compatibility with TTL levels.

[0129] At the same time, the technical solution of the present application can realize the function of the improved circuit by rationally laying out each layout area, especially optimizing and adjusting the position, shape and spacing of each sub-layout area in the second layout area. On the other hand, the position and placement of each sub-layout area are adapted to the signal flow, while meeting the requirement of being close to the pad, thereby facilitating metal wiring and reducing the area, while improving the reliability of the product.

[0130] The above is only a partial specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with the technical field within the technical scope disclosed in the embodiments of the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A layout structure of an output buffer, characterized in that: Comprising a first layout area (1) and at least one second layout area (2), wherein the first layout area (1) is arranged at the edge of the chip and surrounds the at least one second layout area (2); The first layout area (1) is provided with a power supply pad, a ground pad, and an input pad and an output pad corresponding one-to-one to the at least one second layout area (2); The second layout area (2) includes: A first sub-layout area (201), adjacent to the first layout area (1), for receiving an input signal from a corresponding input pad; A second sub-layout area (202) is provided with a comparison unit, and is adjacent to the first sub-layout area (201); the comparison unit is configured to compare the input signal with a reference voltage and provide a control signal based on the comparison result; A third sub-layout area (203) is provided with a logic circuit unit, and is adjacent to the second sub-layout area (202); the logic circuit unit is configured to receive and enhance the driving capability of the control signal, and provide a processed control signal; The fourth sub-layout area (204) is provided with an output unit, comprising a first end (2041) extending along a first direction and a second end (2042) extending along a second direction, the first direction and the second direction being perpendicular; the first end (2041) is adjacent to the third sub-layout area (203), and the second end (2042) is adjacent to the first layout area (1); the output unit is configured to provide an output signal to a corresponding output pad based on the processed control signal.

2. The layout structure according to claim 1, characterized in that: The first ends (2041) of the third sub-layout area (203) and the fourth sub-layout area (204) are both arranged at an end of the second layout area (2) away from the first layout area (1) along the second direction.

3. The layout structure according to claim 1 or 2, characterized in that: The first sub-layout area (201) and the second sub-layout area (202) are arranged along a first direction; The second ends (2042) of the first sub-layout area (201), the second sub-layout area (202) and the fourth sub-layout area (204) are all arranged at an end of the second layout area (2) close to the first layout area (1) along the second direction.

4. The layout structure according to claim 1 or 2, characterized in that: The second layout areas (2) are multiple and arranged in an array, and two second layout areas (2) adjacent to each other along the second direction are symmetrically arranged.

5. The layout structure according to any one of claims 1 to 4, characterized in that: The first sub-layout area (201) is provided with a first resistor, one end of the first resistor is connected to the power pad, and the other end is connected to the corresponding input pad; The comparison unit comprises a comparator, a non-inverting input terminal of the comparator is connected to a corresponding input pad, and an inverting input terminal is used to access a reference voltage; The logic circuit unit includes a plurality of cascaded inverters, and an input end of the logic circuit unit is connected to an output end of the comparison unit; The output unit comprises a first NMOS tube, the gate of the first NMOS tube is connected to the output end of the logic circuit unit, the source and substrate are connected to the ground pad, the drain is connected to the corresponding output pad, and the drain is also used to connect the pull-up resistor.

6. The layout structure according to claim 5, characterized in that: The second sub-layout area (202) is also provided with a second resistor and a third resistor; One end of the second resistor is connected to the power pad, and the other end is connected to the inverting input terminal of the comparator; One end of the third resistor is connected to the inverting input terminal, and the other end is connected to the ground pad.

7. The layout structure according to claim 6, characterized in that: The second resistor and the third resistor each include a plurality of resistors connected in series; The multiple resistors in the second resistors have the same specifications as the multiple resistors in the third resistors, and the number is the same or different.

8. The layout structure according to claim 5, characterized in that: The comparator comprises: A first PMOS tube and a second PMOS tube with the same specifications, the gate of the first PMOS tube serves as the in-phase input terminal, and the gate of the second PMOS tube serves as the inverting input terminal; substrates of the first PMOS tube and the second PMOS tube are both connected to the power pad, and the drain of the second PMOS tube serves as the output terminal of the comparison unit; A third PMOS tube, whose source and substrate are used to connect to the power pad, whose gate is connected to the ground pad via a resistor, and whose drain is connected to the source of the first PMOS tube and the second PMOS tube; A second NMOS tube, a drain electrode of which is connected to the drain electrode of the first PMOS tube, and a source electrode and a substrate of which are connected to the ground pad; A third NMOS tube, a drain electrode of which is connected to the drain electrode of the second PMOS tube, and a source electrode and a substrate of which are connected to the ground pad; in, The gates of the second NMOS tube and the third NMOS tube are both connected to the drain of the first PMOS tube.

9. The layout structure according to claim 5, characterized in that: The number of inverters in the logic circuit unit is an odd number.

10. The layout structure according to claim 1 or 2, characterized in that: The power pad and the ground pad are symmetrically arranged at two ends of the first layout area (1) along a first direction; The input pads and the output pads corresponding to the same second layout area (2) are arranged adjacent to each other.

11. An output buffer circuit, characterized in that: comprising an output buffer and at least one external resistor unit; The output buffer adopts the layout structure according to any one of claims 1 to 10; The external resistor unit includes a fourth resistor, one end of which is used to connect to an external power source, and the other end of which is connected to a corresponding output pad in the output buffer, so as to provide a pull-up resistor for the corresponding output unit.

Images