SiC optically controlled bipolar power transistor with vertically shielded emitter region

Abstract

The application discloses a SiC light-controlled bipolar power transistor with an emission area vertical shielding well, comprising: an emitter metal, an n-type substrate, an n-type emission area, an n-type pressure-bearing area, and a plurality of isolation wells distributed in the top area of the n-type pressure-bearing area, which are sequentially stacked from bottom to top; an n-type shielding layer arranged on the entire surface of the n-type pressure-bearing area; a p-type base area arranged in the central area of the surface of the n-type shielding layer; an n-type collector area above the p-type base area; a collector metal arranged in the central area of the surface of the n-type collector area; and a SiO2 oxide layer around the surface layer; the n-type substrate is made of 4H-SiC material; the isolation well and the n-type shielding layer are in an intrinsic state; the SiO2 oxide layer is arranged on the surface of the p-type base area except the area of the collector metal, and is arranged outside the p-type base area and the n-type collector area and in contact with the surface of the n-type shielding layer. The application can improve the high-voltage resistance of the power transistor, better control the off ability, and simplify the circuit design.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of power transistors, and particularly relates to a SiC photo-controlled bipolar power transistor with vertical shielding well in the emitter region. BACKGROUND

[0002] SiC material has excellent characteristics such as wide band gap, high critical breakdown field, high electron saturation velocity and high thermal conductivity, which makes SiC power devices very suitable for high temperature, high voltage and high power application scenarios. For compound semiconductor materials, there is an inverse proportional relationship between the band gap and the cut-off wavelength of the photovoltaic effect. For the 3.27eV band gap of SiC, the cut-off wavelength is near 280nm. Therefore, wide band gap semiconductors represented by SiC are very sensitive to light. Illuminating the base region of the SiC transistor with light of a specific wavelength can achieve the purpose of light control of the base region. Compared with electrically controlled power transistors, photo-controlled power transistors not only have the advantage of breakdown capability, but also can avoid electromagnetic interference and simplify the driving circuit when designing the circuit. Compared with other wide band gap semiconductor photoelectric materials such as aluminum gallium nitride, the preparation technology of SiC is more mature and the process is more advanced. It can be epitaxially grown, and the epitaxial quality is very high. It can directly form an oxide layer by thermal oxidation, and the process steps are simple. In nature, the ultraviolet waveband with a wavelength less than 280nm is called the solar blind waveband. The ultraviolet waveband from the sun in the solar blind waveband is completely absorbed by the atmosphere, and the environmental interference is very low. Therefore, the photo-controlled power transistor switch in the solar blind ultraviolet waveband has good performance, and has great application prospects in the fields of large-scale integrated circuits, automobiles, energy, and harsh environment monitoring.

[0003] SiC power transistor devices are currently mainly in electrically controlled mode, and are three-terminal devices. The emitter region, base region and collector region all need to be connected to electrodes. For the structure, since the three terminals need to be connected to electrodes, the electrically controlled power transistors used in integrated circuits all adopt a lateral horizontal structure.

[0004] The traditional vertical structure SiC photoelectric transistor is grown by epitaxy, which is the most commonly used single crystal thin film growth technology for SiC preparation at present, and has the advantages of fast growth speed and good process stability. In the preparation process, the emitter N region, base P region and collector N region are successively epitaxially grown on an N-type substrate, and then the preparation is completed through steps such as trench etching, electrode sputtering, thermal annealing and thermal oxidation to form an oxide layer.

[0005] In the final process of SiC device production, an insulating passivation layer needs to be prepared on the surface to protect the device. For SiC, the mainstream passivation layer generation technology at present is to directly form SiO2 by thermal oxidation at high temperature.

[0006] However, the traditional SiC power transistor is a three-terminal device, and the base region needs to be connected to an electrode, which is not suitable for vertical devices. The current distribution of the lateral power transistor is very uneven, and it is very easy to generate a current aggregation point at the horizontal injection well side edge, which leads to a very easy breakdown. In addition, since the base region needs to be connected to an electrode, the ohmic contact of SiC must be considered, so the process is more complex, and the design of the doping concentration needs to be improved. However, the base region needs to be designed as a pressure-bearing region for high-voltage power devices, and the design of the doping concentration needs to be reduced, which is difficult to balance.

[0007] In addition, the light-controlled power transistor with a horizontal structure has a very uneven current distribution, and it is very easy to generate a current aggregation point at the horizontal injection well side edge, which leads to a very easy breakdown. In addition, the light-controlled power transistor with a horizontal structure has a part directly illuminated and another part blocked by the collector region, resulting in a difference in light exposure and uneven generation of photo-generated carriers, which also leads to uneven current distribution.

[0008] Therefore, it is urgent to design a light-controlled power transistor to solve the problem of the base region in view of the shortcomings of the traditional electrically controlled power transistor. In addition, a light-controlled power transistor with a vertical structure is designed to solve the problem of uneven current distribution and easy breakdown at the inflection point and boundary point in view of the shortcomings of the traditional lateral light-controlled power transistor. SUMMARY

[0009] In order to solve the above-mentioned problems existing in the prior art, the present application provides a SiC light-controlled bipolar power transistor with a vertical shielding well in the emitter region and a preparation method thereof. The technical problems to be solved by the present application are solved by the following technical solutions:

[0010] In a first aspect, the embodiments of the present application provide a SiC light-controlled bipolar power transistor with a vertical shielding well in the emitter region, comprising:

[0011] The emitter metal, the n-type substrate, the n-type emitter region, the n-type pressure-bearing region, and the multiple isolation wells distributed in the top region of the n-type pressure-bearing region are sequentially stacked from bottom to top. An n-type shielding layer is arranged on the entire surface of the n-type pressure-bearing region. A p-type base region is arranged in the central region of the surface of the n-type shielding layer. An n-type collector region is located above the p-type base region. A collector metal is arranged in the central region of the surface of the n-type collector region. And a SiO2 oxide layer is arranged around the surface layer, wherein the n-type substrate is made of 4H-SiC material. The isolation well and the n-type shielding layer are in an intrinsic state. The SiO2 oxide layer is arranged on the surface of the p-type base region except the region of the collector metal, and is arranged on the outer side of the p-type base region and the n-type collector region, and is in contact with the surface of the n-type shielding layer.

[0012] In one embodiment of the present application, the junction depth of the plurality of isolation wells is 5-10 μm, the adjacent distance is 5-10 μm, the doping element is Al, and the doping concentration is 5e 16 cm -3 -1e 17 cm -3 .

[0013] In one embodiment of the present application, the thickness of the n-type shielding layer is 2-8 μm, and the doping concentration is 5e 16 cm -3 -1e 17 cm -3 .

[0014] In one embodiment of the present application, the thickness of the p-type base region is 0.5-3 μm, the doping element is Al, and the doping concentration is 5e 15 cm -3 -5e 16 cm -3 .

[0015] In one embodiment of the present application, the thickness of the n-type collector region is 0.3-0.5 μm, the doping element is N, and the doping concentration is 8e 17 cm -3 -2e 18 cm -3 .

[0016] In a second aspect, the present application provides a preparation method of a SiC photo-controlled bipolar power transistor with a vertical shielding well in the emitter region, which comprises the following steps:

[0017] Obtaining an n-type substrate, and sequentially preparing an n-type emitter region and an n-type pressure-bearing region on the front surface of the n-type substrate;

[0018] Injecting a plurality of isolation wells in the n-type pressure-bearing region, and preparing an n-type shielding layer on the entire surface of the n-type pressure-bearing region;

[0019] Forming a p-type base region on the n-type shielding layer;

[0020] Forming an n-type collector region on the p-type base region;

[0021] Sputtering to form an emitter metal on the back surface of the n-type substrate;

[0022] Etching isolation grooves on both sides of the n-type collector region until the surface of the n-type shielding layer is exposed;

[0023] Sputtering to form a collector metal in the central region of the surface of the n-type collector region;

[0024] Forming SiO2 oxide layer in the region of the n-type shielding layer and the surface of the n-type collector region except the region where the collector metal is located.

[0025] In one embodiment of the present application, a plurality of isolation wells are injected in the n-type pressure-bearing region, including:

[0026] Through a photoetching process, mask windows with a certain interval are photoetched on the surface of the n-type pressure-bearing region;

[0027] The well region injection is performed by using an ion injection process to form n-type intrinsic isolation wells; wherein the junction depth of the n-type intrinsic isolation well is 5 μm-10 μm, the distance between each injection well ranges from 5 μm to 10 μm, the doping element is Al, and the doping concentration ranges from 5e 16 cm -3 ~1e 17 cm -3 .

[0028] In one embodiment of the present application, an n-type shielding layer is prepared on the entire surface of the n-type pressure-bearing region, including:

[0029] On the entire surface of the n-type pressure-bearing region, an n-type shielding layer is formed by using a chemical vapor deposition device with a mixed gas of SiH4, CH4 and N2 as source gas and H2 as dilution gas; wherein the flow rate of SiH4 is 5 sccm, the flow rate of CH4 is 5 sccm-10 sccm, the flow rate of N2 is 0.01 sccm-0.1 sccm, the radio frequency power is 10 W-30 W, the annealing temperature is 900 °C-1150 °C, the thickness of the n-type shielding layer is 2 μm-8 μm, and the doping concentration ranges from 5e 16 cm -3 ~1e 17 cm -3 .

[0030] In one embodiment of the present application, a p-type base region is formed on the n-type shielding layer, including:

[0031] On the n-type shielding layer, a p-type base region is formed by using a chemical vapor deposition device with a mixed gas of SiH4, CH4 and N2 as source gas and H2 as dilution gas; wherein the flow rate of SiH4 is 5 sccm, the flow rate of CH4 is 5 sccm-10 sccm, the flow rate of N2 is 0.1 sccm-1 sccm, the radio frequency power is 10 W-30 W, the annealing temperature is 900 °C-1200 °C, the thickness of the p-type base region is 0.5 μm-3 μm, the doping element is Al, and the doping concentration ranges from 5e 15 cm -3 ~5e 16 cm -3.

[0032] In one embodiment of the present application, the n-type collector region is formed on the p-type base region, comprising:

[0033] The n-type collector region is formed on the p-type base region by using a chemical vapor deposition device with a mixed gas of SiH4, CH4 and N2 as a source gas and H2 as a dilution gas, wherein the flow rate of SiH4 is 5sccm, the flow rate of CH4 is 5sccm-10sccm, the flow rate of N2 is 0.1sccm-1sccm, the radio frequency power is 10W-30W, the annealing temperature is 900℃-1150℃, the thickness of the n-type collector region is 0.3μm-0.5μm, the doping element is N, and the doping concentration ranges from 8e 17 cm -3 -2e 18 cm -3 .

[0034] The present application has the following advantages:

[0035] The present application designs intrinsic isolation wells vertically arranged in the pressure-bearing region, which have low doping concentration, weak conductivity and vertical distribution. These isolation wells block the lateral transport of carriers to some extent, thereby reducing the possibility of current aggregation in a certain place in the horizontal direction and optimizing the high-voltage resistance of the device. Moreover, a low-doped intrinsic shielding layer is designed above the pressure-bearing layer. At the junction of the emitter region and the base region, the doping concentration of the reverse-biased emitter junction is lower, the space charge region is wider, and the anti-breakdown ability is stronger. The present application can improve the high-voltage resistance of the power transistor, better control the off ability, and simplify the circuit design. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1 A cross-sectional structure schematic diagram of a SiC photo-controlled bipolar power transistor with a vertical shielding well in the emitter region is provided in an embodiment of the present application.

[0037] Figure 2 A flowchart schematic diagram of a preparation method of a SiC photo-controlled bipolar power transistor with a vertical shielding well in the emitter region is provided in an embodiment of the present application.

[0038] Figures 3a to 3j A preparation process schematic diagram of a SiC photo-controlled bipolar power transistor with a vertical shielding well in the emitter region is provided in an embodiment of the present application.

[0039] Figure 4 A comparison diagram of the breakdown voltage of a SiC photo-controlled bipolar power transistor with a vertical shielding well in the emitter region and the prior art is provided in an embodiment of the present application.

[0040] REFERENCE NUMERALS:

[0041] 1. n-type substrate, 2. n-type emitter region, 3. n-type buffer region, 4. isolation well, 5. n-type shield layer, 6. p-type base region, 7. n-type collector region, 8. emitter metal, 9. collector metal, 10. SiO2 oxide layer. DETAILED DESCRIPTION

[0042] The application will be further described in details below in connection with specific embodiments, but the embodiments of the application are not limited thereto.

[0043] In a first aspect, the embodiments of the application provide a SiC photo-controlled bipolar power transistor with vertical shield well in emitter region, as shown in FIG. 1, which can include: Figure 1

[0044] The emitter metal 8, the n-type substrate 1, the n-type emitter region 2, the n-type buffer region 3, and the multiple isolation wells 4 distributed in the top region of the n-type buffer region 3 are sequentially stacked from bottom to top, the n-type shield layer 5 is arranged on the entire surface of the n-type buffer region 3, the p-type base region 6 is arranged in the central region of the surface of the n-type shield layer 5, the n-type collector region 7 is located above the p-type base region 6, the collector metal 9 is located in the central region of the surface of the n-type collector region 7, and the SiO2 oxide layer 10 is arranged around the surface layer, wherein the n-type substrate 1 is made of SiC material; the isolation well 4 and the n-type shield layer 5 are in intrinsic state; the SiO2 oxide layer 10 is arranged on the surface of the p-type base region 6 except the region of the collector metal 9, and is arranged outside the p-type base region 6 and the n-type collector region 7 and in contact with the surface of the n-type shield layer 5.

[0045] The n-type substrate 1 is made of SiC material, the doping element is N, the thickness can be 200 μm to 400 μm, and the doping concentration range can be 6e 18 cm -3 to 1e 19 cm -3 .

[0046] The thickness of the n-type emitter region 2 can be 5 μm to 50 μm, and the maximum value of the doping concentration gradient range can be 1e 18 cm -3 to 5e 18 cm -3 .

[0047] The thickness of the n-type buffer region 3 can be 10 μm to 40 μm, and the doping concentration range can be 8e 17 cm -3 to 1e 18 cm -3 .

[0048] ​The junction depth of the plurality of isolation wells 4 can be 5 μm to 10 μm, the adjacent distance range can be 5 μm to 10 μm, the doping element is Al, and the doping concentration range can be 5e 16 cm -3 ~ 1e 17 cm -3 . Due to the low doping concentration, intrinsic isolation wells are formed.

[0049] The thickness of the n-type shielding layer 5 can be 2 μm to 8 μm, and the doping concentration range can be 5e 16 cm -3 ~ 1e 17 cm -3 . The doping concentration thereof is the same as that of the isolation well 4, and due to the low doping concentration, a low-doped intrinsic shielding layer is formed.

[0050] The thickness of the p-type base region 6 can be 0.5 μm to 3 μm, the doping element is Al, and the doping concentration range can be 5e 15 cm -3 ~ 5e 16 cm -3 .

[0051] The thickness of the n-type collector region 7 can be 0.3 μm to 0.5 μm, the doping element is N, and the doping concentration range can be 8e 17 cm -3 ~ 2e 18 cm -3 .

[0052] The emitter metal 8 and the collector metal 9 are metal Ni, and the thickness can be 200 nm-250 nm.

[0053] The thickness of the SiO2 oxide layer 10 can be 0.5 μm to 1 μm.

[0054] In the design of a power transistor, since the transistor is a three-terminal device, electrodes must be prepared for the emitter region, the base region, and the collector region to connect the external circuit, which leads to the fact that the device design must use a lateral horizontal structure. The horizontal transistor has many disadvantages, including: the base region must form an ohmic contact with the electrode, the doping concentration design is complex, and the base region has weak anti-breakdown capability; in the horizontal structure, the current flows horizontally, and when the current flows from the base region to the collector region, it is inevitable that the current density will be large on the side of the collector region close to the base region and small on the side far away from the base region, which forms a current gathering point that is easy to form a breakdown point at the geometric corner of the collector junction, leading to premature breakdown of the device; finally, the electrically controlled power transistor is controlled to be turned off by the base region voltage, which is easy to be disturbed by the electric signal, and the design of the circuit driver is more complex.

[0055] To solve the above problems, the application provides a SiC photo-controlled bipolar power transistor with vertical shielding traps in an emitting area, which adopts a vertical structure, an emitting area electrode is below the device, a collecting area electrode is above the device, and a light window is above the device; an n-type pressure-bearing area is arranged above the n-type emitting area, and spaced apart isolation traps are arranged above the n-type pressure-bearing area; and an n-type shielding layer is arranged above the isolation traps, and has a low doping concentration and is in an intrinsic state.

[0056] The application uses a vertical structure instead of a horizontal structure, and current flows vertically, and the device structure is horizontally symmetrical, so that the current can be uniformly distributed in the entire pressure-bearing area, but even so, as the device size increases, the current distribution in the pressure-bearing area is uneven due to lattice defects and other reasons, the current is unevenly distributed in the horizontal direction, the current is gathered in a certain position, and the device is broken down in advance. Therefore, the application designs vertical intrinsic isolation traps in the pressure-bearing area, the isolation traps have a low doping concentration, a weak conductivity, and a vertical distribution, the isolation traps block the horizontal transport of carriers to a certain extent, thereby reducing the possibility of current gathering in a certain place in the horizontal direction, and optimizing the high-voltage resistance of the device. Moreover, a low-doped intrinsic shielding layer is arranged above the pressure-bearing layer, the doping concentration of the emitter junction is lower at the junction between the emitter and the base, the space charge region is wider, and the anti-breakdown capability is stronger.

[0057] Therefore, the application can improve the high-voltage resistance of the power transistor, better control the off ability, and simplify the circuit design.

[0058] Moreover, the photo-controlled power transistor provided by the application can be controlled by using 240nm-300nm ultraviolet light in the base area instead of the base voltage, which is different from the traditional photo-controlled transistor in that the photo-controlled p area and the pressure-bearing area are separated in structure, and the isolation area is designed in the pressure-bearing area, so that the breakdown capability is improved without affecting the photo-control capability.

[0059] In a second aspect, an embodiment of the application provides a preparation method of a SiC photo-controlled bipolar power transistor with vertical shielding traps in an emitting area, as shown in the accompanying drawings, which can include the following steps: Figure 2

[0060] S1, an n-type substrate is obtained, and an n-type emitting area and an n-type pressure-bearing area are sequentially prepared on the front surface of the n-type substrate;

[0061] Specifically, the n-type substrate can be made of 4H-SiC material, the doping element is N, the thickness can be 200-400μm, and the doping concentration range can be 6e 18 cm -3 ~1e 19 cm​-3 .

[0062] In the formation of n-type emitter region on the front surface of n-type substrate, a chemical vapor deposition device is used, with a mixed gas of SiH4, CH4 and N2 as source gas, H2 as diluent gas, the flow rate of SiH4 being 5 sccm, the flow rate of CH4 being 5 sccm-10 sccm, the flow rate of N2 being 0.01 sccm-0.1 sccm, in the epitaxial growth process, the growth time is evenly divided into five parts, and after each time node, the flow rate of N2 is adjusted to 20% of the previous one, forming a five-step concentration gradient doping. The radio frequency power is 10 W-30 W, the annealing temperature is 900 ℃-1150 ℃, the thickness of the n-type emitter region can be 5 μm-50 μm, and the maximum doping concentration gradient range can be 1e 18 cm -3 -5e 18 cm -3 ; see Figure 3a .

[0063] In the formation of n-type pressure-bearing region on the front surface of n-type emitter region, a chemical vapor deposition device is used, with a mixed gas of SiH4, CH4 and N2 as source gas, H2 as diluent gas, the flow rate of SiH4 being 5 sccm, the flow rate of CH4 being 5 sccm-10 sccm, the flow rate of N2 being 0.01 sccm-0.1 sccm, the radio frequency power being 10 W-30 W, the annealing temperature being 900 ℃-1150 ℃, the thickness of the n-type pressure-bearing region can be 10 μm-40 μm, and the doping concentration range can be 8e 17 cm -3 -1e 18 cm -3 . See Figure 3b .

[0064] S2, a plurality of isolated wells are injected in the n-type pressure-bearing region; and an n-type shielding layer is prepared on the entire surface of the n-type pressure-bearing region;

[0065] Among them, the plurality of isolated wells injected in the n-type pressure-bearing region can include:

[0066] Through a photolithography process, a mask window with a spacing arrangement is photoetched on the surface of the n-type pressure-bearing region;

[0067] An ion implantation process is used to implant the well region to form an n-type intrinsic isolated well;

[0068] Among them, the junction depth of the n-type intrinsic isolated well is 5 μm-10 μm, the distance between each implanted well can range from 5 μm to 10 μm, the doping element is Al, and the doping concentration range can be 5e 16 cm -3~1e 17 cm -3 This doping concentration is low in this field, thus forming an isolation well of the intrinsic state. Figure 3c shown.

[0069] Wherein, preparing an n-type shielding layer on the entire surface of the n-type pressure-bearing region comprises:

[0070] On the entire surface of the n-type pressure-bearing region, an n-type shielding layer is formed using a chemical vapor deposition device using a mixed gas of SiH4, CH4 and N2 as a source gas and H2 as a dilution gas; wherein the flow rate of SiH4 is 5sccm, the flow rate of CH4 is 5sccm~10sccm, the flow rate of N2 is 0.01sccm~0.1sccm, the RF power is 10W~30W, the annealing temperature is 900℃~1150℃, the thickness of the n-type shielding layer can be 2μm~8μm, and the doping concentration range can be 5e 16 cm -3 ~1e 17 cm -3 Its doping concentration range is consistent with that of the n-type intrinsic isolation well, thus obtaining an intrinsic state shielding layer. Figure 3d shown.

[0071] S3, forming a p-type base region on the n-type shielding layer;

[0072] Among them, this step includes:

[0073] On the n-type shielding layer, a p-type base region is formed using a chemical vapor deposition device with a mixed gas of SiH4, CH4 and N2 as the source gas and H2 as the dilution gas; wherein the flow rate of SiH4 is 5sccm, the flow rate of CH4 is 5sccm~10sccm, the flow rate of N2 is 0.1sccm~1sccm, the RF power is 10W~30W, the annealing temperature is 900℃~1200℃, the thickness of the p-type base region can be 0.5μm~3μm, the doping element is Al, and the doping concentration range can be 5e 15 cm -3 ~5e 16 cm -3 For this step, see Figure 3e shown.

[0074] S4, forming an n-type collector region on the p-type base region;

[0075] Specifically, on the p-type base region, a mixed gas of SiH4, CH4 and N2 is used as a source gas, H2 is used as a dilution gas, and an n-type collector region is formed by a chemical vapor deposition device; wherein the flow rate of SiH4 is 5sccm, the flow rate of CH4 is 5sccm-10sccm, the flow rate of N2 is 0.1sccm-1sccm, the radio frequency power is 10W-30W, the annealing temperature is 900℃-1150℃, the thickness of the n-type collector region can be 0.3μm-0.5μm, the doping element is N, and the doping concentration range can be 8e 17 cm -3 ~2e 18 cm -3 . This step is shown in Figure 3f .

[0076] S5, sputtering an emitter metal on the back of the n-type substrate;

[0077] Specifically, the emitter metal is sputtered below the n-type substrate formed in S1, a magnetron sputtering technology is used, the metal is Ni, the sputtering rate is 10nm / min-15nm / min, the sputtering power is 100w-120w, and the sputtering thickness can be 200nm-250nm. This step is shown in Figure 3g .

[0078] S6, etching an isolation groove on both sides of the n-type collector region until the surface of the n-type shielding layer is exposed;

[0079] Specifically, photolithography is performed on the n-type collector region, a mask is used to protect the center region of the p-type base region and expose the edge, the diameter ratio of the center region to the overall base region is 0.8-0.9, an inductively coupled plasma ICP dry etching process is used to form a side isolation groove. This step is shown in Figure 3h .

[0080] S7, sputtering a collector metal in the center region of the surface of the n-type collector region;

[0081] Specifically, photolithography is performed on the n-type collector region, a mask is used to expose the center region of the n-type collector region and protect other regions, the diameter ratio of the center region to the overall p-type base region is 0.3-0.4, a collector metal magnetron sputtering is performed, the metal is Ni, the sputtering rate is 10nm / min-15nm / min, the sputtering power is 100w-120w, and the sputtering thickness is 200nm-250nm. This step is shown in Figure 3i .

[0082] S8, forming a SiO2 oxide layer on the n-type shielding layer in the region of the isolation groove and on the surface of the n-type collector region except the region where the collector metal is located.

[0083] Specifically, the SiO2 layer is formed on the upper surface of the device by a thermal oxidation process, the oxygen flow rate is controlled at 300sccm-500sccm, the argon flow rate is 500sccm, the temperature range is 1400℃-1450℃, and the thickness is 0.5um-1um; please refer to Figure 3j

[0084] The SiC photo-controlled bipolar power transistor with the emission region vertical shielding well prepared by the preparation method has high high-voltage resistance, better turn-off control, and simpler circuit design.

[0085] Please refer to Figure 4 Compared with the breakdown voltage of the prior art, the reverse breakdown voltage of the device can be increased to about 1800V, and the breakdown performance is significantly improved.

[0086] It should be noted that in the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the devices or elements indicated must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0087] In addition, the terms "first" and "second" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first" and "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0088] ​In the description of the specification, reference to "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" means that a particular feature, structure, material, or characteristic being described is included in at least one embodiment or example of the application. The appearances of the phrases "in one embodiment", "in some embodiments", "an example", "a specific example", or "some examples" in various places in the specification are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples. Also, the terminology used in the description is for the purpose of describing particular embodiments only and is not intended to be limiting. It is also possible in the present application that additional or

[0089] The preferred embodiments of the application described above are intended to be merely exemplary and those skilled in the art will readily suggest modifications, equivalent replacements, improvements and the like without departing from the spirit and principles of the application. Any modification, equivalent replacement, improvement and the like made within the spirit and principles of the application are intended to be included in the scope of the application.

Claims

1. A SiC photonic bipolar power transistor with vertically shielded emitter region, characterized by, It comprises: The emitter metal (8), n-type substrate (1), n-type emitter region (2), n-type pressure bearing region (3) are stacked from bottom to top, and a plurality of isolation wells (4) are distributed in the top area of the n-type pressure bearing region (3), the n-type shielding layer (5) is arranged on the entire surface of the n-type pressure bearing region (3), the p-type base region (6) is arranged in the surface center region of the n-type shielding layer (5), the n-type collector region (7) is located above the p-type base region (6), the collector metal (9) is located in the surface center region of the n-type collector region (7), and the SiO2 oxide layer (10) is arranged around the surface layer, wherein the n-type substrate (1) is made of 4H-SiC material; the isolation well (4) and the n-type shielding layer (5) are in intrinsic state; the SiO2 oxide layer (10) is arranged on the surface of the p-type base region (6) except the area of the collector metal (9), and is arranged on the outside of the p-type base region (6) and the n-type collector region (7), and is in contact with the surface of the n-type shielding layer (5); The junction depth of the plurality of isolation wells (4) is 5-10 μm, the adjacent distance is 5-10 μm, the doping element is Al, and the doping concentration is 5e 16 cm -3 -1e 17 cm -3 ; the thickness of the n-type shielding layer (5) is 2-8 μm, the doping concentration is 5e 16 cm -3 -1e 17 cm -3 ; the thickness of the p-type base region (6) is 0.5-3 μm, the doping element is Al, and the doping concentration is 5e 15 cm -3 -5e 16 cm -3 ; the thickness of the n-type collector region (7) is 0.3-0.5 μm, the doping element is N, and the doping concentration is 8e 17 cm -3 -2e 18 cm -3 .

2. A method of fabricating a SiC photonic bipolar power transistor with vertically shielded emitter region, characterized in that, The method for preparing the SiC photo-controlled bipolar power transistor with vertical shielding well of emitter region according to claim 1 comprises: Obtaining an n-type substrate, and preparing an n-type emitter region and an n-type pressure bearing region on the front surface of the n-type substrate; Spacedly implanting a plurality of isolation wells in the n-type pressure bearing region; and preparing an n-type shielding layer on the entire surface of the n-type pressure bearing region; Forming a p-type base region on the n-type shielding layer; Forming an n-type collector region on the p-type base region; Sputtering an emitter metal on the back surface of the n-type substrate; Etching isolation trenches on both sides of the n-type collector region until the surface of the n-type shielding layer is exposed; Sputtering a collector metal in the surface center region of the n-type collector region; Forming a SiO2 oxide layer in the region of the isolation trench on the n-type shielding layer, and in the region of the surface of the n-type collector region except the region where the collector metal is located.

3. The method of fabricating a SiC photonic control bipolar power transistor with vertically shielded emitter region according to claim 2, characterized in that Spacedly implanting a plurality of isolation wells in the n-type pressure bearing region comprises: Through a photoetching process, a mask window with a spacing arrangement is photoetched on the surface of the n-type pressure bearing region; The ion implantation process is used to form n-type intrinsic isolation wells, wherein the junction depth of the n-type intrinsic isolation well is 5-10 μm, the distance between each implanted well is 5-10 μm, the doping element is Al, and the doping concentration is 5e 16 cm -3 ~1e 17 cm -3 .

4. The method of fabricating a SiC photonic control bipolar power transistor with vertically shielded emitter region according to claim 3, characterized in that Preparing an n-type shielding layer on the entire surface of the n-type pressure bearing region comprises: On the entire surface of the n-type pressure-bearing region, a mixed gas of SiH4, CH4 and N2 is used as a source gas, H2 is used as a dilution gas, and an n-type shielding layer is formed by a chemical vapor deposition device; wherein the flow rate of SiH4 is 5sccm, the flow rate of CH4 is 5sccm-10sccm, the flow rate of N2 is 0.01sccm-0.1sccm, the radio frequency power is 10W-30W, the annealing temperature is 900℃-1150℃, the thickness of the n-type shielding layer is 2μm-8μm, and the doping concentration range is 5e 16 cm -3 ~1e 17 cm -3 .

5. The method of fabricating a SiC photonic control bipolar power transistor with vertically shielded emitter region according to claim 2, wherein, Forming a p-type base region on the n-type shielding layer comprises: On the n-type shielding layer, a p-type base region is formed by a chemical vapor deposition device using a mixed gas of SiH4, CH4 and N2 as a source gas and H2 as a dilution gas; wherein the flow rate of SiH4 is 5sccm, the flow rate of CH4 is 5sccm-10sccm, the flow rate of N2 is 0.1sccm-1sccm, the radio frequency power is 10W-30W, the annealing temperature is 900℃-1200℃, the thickness of the p-type base region is 0.5μm-3μm, the doping element is Al, and the doping concentration ranges from 5e 15 cm -3 ~5e 16 cm -3 .

6. The method of fabricating a SiC photonic control bipolar transistor with vertically shielded emitter region according to claim 2, wherein, Forming an n-type collector region on the p-type base region comprises: On the p-type base region, an n-type collector region is formed by a chemical vapor deposition device using a mixed gas of SiH4, CH4 and N2 as a source gas and H2 as a dilution gas; wherein the flow rate of SiH4 is 5sccm, the flow rate of CH4 is 5sccm-10sccm, the flow rate of N2 is 0.1sccm-1sccm, the radio frequency power is 10W-30W, the annealing temperature is 900℃-1150℃, the thickness of the n-type collector region is 0.3μm-0.5μm, the doping element is N, and the doping concentration ranges from 8e 17 cm -3 -2e 18 cm -3 .

Images