Dynamic voltage frequency regulation for critical timing drive based on full-speed scan

Abstract

The invention relates to dynamic voltage frequency regulation based on key timing drive of full-speed scanning. An example method may include performing a first sensing operation associated with circuitry on a system on a chip (SoC) to determine a first data value; performing a second sensing operation associated with circuitry of a sensor of the SoC to determine a second data value; in response to the first data value and the second data value being the same data value, determining that a clock margin is sufficient; and determining that the clock margin is insufficient in response to the fact that the first data value and the second data value are different data values. In some examples, a voltage-frequency combination of operations associated with at least one operation of the SoC may be adjusted to a particular stored voltage-frequency combination of operations that provides sufficient timing margin.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to dynamic voltage frequency scaling (DVFS) based on critical timing driving of at-speed scan. Background Art

[0002] Various types of electronic devices, such as digital logic circuits and memory systems, can store and process data. Digital logic circuits are electronic circuits that process digital signals or binary information that can take two possible values ​​(usually represented as 0 and 1). Digital logic circuits can use logic gates to manipulate and transform digital signals or binary information. Digital logic circuits can be used in a wide range of electronic devices, including computers, calculators, digital clocks, and many other electronic devices that employ digital processing. Digital logic circuits can be designed to perform specific logical operations on digital inputs to produce digital outputs, and in some cases, can be combined to form more complex circuits to perform more complex operations. Generally speaking, power supply, voltage control, and / or clock control can vary the voltage or frequency during the operation of the digital logic. A memory device can include one or more memory devices that store data. The memory device can be, for example, a nonvolatile memory device or a volatile memory device. Generally speaking, a host system can utilize a memory system to store data at the memory device and retrieve data from the memory device. Summary of the Invention

[0003] On the one hand, the present application provides a method for dynamic voltage frequency adjustment, which includes: performing a first sensing operation associated with a circuit system on a system on a chip (SoC) to determine a first data value associated with the circuit system of the SoC; performing a second sensing operation associated with the circuit system of a sensor to determine a second data value associated with the circuit system of the sensor; in response to the first data value and the second data value being the same data value, determining that the clock margin of the SoC is sufficient; and in response to the first data value and the second data value being different data values, determining that the clock margin of the SoC is insufficient.

[0004] On the other hand, the present application provides a device for dynamic voltage-frequency adjustment, comprising: a controller configured to: perform a first sensing operation associated with a circuit system on a system on a chip (SoC) to determine a first data value associated with the circuit system of the SoC; perform a second sensing operation associated with a circuit system of a sensor to determine a second data value associated with the circuit system of the sensor; determine that a clock margin of the SoC is sufficient in response to the first data value and the second data value being the same data value; determine that the clock margin of the SoC is insufficient in response to the first data value and the second data value being different data values; and store a voltage-frequency operation combination associated with at least one operation of the SoC in a data structure.

[0005] On the other hand, the present application provides an apparatus for dynamic voltage-frequency adjustment, comprising: a voltage control component; a clock control component; and a controller coupled to the voltage control component and the clock control component, wherein the controller is configured to: perform a first sensing operation associated with a trigger on a system on a chip (SoC) to determine a first data value associated with the trigger of the SoC; perform a second sensing operation associated with an individual trigger of a sensor of the SoC to determine a second data value associated with the individual trigger of the sensor; in response to the first data value and the second data value being the same data value: gradually change a voltage, a timing frequency, or both associated with at least one operation of the SoC; perform additional sensing operations to determine: a subsequent data value associated with the trigger on the SoC; and a subsequent data value associated with the individual trigger of the sensor; store at least one voltage-frequency operation combination of the SoC associated with the first data value, the second data value, and the subsequent data value in a data structure; and configure the SoC to provide one operation of the stored voltage-frequency operation combination with sufficient margin. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description provided below and the accompanying drawings of various embodiments of the present disclosure.

[0007] Figure 1 An example system for dynamic voltage frequency scaling (DVFS) based on critical timing driving of at-speed scan according to some embodiments of the present disclosure is shown.

[0008] Figures 2A-2B Each shows an example system for dynamic voltage frequency scaling (DVFS) based on critical timing driving of at-speed scan according to some embodiments of the present disclosure.

[0009] Figures 3A-3BEach shows an example system including sensors for dynamic voltage frequency scaling (DVFS) based on critical timing driving of full-speed scan according to some embodiments of the present disclosure.

[0010] Figure 4 An example method for dynamic voltage frequency scaling (DVFS) of critical timing-driven at-speed scan is shown according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0011] Various aspects of the present disclosure relate to dynamic voltage frequency scaling (DVFS) driven by critical timing based on full-speed scanning. As will be described below, sensors can monitor critical timing of a circuit. The sensors can include triggers, such as individual triggers. The sensors can be included in a scan chain, as described herein. For example, because an increased clock frequency and / or decreased voltage changes the arrival timing of data compared to the arrival timing of data in a data storage element, the sensors can be configured to operate with different timing, such as a different frequency / phase, and the data storage element, such as a trigger of a system on chip (SoC) at a functionally critical endpoint where the data is sampled. In this way, the voltage and / or clock frequency can be adjusted to provide sufficient margin and thereby avoid any problems (e.g., data errors) that would otherwise be associated with operation with insufficient margin. For example, a specific voltage-frequency operating combination that is suitable (e.g., provides sufficient margin) can be selected from a plurality of stored voltage-frequency operating combinations, as described herein. However, at least due to the selection of a particular voltage-frequency operating combination appropriate for given conditions (e.g., a particular operating temperature, a particular lifetime, etc.), the approaches herein may also reduce the operating voltage of the SoC and / or increase the operating frequency of the SoC to improve SoC performance (e.g., reduce the power consumption of the SoC and / or reduce the latency associated with the operation of the SoC, etc.).

[0012] A voltage-frequency operating combination suitable for a given operating condition, such as operating temperature, operating duration (e.g., based on operating duration, number of cycles, etc.), can be determined via a sensor by gradually changing (e.g., decreasing or increasing) the voltage and / or gradually changing (e.g., decreasing or increasing) the clock frequency until the sensor detects a timing violation or the sensor detects no timing violation. For example, the voltage can be gradually decreased and / or the clock frequency can be gradually increased until the sensor detects a timing violation. Similarly, the voltage can be gradually increased and / or the clock frequency can be gradually decreased until the sensor detects no timing violation. Thus, the methods described herein can determine whether a timing violation exists, thereby permitting the subsequent determination of at least one voltage-frequency operating combination, such as the voltage-frequency operating combination described herein that produces sufficient margin (e.g., does not produce insufficient margin). For example, several voltage-frequency operating combinations can be stored in a data structure, thereby permitting the circuit to be configured at a given voltage-frequency operating combination to ensure that the circuit operates with sufficient or optimal margin across a variety of potential operating conditions, such as operating temperature, as described herein. However, the approaches herein may be less prone to exceeding the optimal margin, at least due to gradual changes in frequency and / or voltage. Thus, unlike other approaches, the approaches herein can employ sensors with fewer components (e.g., individual flip-flops, as compared to multiple flip-flops in the sensor), can reduce computational overhead, and can reduce any latency associated with voltage-frequency adjustments, thereby operating the circuit with the optimal margin. In one example, the voltage and / or clocking frequency of at least one operation of the SoC can be adjusted to a specific voltage-frequency operating combination stored in a data structure corresponding to operating conditions such as the operating temperature of the SoC, for example, in response to determining that the clock margin is insufficient. Thus, the approaches herein can improve the performance of circuits and / or devices, employing circuits operating with the optimal margin. For example, the approaches herein can permit circuit testing and subsequent dynamic voltage and frequency scaling (DVFS) to handle delays in logic 0-to-1 transitions (slow-rise faults) or delays in logic 1-to-0 transitions (slow-fall faults), among others.

[0013] Voltage and frequency scaling (VFS) can be used to match system power consumption to desired performance. The workload associated with a system (e.g., a computing system) can be monitored to determine the settings for voltage and clock speed, and the system's hardware can be configured appropriately. DVFS is a technique designed to reduce system power consumption or improve system performance by dynamically adjusting the system's voltage and frequency. This can take advantage of the fact that systems typically have discrete frequency and voltage settings. Dynamic voltage scaling to increase voltage may be referred to as overvolting, while dynamic voltage scaling to decrease voltage may be referred to as undervolting. Undervolting may be performed to save power, particularly in laptops and other mobile devices where energy is limited and battery-powered, or in rare cases to increase reliability. Overvolting may be performed to support higher frequencies for performance. The term "overvolting" may also be used to refer to increasing the static operating voltage of a component to allow operation at a higher speed (e.g., when overvolted).

[0014] The voltage and frequency applied to various components of the systems described herein can be dynamically adjusted based on the desired power and performance associated with voltage, frequency, and / or temperature data (in addition to other parameters, if monitored) collected during monitoring operations (e.g., AC (or full-speed) sweep operations, or other data collection and / or monitoring operations), and / or through dedicated embedded monitors, built-in self-test (BIST), or tables compiled using modeling and / or characterization, among other means. The voltage, frequency, and / or temperature data from monitoring operations (e.g., AC sweeps or other monitoring operations) can collect a large portion of the system's measured data and provide a more accurate way to adjust voltage and frequency for regulation. For example, measured data can refer to data that is not derived from simulations but rather from actual sweeps and is not extrapolated. Therefore, voltage and frequency regulation can provide benefits in systems that rely on instantaneous (or near-instantaneous) changes in the system's voltage, frequency, and temperature (e.g., application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), automated power management systems, etc.), where each parameter can affect one of the other parameters.

[0015] In some previous approaches, a clock frequency or period that utilizes excessive margin (e.g., excessive clock margin) can be used to avoid sampling incorrect data from locations in the SoC. As used herein, excessive clock margin refers to a slower clock or clocks with a longer period. For example, if the length of the clock period is sufficient to cover the propagation time of the data from the starting point (e.g., the rising edge of the clock) to the end point (e.g., the rising edge of the subsequent clock) plus some clock margin, then the data will be accurate at the time of sampling. However, using excessive clock margin can affect system performance by introducing excess time that is not necessary to provide accurate data.

[0016] Compared to these previous approaches, the methods and systems described herein employ sensors that can permit determination of a voltage-frequency operating combination that provides sufficient margin based on data propagation time determined using full-speed scanning, as described herein. Thus, the approaches herein can ensure that the system operates at a given voltage-frequency operating combination that provides sufficient clock margin, while also reducing the amount of latency and / or power consumption associated with the operation of the system compared to other approaches that, for example, employ excessive margin.

[0017] Figure 1 An example system 101 for critical timing DVFS based on at-speed scan, according to some embodiments of the present disclosure, is shown. System 101 may include an automatic test equipment (ATE) component 120 and a system-on-chip (SoC) 110. Components such as the ATE component 120 described herein may include various circuitry to facilitate operations associated with the component, such as testing a portion of an SoC (e.g., SoC 110). For example, ATE component 120 may include specialized circuitry in the form of an ASIC, an FPGA, a state machine, and / or other logic circuitry or software and / or firmware that may allow ATE component 120 to test other components and / or parameters of SoC 110. For example, ATE component 120 may be a simple computer-controlled digital multimeter, or a complex system containing dozens or more complex test instruments (real or simulated electronic test equipment), including SoCs and / or integrated circuits, capable of automatically testing and diagnosing faults in precision electronic package components or in connection with wafer testing.

[0018] Furthermore, SoC 110 may be an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or the like. SoC 110 includes a design unit 122 and a power management controller 124. Design unit 122 includes circuitry that may include one or more cores (e.g., "intellectual property (IP) cores"). As used herein, a "core" or "IP core" generally refers to one or more data blocks and / or logic blocks that form a constituent component of an application-specific integrated circuit or a field-programmable gate array. A "core" or "IP core" may be designed, constructed, and / or otherwise configured to perform specific tasks and / or functions within the systems described herein.

[0019] The power management controller 124 can communicate with various components, such as the temperature sensor 118 and the OTP 116, as described herein. The power management controller can also control various aspects of the operation of various components, such as the clock control component 128 and the voltage control component 130, as described herein. In some cases, the power management controller 124 can apply or determine whether to perform a DVFS operation using the one-time programmable (OTP) memory 116, the temperature sensor 118, and any other available inputs, as described below. In some examples, the power management controller 124 can be a power management integrated circuit (or PMIC) used to manage power for the system 101. While a PMIC can refer to a wide range of chips (or modules in a system-on-chip (SoC) device), most include several DC / DC converters. A DC-to-DC converter is an electronic circuit or electromechanical device that converts a direct current (DC) source from one voltage level to another. PMICs are often included in battery-operated devices, such as mobile phones and portable media players, to reduce the amount of space required.

[0020] ATE assembly 120 communicates with design unit 122 by " memory built-in self test " (MBIST) controller 112 and / or monitor assembly 115. Although mbist controller 112 has been described herein, embodiment is not limited thereto. For example, mbist is just example self-test controller / circuit, and can use the self-test circuit of any number. Monitor assembly 115 can refer to circuit system and / or the control logic that is used to control and manage monitoring operation (for example AC sweep operation, and other monitoring operation), as will be further described below. MBIST can refer to the industry standard method of testing embedded memory. MBIST is by carrying out read and write sequence according to test algorithm and operates. There are many industry standard test algorithms. The mbist controller produces the correct read and write sequence to all positions. When doing so, in the address that mbist uses and the data path, realize some extra test coverages. Additionally, the design unit 122 may communicate with the power management controller 124 via a clock (“CLK”) control component 128 and a voltage control component 130, which communicates with the power supply component 126 and communicates with the design unit 122 via the power supply component 126. The voltage control component 130 may control the voltage of the power supply component 126 according to instructions received from the power management controller 124.

[0021] Clock control component 128 may include various circuitry and / or logic incorporated into SoC 110 for clock control. Clock control component 128 may adjust clock timing based on instructions received from power management controller 124. Furthermore, since monitoring for AC (at-speed) testing typically requires two or more clock pulses in capture mode at a frequency equal to or substantially close to the functional clock frequency, without requiring clock control component 128, it may be necessary to provide full-speed pulses for ATE component 120 via input / output (I / O) pads of SoC 110. However, these I / O pads may have limitations in the maximum frequency they can support. Alternatively, clock control component 128 may use an internal phase-locked loop (PLL) clock in some instances to generate clock pulses for testing, and / or use an internal delay-locked loop (DLL) clock in other instances to generate clock pulses for testing. While clock control component 128 is described as providing timing for ATE component 120 based on instructions received from power management controller 124 and also providing clocks, embodiments are not limited thereto. For example, clock control component 128 may be used to adjust frequency according to instructions from power management controller 124 to dynamically adjust the frequency for DVF regulation, and a different clock control component (not shown) may be used separately for ATE component 120 and for clock timing of the ATE test itself.

[0022] In some instances, a PLL clock may refer to a circuit system and / or logic that generates an output signal whose phase is related to the phase of an input signal. Although there are several different types of PLL clock circuits, the simplest is an electronic circuit consisting of a variable frequency oscillator and a phase detector in a feedback loop. The oscillator generates a periodic signal, and the phase detector compares the phase of the signal with the phase of the input periodic signal, thereby adjusting the oscillator to maintain phase matching. Keeping the input and output phases in lock step also means keeping the input and output frequencies the same. Therefore, in addition to synchronizing the signals, a phase-locked loop can also track the input frequency, or it can generate a frequency that is an integer multiple of the input frequency. These characteristics are used for computer clock synchronization, demodulation, and frequency synthesis.

[0023] In other examples, a delay-locked loop (DLL) can be a digital circuit similar to a phase-locked loop (PLL), with the main difference being the absence of an internal voltage-controlled oscillator, which is replaced by a delay line. A DLL can be used to change the phase of a clock signal (a signal with a periodic waveform), often used to enhance the timing characteristics of integrated circuits (such as DRAM devices) from the time the clock rises to the time the data output is valid. DLLs can also be used for clock recovery (CDR). From an external perspective, a DLL can be viewed as a negative delay gate placed in the clock path of a digital circuit. The main component of a DLL can be a delay chain consisting of many delay gates connected from output to input. The input of the chain (and therefore the DLL) is connected to the clock to be negatively delayed. A multiplexer can be connected to each stage of the delay chain, and the selector of this multiplexer can be automatically updated by the control circuit to produce the negative delay effect. The output of the DLL can be the resulting negatively delayed clock signal.

[0024] Phase-locked loops (PLLs) are widely used in radio, telecommunications, computers, and other electronic applications. They can be used to demodulate signals, recover signals from noisy communication channels, generate stable frequencies from multiple input frequencies (frequency synthesis), or distribute precisely timed clock pulses in digital logic circuits such as microprocessors. Because a single integrated circuit can now provide a complete phase-locked loop building block, the technology is widely used in modern electronic devices, with output frequencies ranging from fractions of a hertz to several gigahertz. Furthermore, while phase-locked loops (PLLs) and delay-locked loops (DLLs) are provided in these examples, embodiments are not limited thereto. For example, any circuit capable of generating a clock or frequency change can be used.

[0025] In the case of DC (fixed) testing, the clock control component 128 can ensure that only one clock pulse is generated during the capture phase. Similarly, during AC (at-speed) testing, the clock control component 128 ensures that two or more clock pulses are generated during the capture phase, with the frequency of the capture phase equal to the frequency of the functional clock. Thus, the test clock used in a scan design can be routed through the clock control component 128, which controls the clock operation in scan mode (in both fixed and at-speed testing) and bypasses the functional clock in functional mode.

[0026] Generally speaking, an AC scan is configured to detect full-speed faults, and a DC scan is configured to detect stuck-at faults. The AC scan detects manufacturing defects that manifest as delays on the gate input-output ports. Therefore, in the AC scan, each port is tested for a logic 0-to-1 transition delay (a slow-rising fault) or a logic 1-to-0 transition delay (a slow-falling fault). Like stuck-at faults, full-speed faults can be at the input or output of the gate, so a simple 2-input AND gate has six possible full-speed faults. For example, suppose a slow-falling fault occurs at the output of the AND gate. A slower 1-to-0 transition at the output of the AND gate can occur and can affect the captured value. It is important to note that a full-speed fault can only be detected if the initial state in the flip-flop is '1' and the inputs are 010.

[0027] Referring back to the DC (stuck-at) scan, a DC scan models manufacturing defects that occur when a circuit node is shorted to the positive supply voltage, or "VDD" (stuck-at-1 fault), or to ground, "GND" (stuck-at-0 fault). This fault can be at the gate's input or output. Therefore, a simple 2-input AND gate has six possible stuck-at faults. For example, assume a stuck-at-0 fault is at the AND gate's output. It's important to note that for this example, there are three input ports in the circuit, so there are eight possible combinations of inputs or patterns: {000, 001, 010, 011, 100, 101, 110, 111}; of the eight patterns, only one, {011}, is capable of detecting this fault. Like the other patterns, in the presence of this stuck-at-0 fault, the expected output can be the same as the actual circuit output. Because the circuit in this example is small, the pattern that detects this fault is easily found. However, more complex circuits would use more complex stuck-at-0 fault patterns to test all possible fault locations using complex procedures and are contemplated within the scope of this disclosure.

[0028] In addition, Figure 1In this example shown in FIG, ATE component 120 can configure power management controller 124 via one-time programmable ("OTP") memory 116. However, embodiments are not limited thereto, and power management controller 124 can be configured via other methods or components. For example, programmable components other than one-time programmable components, such as memories that can be programmed multiple times or more than once, can be used. One-time programmable memory (OTP) can refer to a specific type of non-volatile memory (NVM) that only allows data to be written to the memory once. Once the memory has been programmed, it retains its value after power is lost (i.e., it is non-volatile). OTP memory can be used in applications that require reliable and repeatable data reading. Examples include boot code, encryption keys, and configuration parameters for analog, sensor, or display circuitry. OTP NVM is characterized by providing a low-power, small-footprint memory structure over other types of NVM, such as electronic fuses (eFuses) or electrically erasable programmable read-only memories (EEPROMs). As such, OTP memory can be used in microprocessors, display drivers, and power management ICs (PMICs).

[0029] The OTP memory 116 may include a voltage-frequency-temperature table ("VFT") 132. The VFT table 132 may be a set of cells for storing data related to the performance of an AC sweep operation and / or data related to the performance of a memory built-in self-test (MBIST) operation. For example, a monitoring operation (e.g., an AC sweep or other monitoring operation) may be performed by the monitor component 115 (or, in the case of an AC sweep, by an AC sweep controller, e.g., Figures 2A-2BThe AC scan controller 214 in the system 101 is executed, and data generated from the monitor operation (e.g., AC scan) is associated with parameters such as voltage (V), frequency (F), and temperature (T), and may be stored in the VFT table 132. The data stored in the VFT table 132 may be used to determine a specific frequency and / or voltage (e.g., a voltage-frequency operating combination associated with a specific operating condition such as an operating temperature) to configure the SoC 110 based on a specific frequency, temperature, and / or voltage. In some embodiments, while the monitor operation may occur at the time of manufacture and before use by a user, the monitor operation may be performed throughout the life cycle of the system 101 and / or SoC 110. For example, the monitor operation may be performed at startup of the SoC 110 at a specific time period after manufacture or after use by a user. The data associated with the frequency and / or voltage and / or temperature and the corresponding error rate and / or error amount may have changed from the initial monitor operation or several initial monitor operations associated with the time of manufacture. This may be due to the effects of cell aging, which may cause frequency, voltage, and / or temperature to change the efficacy and / or accuracy of the data stored in the cell over time. Accordingly, adjusted data values ​​based on such post-manufacturing scans may be stored in registers and / or specific locations within SoC 110 and may be used to modify how VFT table 132 adjusts the voltage and / or frequency and / or temperature values ​​of SoC 110.

[0030] Furthermore, a temperature sensor 118 can communicate with the power management controller 124 and can provide temperature data to the power management controller 124. The temperature sensor 118 can be embedded within the SoC 110 and can provide temperature values ​​at a number of different locations within the SoC 110. For example, the temperature sensor 118 can be embedded near a power transistor that is near a heat source of the SoC 110. While one temperature sensor 118 is described, embodiments are not limited thereto. For example, any number of temperature sensors can be positioned throughout the SoC 110, such as near a particular heat dissipating transistor, near the power supply component 126, and so on.

[0031] In some embodiments, system 101 may be deployed on or otherwise included in a system (e.g., a storage device, a memory module, or a hybrid of a storage device and a memory module). Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0032] In other embodiments, system 101 may be deployed on or otherwise included in a computing device, such as a desktop computer, a laptop computer, a server, a network server, a mobile computing device, a vehicle (e.g., an airplane, drone, train, car, or other transportation), an Internet of Things (IoT)-enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such computing device that includes memory and processing devices. As used herein, the term "mobile computing device" generally refers to a handheld computing device having a tablet or phablet form factor. Generally speaking, a tablet form factor may include a display screen between approximately 3 inches and 5.2 inches (measured diagonally), while a phablet form factor may include a display screen between approximately 5.2 inches and 7 inches (measured diagonally). However, examples of a "mobile computing device" are not limited thereto, and in some embodiments, a "mobile computing device" may refer to an IoT device, as well as other types of edge computing devices.

[0033] Such a computing device may include a host system coupled to a memory system (e.g., one or more storage devices, memory modules, or a combination thereof). The host system may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an SSD controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system uses the storage devices, memory modules, or a combination thereof, for example, to write data to and read data from the storage devices, memory modules, or a combination thereof.

[0034] In these examples, the host system may include a processing unit, such as a central processing unit (CPU), configured to execute an operating system. In some embodiments, the processing unit may execute a complex instruction set computer architecture, such as x86 or other architecture suitable for use as the host system's CPU.

[0035] The host system can be coupled to the memory system via a physical host interface. Examples of a physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), a Double Data Rate (DDR) memory bus, a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting Double Data Rate (DDR)), Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface can be used to transfer data between the host system and the memory system. When the memory system is coupled to the host system via a PCIe interface, the host system can further utilize an NVM Express (NVMe) interface to access the components. The physical host interface can provide an interface for transferring control, address, data, and other signals between the memory system and the host system. Generally speaking, the host system can access multiple memory subsystems via the same communication connection, multiple independent communication connections, and / or a combination of communication connections.

[0036] The system may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0037] Some examples of non-volatile memory devices include NAND-type flash memory and write-in-place memory, such as three-dimensional cross-point ("3D cross-point") memory devices, which are cross-point arrays of non-volatile memory cells. The cross-point array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in bulk resistance. Furthermore, compared to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without first erasing them. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0038] Although nonvolatile memory components such as a three-dimensional cross-point array of nonvolatile memory cells and NAND-type memory (e.g., 2D NAND, 3D NAND) are described, the memory device may be based on any other type of nonvolatile memory or storage device, such as read-only memory (ROM), phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0039] The memory system may also include additional circuitry or components. In some embodiments, the memory system may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from a memory system controller and decode the addresses to access the memory devices.

[0040] In some embodiments, a memory device may include a local media controller that operates with a memory system controller to perform operations on one or more memory cells of the memory device. For example, an external controller may externally manage the memory device (e.g., perform media management operations on the memory device). In some embodiments, the memory device is a managed memory device, which is a raw memory device combined with a local controller to perform media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0041] While the non-limiting examples herein are generally described in terms of applicability to memory systems and / or memory devices, embodiments are not limited thereto, and aspects of the present disclosure may also be applicable to systems on a chip, computing systems, data collection and processing, storage, networking, communications, power, artificial intelligence, control, telemetry, sensing and monitoring, digital entertainment, and other types of systems and / or devices, and thus aspects of the present disclosure may be applied to these components to provide critical timing DVFS based on full-speed scan, as described herein.

[0042] Figure 2A An example system for critical timing DVFS based on full-speed scan according to some embodiments of the present disclosure is shown. Figure 1 , Figure 2A May include the same and / or similar components. For example, Figure 2A Shows something like Figure 1 ATE 220 and similar ATE components 120 in Figure 1 210 of the system on chip (SoC) 110 in the embodiment of the present invention. The ATE 220 may communicate with the SoC 210. The SoC 210 may include a design unit 222. The ATE 220 may communicate with the design unit 222. For example, the ATE 220 may communicate with the design unit 222 through the MBIST controller 212. The ATE 220 may configure the SoC 210. The SoC 210 may include a power management controller 224. The ATE 220 may communicate with the power management controller 224. For example, the ATE 220 may communicate with the power management controller 224 through the OTP memory 216. The ATE 220 may control the design unit 222 through the clock control component 228, the voltage control component 230, and the power supply 226. The temperature sensor 218 may communicate with the power management controller 224. However, Figure 1 The difference is that in Figure 2A In place of the monitor component 115 , an AC sweep controller 214 is shown for more specific performance of an AC sweep operation, which is a subset of the general monitoring operation described above.

[0043] Figure 2B An example system for critical timing DVFS based on full-speed scan according to some embodiments of the present disclosure is shown. Figure 1 and Figure 2A , Figure 2B May include the same and / or similar components. For example, Figure 2B Shows something like Figure 1 ATE 220 and similar ATE components 120 in Figure 1 The SoC 210 may include a system on chip (SoC) 110 in the embodiment of the present invention. The SoC 210 may include an ATE 220 through an MBIST controller 212 and an AC scan controller 214 (similar to Figure 2A ) controlled design unit 222. SoC 210 may also include a power management controller 224, which is configured by ATE 220 through OTP 216 and may control clock control components 228, voltage control components 230, and power supply 226. Temperature sensor 218 may communicate with power management controller 224.

[0044] However, with Figure 1 and Figure 2A The difference is that in Figure 2B2 shows circuitry 234 in communication with AC scan controller 214. Circuitry 234 may be, for example, circuitry associated with a nonvolatile memory device, such as a NAND flash memory array in some instances. As additional examples, the memory array may be a storage class memory (SCM) array or other such memory array, such as a three-dimensional crosspoint (3D crosspoint) memory array, a ferroelectric RAM (FRAM) array, or a variable resistance memory array such as PCRAM, RRAM, or a spin torque transfer (STT) array. Circuitry 234 may be used to store scan vectors or other test program data that the AC scan controller 214 can operate autonomously without the need for ATE 220. Furthermore, for example, as described above, AC scans performed during the lifecycle of the SoC 110, 210 may provide additional voltage, frequency, temperature, and / or error data that may be stored in circuitry 234. For example, OTP 216 may be prevented from being written to (because it is a one-time programmable memory and may have already been written to initially). In this case, stored AC scan data may be accessed from another reprogrammable memory to modify the analysis of scan data already stored in voltage-frequency-temperature (VFT) table 232 in OTP 216. VFT table 232 storing scan data may be adjusted based on the additional scan data stored in circuitry 234 to modify frequency and / or voltage and / or temperature and minimize and / or attempt to avoid errors in SoC 210. In some examples, OTP 216 may be any other memory, such as a reprogrammable memory, etc.

[0045] Figure 3A An example system 331-1 including a sensor 338 for critical timing DVFS based on full-speed scan according to some embodiments of the present disclosure is shown. Example system 331-1 employs a sensor 338 that is set to sample data at an earlier clock arrival (e.g., a negative clock offset) than a functionally critical endpoint (e.g., an endpoint at a flip-flop 333-4) under stricter conditions. This example helps prevent marginal setting violations (e.g., timing violations) in the timing of system 331-1, such as in the clock frequency.

[0046] That is, the system 331-1 may include a power management controller, such as the power management controller described herein. The power management controller 124 may use the one-time programmable (OTP) memory 116, the temperature sensor 118, and any other available inputs to apply DVFS operations, as will be described below. The power management controller may be similar to Figure 1 The power management controller 124 and / or Figures 2A-2BLikewise, the system 331-1 may include a power supply component (not shown), a clock control component 370, and a voltage control component (not shown), such as those described herein. Figure 1 Design units such as design unit 122 in FIG. 1 may be controlled by a power management controller via a clock (“CLK”) control component and a voltage control component that communicate with the power supply. The voltage control component may control the voltage of the power supply based on instructions received from the power management controller. In some examples, the power management controller may be a power management integrated circuit system (PMIC).

[0047] The signal from the clock control component 370 can be input to the delay line 336. The delay line 336 can include a number of buffers, inverters and / or other units. Figure 3A The example is shown as three buffers, however, the example is not limited thereto. The delay line 336 can be fixed or configurable. For example, a portion of the clock tree can be a delay line. A configurable or trimmable delay line can be used in conjunction with, for example, Figure 1-2B Temperature sensors such as temperature sensors 118 and 218 in the example and Figure 1-2B Design units 122 and 222 provide better temperature compensation when paired.

[0048] An example system 331-1, which may be referred to as a device in the alternative, includes multiple flip-flops 333-1, 333-2, 333-3, 333-4, 359, which are referred to as "latches" 333-1, 333-2, 333-3, 333-4, 359 in the alternative (which are generally referred to herein as "multiple flip-flops 333 or 359" or "multiple latches 333 or 359," respectively).

[0049] like Figure 3A As shown in FIG, a clock control component 370 (e.g., "AT SPEED CLOCK") is coupled to flip-flops 333-1, 333-2, 333-3, and 333-4 via a delay line 336. The clock control component can receive a clock signal from a circuit system external to the system 331-1. In some embodiments, the clock signal is asserted by the clock control component to enable clock gating logic. Generally speaking, the "flip-flops" referred to herein are edge-triggered flip-flops (e.g., flip-flops that are edge-triggered devices that respond to rising or falling edges of a timing signal) or level-sensitive flip-flops (e.g., flip-flops that are level-triggered devices that are transparent to a particular clock signal level and opaque to a different clock signal level). Although Figure 3AA plurality of flip-flops 333 are shown, but the example is not so limited. For example, the example system 331-1 can include and operate correctly with any sequential cell type latch, such as a flip-flop, a register, a register bank, a memory, and the like.

[0050] Each of the multiple flip-flops 333, 359 can be the same type of flip-flop. Having each of the multiple flip-flops 333, 359 be the same type of flip-flop can facilitate various aspects herein, such as allowing for accurate and easy determination of when margin is sufficient or insufficient. For example, each of the multiple flip-flops 333, 359 can be a data flip-flop, among other possibilities. Each of the multiple flip-flops 333, 359 can have an edge-triggered clock input (shown as a sideways triangle), a data "D" input gate, a "Q" output, and a Q-bar output, or both. As discussed herein, the first of the flip-flops 333-1 can be clocked by a delay line 336 at the clock input of the first flip-flop 333-1. In this case, via the "Q" or "Q-bar" output, flip-flop 333-1 can be the starting point of the critical timing path 329. Similarly, delay line 336 provides a clock to each of the flip-flops 333-2, 333-3, and 333-4. Furthermore, each of flip-flops 333-2, 333-3 in this case through each of the corresponding "Q" or "Q-bar" outputs is the starting point of critical timing path 329. Flip-flop 333-4 may be the endpoint of critical timing path 329 through the "D" input.

[0051] Sensor 338 includes at least one trigger, such as trigger 359. Trigger 359 is the portion of sensor 338 that senses the endpoint of critical timing path 329. In some embodiments, sensor 338 includes individual triggers, such as individual trigger 359, without any additional triggers. Figures 3A-3B . Including individual triggers in sensor 338 may result in a sensor with fewer components than would otherwise be possible using multiple triggers in the sensor, and / or may reduce the computational overhead associated with voltage-frequency regulation to operate the circuit with optimal margins. However, in some embodiments, sensor 338 may include additional components, such as multiple triggers.

[0052] The output from the clock control component 370 can be connected to the flip-flop 333-1 and, as mentioned, can also be connected to the delay line 336. The scan input ("SCAN IN") 368 can be the starting point or an intermediate point of the scan chain that is provided to the scan input ("si") of the first flip-flop (FF1) and then propagated to the corresponding scan inputs of the other flip-flops 333-2, 333-3, 333-4, and 359. The scan output ("SCAN OUT") can be the Q output and / or the Q bar output of the flip-flop 359 in the sensor 338 and / or can be located at another position along the scan chain.

[0053] Although Figure 3A and Figure 3B 3. In the figure, each flip-flop (e.g., flip-flop 333 and flip-flop 359) is shown on the same scan chain. However, the present disclosure is not limited thereto. In fact, in some embodiments, flip-flop 333 and flip-flop 359 can be separate and different chains.

[0054] Scan output 367 can be an input to a scan controller or ATE, as described herein, which is used to determine various suitable voltage-frequency operating combinations that provide sufficient margin. For example, the scan output can permit a determination of whether a first data value (e.g., a data value associated with the circuitry of the SoC) and a second data value are the same or different data values. Thus, a baseline voltage (e.g., a minimum voltage) and / or a threshold frequency (e.g., a maximum clocking frequency) can be determined for a given operating condition, such as an operating temperature, and the SoC can then be configured to operate at a voltage-frequency operating combination that produces sufficient timing margin and, in turn, reduces the operating voltage employed by the SoC and / or maximizes the clocking frequency employed by the SoC to improve SoC performance (e.g., reduce power consumption and / or reduce computational overhead).

[0055] Figure 3B An example system 331-2 is shown for use with a sensor 338 in accordance with some embodiments of the present disclosure. Example system 331-2 is similar to system 331-1, but employs a sensor 338 set to a positive data offset, where the sensor samples data under more stringent conditions (e.g., with a shorter time interval between samples) than a functionally critical endpoint, which is represented by a trigger 333-4. Thus, unlike Figure 3A, a delay line 386 may be present before the scan input "Si" of the sensor 338. The signal from the sensor 338 may be used by the ATE and / or the scan controller, as described herein. For example, the signal from the sensor 338 may be used to determine a baseline voltage (e.g., a minimum voltage), and / or a threshold frequency (e.g., a maximum clocking frequency) may be determined for a given operating condition, such as an operating temperature, and the SoC may then be configured (e.g., based on stored values ​​in a data structure, such as a table) to operate at a voltage-frequency operating combination that produces sufficient timing margin and, in turn, reduces the operating voltage employed by the SoC and / or maximizes the clocking frequency employed by the SoC to improve SoC performance, as described herein.

[0056] Figure 4 An example method 409 is shown according to some embodiments of the present disclosure. Method 409 may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all operations are required in every embodiment. Other process flows are possible.

[0057] At 490, method 409 may include executing a circuit system (eg, a flip-flop, such as a flip-flop) on a system on a chip (SoC). Figure 3A and Figure 3B At 492, the method may include executing a first sensing operation associated with a sensor (e.g., a flip-flop 333-4 "FF4") of the SoC (e.g., which may be located along a scan chain) of the SoC. Figure 3A and Figure 3B In some embodiments, the second sensing operation is associated with a sensor configured to receive a second data value associated with the circuitry of the sensor, as described herein. As mentioned, the second sensing operation can be performed earlier than the first sensing operation. For example, the second sensing operation can be associated with a sensor configured to receive an earlier clock than the first sensing operation. However, in some embodiments, the second sensing operation is associated with a sensor configured to receive a later data value than the first sensing operation.

[0058] In digital logic circuits, a sensing operation refers to a circuit component detecting and responding to a specific digital signal on a line or a specific voltage level on a logic gate input. Sensing can be performed by circuit systems including registers, flip-flops, latches, and other types of components. Sensing operations can be used in digital circuits to control the behavior of the circuit, allowing the circuit to perform specific tasks, such as decision making, memory storage, and state control. In general, sensing operations are an important part of digital logic circuits, allowing circuit components to detect and respond to specific signals, thereby enabling the desired task to be performed. Therefore, in some examples described herein, at least one of the multiple sensing operations (e.g., the second sensing operation) is associated with a sensor that is set to have an earlier clock arrival relative to at least one other of the multiple sensing operations. In some examples, at least one of the multiple sensing operations (e.g., the second sensing operation) is associated with a sensor that is set to have a later data arrival relative to at least one other of the multiple sensing operations. In some examples, the multiple sensing operations can determine a specific data value stored in a location of a data storage element, such as a flip-flop or latch in a system-on-chip (SoC).

[0059] At 494 , method 409 may include, in response to the first data value and the second data value being the same data value, determining that a clock margin of the SoC is sufficient, that is, the SoC may provide a voltage-frequency combination operation with sufficient margin.

[0060] Conversely, at 496, method 409 may include determining that the SoC has insufficient clock margin in response to the first data value and the second data value being different data values. In other words, the SoC may operate with an insufficient voltage-frequency combination of operating margin (e.g., which may result in data corruption or data loss, etc.).

[0061] Method 409 may include storing at least one voltage-frequency operating combination that provides sufficient margin under corresponding operating conditions, such as a particular operating temperature. In some embodiments, method 409 may include storing only voltage-frequency operating combinations that provide sufficient margin (e.g., without storing any voltage-frequency operating combinations associated with corresponding temperatures that provide insufficient margin). However, in some embodiments, voltage-frequency operating combinations that provide sufficient margin and voltage-frequency operating combinations that provide insufficient margin may be stored in a data structure (e.g., a lookup table, etc.) along with a corresponding indication of whether the margin is sufficient or insufficient. In any case, the SoC may be configured (e.g., based on a given operating condition, such as a particular operating temperature) for a particular voltage-frequency operating combination that provides sufficient margin, as described herein.

[0062] Method 409 may include adjusting the voltage and / or clocking frequency of the SoC in response to the first data value and the second data value being the same data value. For example, the voltage may be reduced or the clocking frequency may be increased until additional sampling of data values ​​of the sensor and the corresponding circuitry of the SoC at the reduced voltage and / or increased clocking frequency produces different sampled data values. Thus, the methods herein may facilitate determining a base operating voltage (e.g., a minimum voltage) for the SoC at a given temperature and / or a threshold operating frequency (e.g., a maximum clocking frequency) for the SoC at a given temperature or temperature range. Thus, the approaches herein may permit operation of the SoC at a reduced voltage and / or a higher (faster) clocking frequency, thereby improving the operation of the SoC, while also ensuring that the SoC operates with sufficient timing margins (e.g., to mitigate or avoid any data corruption or loss) at a given temperature or temperature range.

[0063] For example, a first sensing operation may be associated with a trigger of the SoC, and a second sensing operation may be associated with a trigger of the sensor. In some embodiments, the first sensing operation may occur during a first time window, and the second sensing operation may occur during a second time window. The first time window may be the same as or different from the second time window (e.g., the first time window may be offset from the second time window by a specific amount of clock or data timing). For example, the first time window and the second time window may be the same (e.g., start and stop at the same time), but as described herein, the data values ​​associated with the first sensing operation and the second sensing operation sensed simultaneously may be the same (e.g., indicating that the margin is sufficient) or may be different (e.g., indicating that the margin is insufficient).

[0064] The data value sensed during the first sensing operation can be compared to the data value sensed during the second sensing operation. In response to the comparison, the voltage and / or clocking frequency of at least one operation of the SoC can be adjusted to thereby adjust the timing margin of the SoC or take another remedial action to ensure sufficient timing margin. Examples of remedial actions include adjusting the voltage associated with at least one operation of the SoC, adjusting the frequency of at least one operation of the SoC, logging or otherwise storing a record of the occurrence of insufficient clock margin, among other possibilities. For example, the voltage and / or frequency of at least one operation of the SoC can be adjusted to minimize power consumption (e.g., by reducing the operating voltage of the SoC) and / or reduce latency (e.g., by increasing the operating frequency of the SoC) while still ensuring sufficient timing margin. Thus, the timing margin can be adjusted so that the setup time and / or hold time are adjusted so that the sampled data value is accurate or correct and the setup time and / or hold time are sufficient. For example, in some embodiments, the sampled data values ​​of a fourth trigger in the SoC and a trigger in the sensor can be used to determine whether the margin is sufficient, as described herein. For example, the SoC can be configured to operate with a specific voltage-frequency operating combination that ensures sufficient margin, for example, depending on the operating temperature. For example, the voltage may be gradually reduced and / or the frequency may be gradually increased until the sensor described herein detects insufficient margin (e.g., a setup violation corresponding to an incorrect (different) data value sampled at sensor FF 359). That is, because FF 359 is configured with earlier timing and / or later data arrival time, the FF may have a different data value (e.g., compared to FF 333-4), thereby permitting determination of the SoC's base operating voltage (minimum voltage) and / or the SoC's threshold operating frequency (maximum frequency), which still results in sufficient timing margin for operation of the SoC. When operating with sufficient margin, the data values ​​at FF 359 and FF 333-4 are the same due to the presence of sufficient margin for both FF 359 and FF 333-4. In other words, when operating with sufficient margin, there is no setup violation at both FF 359 and FF 333-4.

[0065] Table 1:

[0066]

[0067] Thus, embodiments herein generate at least one voltage-frequency operating combination stored in a data structure and generate sufficient margin for a given operating condition, such as a given operating temperature. For example, as shown in Table 1, multiple voltage-frequency operating combinations (e.g., with different corresponding frequencies and / or voltages) can be determined as described herein and stored in a data structure. For example, voltage-frequency operating combinations associated with at least one operation of a SoC can be stored in a data structure, such as the data structure represented by Table 1.

[0068] Multiple voltage-frequency operating combinations are stored and the SoC is permitted to operate at the multiple voltage-frequency operating combinations for a given temperature. For example, a stored voltage-frequency operating combination that provides sufficient clock margin for the SoC may be selected based on specific operating conditions, such as a given operating temperature of the SoC corresponding to the stored voltage-frequency operating combination.

[0069] Thus, such an approach can allow for additional flexibility in how the SoC is configured to operate under given operating conditions, such as a given operating temperature (e.g., 25°C, 50°C, etc.), and thereby further improve the operation of the SoC depending on, for example, the computational load, data type, and / or specific application associated with the SoC's operation. Thus, the approaches herein can readily determine the SoC's base operating voltage (minimum voltage) and / or the SoC's threshold operating frequency (maximum frequency), while still providing sufficient timing margin for the SoC's operation. In some embodiments, the SoC's base operating voltage is substantially equal to the last voltage at which the data values ​​for the first and second sensing operations are the same. In some embodiments, the SoC's threshold operating frequency is substantially equal to the highest frequency at which the data values ​​for the sensing operations associated with the SoC's trigger and the sensor's trigger are the same. As used herein, the term "substantially" means that a characteristic need not be absolute, but rather sufficiently close to achieve the benefits of the characteristic. For example, "substantially equal" is not limited to absolute values, but can include similar values, such as those within 10%, 5%, or 1% of a given value. Thus, the approaches herein may permit operation of the SoC at a reduced voltage, such as a base operating voltage, and / or a higher (faster) clocking frequency, such as a threshold operating frequency, and thereby improve the operation of the SoC, while also ensuring that the SoC operates with sufficient timing margin (e.g., to mitigate or avoid any data corruption or loss).

[0070] Although Table 1 shows a total of three different voltage-frequency operating combinations for a given temperature, the present disclosure is not limited thereto and may include additional or fewer voltage-frequency operating combinations for a given temperature. Although Table 1 shows different voltage-frequency operating combinations associated with individual temperature values ​​(e.g., 25° C.), the present disclosure is not limited thereto and may include additional temperature values ​​and / or temperature ranges associated with different voltage-frequency operating combinations.

[0071] Some portions of the previous detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the data processing arts can most effectively convey the substance of their work to others skilled in the art. An algorithm is herein and generally conceived to be a self-consistent sequence of operations that produces a desired result. Operations are those requiring physical manipulation of physical quantities. These quantities are typically, but not necessarily, in the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. Primarily for reasons of common usage, it has proven convenient at times to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0072] It should be borne in mind, however, that all of these and similar terms should be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may relate to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0073] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any other type of medium suitable for storing electronic instructions, each of which is connected to a computer system bus.

[0074] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform processes according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, or the like.

[0075] In the foregoing description, embodiments of the present disclosure have been described with reference to specific exemplary embodiments thereof. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the description and drawings are to be regarded as illustrative rather than restrictive.

[0076] Some portions of the previous detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the data processing arts can most effectively convey the substance of their work to others skilled in the art. An algorithm is herein and generally conceived to be a self-consistent sequence of operations that produces a desired result. Operations are those requiring physical manipulation of physical quantities. These quantities are typically, but not necessarily, in the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. Primarily for reasons of common usage, it has proven convenient at times to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0077] It should be borne in mind, however, that all of these and similar terms should be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may relate to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0078] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk (including solid-state drives (SSDs), hard disk drives (HDDs), floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROMs), random-access memory (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0079] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems may be used with the programs according to the teachings herein, or it may prove convenient to construct more specialized equipment to perform the methods. Structures for various such systems will be presented as set forth in the description below. Additionally, embodiments of the present disclosure are not described with reference to any particular programming language. It will be appreciated that a variety of programming languages ​​may be used to implement the teachings of the present disclosure as described herein.

[0080] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine-readable (e.g., computer-readable) storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory device, or the like.

[0081] In the foregoing description, embodiments of the present disclosure have been described with reference to specific exemplary embodiments thereof. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the description and drawings are to be regarded as illustrative rather than restrictive.

Claims

1. A method (409) for dynamic voltage frequency regulation, comprising: performing a first sensing operation associated with a circuit system (234) on a system on a chip (SoC) (110, 210) to determine a first data value associated with the circuit system (234) of the SoC (110, 210); performing a second sensing operation associated with the circuitry (234) of the sensor (338) to determine a second data value associated with the circuitry (234) of the sensor (338); In response to the first data value and the second data value being the same data value, determining that a clock margin of the SoC (110, 210) is sufficient; as well as In response to the first data value and the second data value being different data values, it is determined that the clock margin of the SoC (110, 210) is insufficient. 2 . The method of claim 1 , further comprising storing a voltage-frequency operation combination associated with at least one operation of the SoC during the first sensing operation, the second sensing operation, or both in a data structure.

3. The method of claim 1 , further comprising configuring the SoC to operate with a stored voltage-frequency operating combination that provides sufficient clock margin for the SoC, wherein the stored voltage-frequency operating combination that provides sufficient clock margin for the SoC is selected based on a specific operating condition of the SoC corresponding to the stored voltage-frequency operating combination.

4. The method of any one of claims 1 to 3, wherein the second sensing operation is associated with a sensor that is set to an earlier clock arrival relative to the first sensing operation, wherein the earlier clock arrival is imparted by a delay line coupled to the circuitry of the SoC.

5. The method of any one of claims 1 to 3, wherein the second sensing operation is associated with a sensor that is configured for later data arrival relative to the first sensing operation, wherein the later data arrival is imparted by a delay line of the circuitry coupled to at least the sensor.

6. A device for dynamic voltage frequency regulation, comprising: A controller (112, 212) configured to: A first sensing operation associated with a circuit system (333-1, 333-2, 333-3, 333-4) on a system on a chip SoC (110, 210) is performed to determine the circuit system (333-1, 333-2, 333-3, 333-4) associated with the SoC (110, 210). 333-2, 333-3, 333-4) associated with a first data value; performing a second sensing operation associated with the circuitry (359) of the sensor (338) to determine a second data value associated with the circuitry (359) of the sensor (338); In response to the first data value and the second data value being the same data value, determining that a clock margin of the SoC (110, 210) is sufficient; In response to the first data value and the second data value being different data values, determining that the clock margin of the SoC (110, 210) is insufficient; as well as A voltage-frequency operation combination associated with at least one operation of the SoC (110, 210) is stored in a data structure.

7. The apparatus of claim 6, wherein: The circuit system in the SoC is a first trigger; and The circuitry in the sensor is a second trigger, wherein the circuitry in the sensor includes individual triggers.

8. The apparatus of claim 7, wherein the sensor comprises the individual trigger in the absence of additional triggers.

9. The apparatus of claim 7, further comprising a delay line, wherein the delay line is coupled to the circuitry or individual flip-flops in the SoC.

10. The apparatus of claim 7, wherein the controller is configured to: gradually reducing a voltage associated with the SoC until the first sensing operation and the second sensing operation have different data values ​​to determine a base operating voltage of the SoC; or A voltage associated with the SoC is gradually increased until the first sensing operation and the second sensing operation have the same data value to determine the basic operating voltage of the SoC. 11 . The apparatus of claim 10 , wherein the basic operating voltage of the SoC is substantially equal to a final voltage at which the data values ​​of the first sensing operation and the second sensing operation are the same value.

12. The apparatus of claim 7 , wherein the controller is configured to gradually increase a frequency associated with the SoC until the first sensing operation and the second sensing operation have different data values ​​to determine a threshold operating frequency of the SoC, wherein the threshold operating frequency of the SoC is substantially equal to a last voltage at which the data values ​​of the first sensing operation and the second sensing operation are the same value.

13. A device for dynamic voltage frequency regulation, comprising: Voltage control components (130, 230); Clock control component (128, 228); as well as A controller (112, 212) coupled to the voltage control component (130, 230) and the clock control component (128, 228), wherein the controller (112, 212) is configured to: A first sensing operation associated with a trigger (333-1, 333-2, 333-3, 333-4) on a system on a chip SoC (110, 210) is performed to determine a first sensing operation associated with the trigger (333-1, 333-2, 333-3, 333-4) of the SoC (110, 210). 333-2, 333-3, 333-4) associated with a first data value; performing a second sensing operation associated with an individual trigger (359) of a sensor of the SoC (110, 210) to determine a second data value associated with the individual trigger (359) of the sensor (338); In response to the first data value and the second data value being the same data value: gradually changing a voltage, a timing frequency, or both associated with at least one operation of the SoC (110, 210); Additional sensing operations are performed to determine: a subsequent data value associated with the flip-flop (333-1, 333-2, 333-3, 333-4) on the SoC (110, 210); and a subsequent data value associated with the individual trigger (359) of the sensor (338); storing at least one voltage-frequency operation combination of the SoC (110, 210) associated with the first data value, the second data value, and the subsequent data value in a data structure; as well as The SoC (110, 210) is configured to operate at one of the stored voltage-frequency operating combinations that provides sufficient margin.

14. The apparatus of claim 13 , wherein the controller is configured to gradually reduce a voltage associated with the SoC until the first sensing operation and the second sensing operation have different data values ​​to determine a basic operating voltage of the SoC, wherein the basic operating voltage of the SoC is substantially equal to a minimum voltage at which the data values ​​of the sensing operations associated with the trigger of the SoC and the trigger of the sensor are the same data value.

15. An apparatus according to claim 13 or claim 14, wherein the controller is configured to gradually increase a frequency associated with at least one operation of the SoC to determine a threshold operating frequency of the SoC, wherein the threshold operating frequency of the SoC is substantially equal to a maximum voltage at which the data value of the sensing operation associated with the trigger of the SoC and the trigger of the sensor is the same data value.

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