Method for process mapping of multiplexer logic, electronic device and medium

Abstract

The present application relates to the technical field of integrated circuits, and particularly relates to a process mapping method of a multiplexer logic, an electronic device and a medium, comprising A1, decomposing a to-be-mapped multiplexer to generate a multiplexer tree; A2, obtaining all possible process mapping structures of each leaf node of an Lth level, and setting l=L-1; A3, obtaining all possible process mapping structures of each node of an lth level, and obtaining an optimal combination structure of each node of the lth level and a corresponding child node group; A4, if l is equal to 1, selecting an optimal target combination structure from the optimal combination structure corresponding to each possible process mapping structure of the node of the current lth level, determining a target process mapping structure of each node based on the optimal target combination structure, if l is greater than 1, setting l=l-1, and returning to step A3. The present application can select a reasonable process mapping mode, and minimize the area and delay of the FPGA as much as possible.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more particularly to a process mapping method for multiplexer logic, electronic devices, and media. Background Technology

[0002] Multiplexers (Muxes) are common components in digital systems, but they have high logic resource overhead. Field-programmable gate arrays (FPGAs) provide various dedicated modules on-chip to bridge the performance gap with application-specific integrated circuits (ASICs), such as dedicated multiplexers integrated with look-up tables (LUTs). Properly mapping multiplexers onto FPGAs can help reduce overall area and latency. However, FPGAs have diverse resources, and some multiplexer structures are bulky. Therefore, various process mapping methods exist for mapping multiplexers onto FPGAs. Thus, choosing a reasonable process mapping method to minimize the overall FPGA area and latency is a pressing technical problem. Summary of the Invention

[0003] The purpose of this invention is to provide a process mapping method, electronic device and medium for multiplexer logic, which can select a reasonable process mapping method to minimize the overall area and latency of the FPGA.

[0004] According to a first aspect of the present invention, a process mapping method for multiplexer logic is provided, comprising:

[0005] Step A1: Decompose the multiplexer to be mapped into a multiplexer tree. Each node of the multiplexer tree corresponds to a multiplexer. The multiplexer tree includes L levels.

[0006] Step A2: Obtain all possible process mapping structures for each leaf node of the Lth level, set l = L-1, and execute step A3. The process mapping structure is the implementation structure of the multiplexer corresponding to the node on the FPGA.

[0007] Step A3: Obtain all possible process mapping structures for each node in the l-th level, and based on all possible process mapping structures of the child nodes corresponding to each node in the l-th level, obtain the optimal combination structure of each node in the l-th level and its corresponding child nodes, and record the structure of the child nodes on which the optimal combination structure corresponding to each possible process mapping structure of each node in the l-th level depends.

[0008] Step A4: Determine if l equals 1. If l equals 1, select the optimal target combination structure from the optimal combination structure corresponding to each possible process mapping structure of the current l-th level node, determine the target process mapping structure of each node based on the optimal target combination structure, and end the process. If l is greater than 1, set l = l - 1 and return to step A3.

[0009] According to a second aspect of the present invention, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the method described in the first aspect of the present invention.

[0010] According to a third aspect of the present invention, a computer-readable storage medium is provided, storing computer-executable instructions for performing the method described in the first aspect of the present invention.

[0011] Compared with existing technologies, this invention has significant advantages and beneficial effects. Through the above technical solution, the process mapping method, electronic device, and medium for multiplexer logic provided by this invention achieve considerable technological advancement and practicality, and have broad industrial application value. It has at least the following beneficial effects:

[0012] This invention first decomposes the multiplexer into a multiplexer tree, then obtains the process mapping structure of each leaf node from bottom to top, as well as the optimal combination of each process mapping structure of each non-leaf node with its child nodes. Finally, it selects the optimal target combination structure from the optimal combination of each process mapping structure of the root node, which can select a reasonable process mapping method and minimize the overall area and latency of the FPGA. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 A flowchart illustrating the process mapping method for multiplexer logic provided in an embodiment of the present invention. Detailed Implementation

[0015] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0016] This invention provides a process mapping method for multiplexer logic, such as... Figure 1 As shown, it includes:

[0017] Step A1: Decompose the multiplexer to be mapped into a multiplexer tree. Each node of the multiplexer tree corresponds to a multiplexer. The multiplexer tree includes L levels.

[0018] It should be noted that, due to limitations in hardware resources on the FPGA, many large-scale multiplexers are difficult to map directly onto the FPGA. A better approach is to first decompose the multiplexers to be mapped into a multiplexer tree, where each node corresponds to a smaller multiplexer, facilitating mapping on the FPGA. Furthermore, the multiplexers can be optimized during the decomposition process.

[0019] Step A2: Obtain all possible process mapping structures for each leaf node of the Lth level, set l = L-1, and execute step A3. The process mapping structure is the implementation structure of the multiplexer corresponding to the node on the FPGA.

[0020] Each leaf node corresponds to a multiplexer, which may have one or more process mapping structures on the FPGA. This invention needs to retain all possible process mapping structures for each leaf node for use in subsequent selection of combination structures. All possible process mapping structures are structures that satisfy hardware setting constraints.

[0021] Step A3: Obtain all possible process mapping structures for each node in the l-th level, and based on all possible process mapping structures of the child nodes corresponding to each node in the l-th level, obtain the optimal combination structure of each node in the l-th level and its corresponding child nodes, and record the structure of the child nodes on which the optimal combination structure corresponding to each possible process mapping structure of each node in the l-th level depends.

[0022] It should be noted that in step A3, each node in the l-th level may be a root node or a non-leaf node that is not a root node. This embodiment of the invention adopts a bottom-up approach, acquiring all possible process mapping structures of the multiplexer corresponding to each node layer by layer, and obtaining the optimal combination of each non-leaf node with its corresponding child node in each process mapping structure, facilitating the subsequent selection of the final optimal target combination structure.

[0023] Step A4: Determine if l equals 1. If l equals 1, select the optimal target combination structure from the optimal combination structure corresponding to each possible process mapping structure of the current l-th level node, determine the target process mapping structure of each node based on the optimal target combination structure, and end the process. If l is greater than 1, set l = l - 1 and return to step A3.

[0024] It is understandable that when l=1, it means that the root node has been traversed. At this time, the optimal target combination structure is selected from the optimal combination structure corresponding to each possible process mapping structure of the root node. It is understandable that the optimal combination structure corresponding to each process mapping structure of each node at each level records the structure of the corresponding child node. Therefore, the target process mapping structure of each node can be directly determined based on the optimal target combination structure.

[0025] As one embodiment, the FPGA includes multiple Configurable Logic Blocks (CLBs). Each CLB's hardware resources include eight Look-Up Tables (LUTs), four multiplexers F7, two multiplexers F8, and one multiplexer F9. The maximum number of inputs for each look-up table is six. It should be noted that multiplexers F7, F8, and F9 are dedicated modules within the FPGA; their specific structures will not be detailed here. A single CLB can directly implement a 1-to-1 selector, a 2-to-1 selector, a 4-to-1 selector, an 8-to-1 selector, a 16-to-1 selector, and a 32-to-1 selector. Specifically, a 1-to-1 selector can be implemented using a single 1-input look-up table. A 2-to-1 selector can be implemented using a single 3-input look-up table. A 4-to-1 selector can be implemented using a single 6-input look-up table. An 8-to-1 selector can be implemented using two 6-input look-up tables and one multiplexer F7. A 16-to-1 selector can be implemented using four 6-input lookup tables, two multiplexers F7, and one multiplexer F8. A 32-to-1 selector can be implemented using eight 6-input lookup tables, four multiplexers F7, two multiplexers F8, and one multiplexer F9.

[0026] As one embodiment, the multiplexer tree satisfies the following: each non-leaf node corresponds to a 2-to-1 multiplexer, the input of the 2-to-1 multiplexer corresponding to a non-leaf node is the output of the multiplexers corresponding to the two child nodes of the non-leaf node, and all leaf nodes are of the first type, second type, or third type. The first type of leaf nodes are buffer leaf nodes, where the input and output of the multiplexer corresponding to a buffer leaf node are identical. The second type of leaf nodes are regular leaf nodes, where the multiplexer corresponding to a regular leaf node does not have any pair of optimizable data, nor does it have any indeterminate (Don't Care) states, i.e., there is no optimization space, and therefore no need to further decompose the regular leaf nodes. The third type of leaf nodes are constant leaf nodes, where all inputs of the multiplexer corresponding to a constant leaf node are constant. It should be noted that there is optimization space when constant, indeterminate, and identical input signals exist. It should also be noted that during the process of decomposing the multiplexer to be mapped into the above multiplexer tree, optimizations have been performed on identical data signals, constant signals, and indeterminate signals to simplify the logic of the multiplexer as much as possible.

[0027] Specifically, step A1 includes:

[0028] Step A11: Obtain the set of selection signals {S1, S2, ..., S} corresponding to the multiplexer to be mapped. n ,…,S N}, S n This is the nth selection signal, where n ranges from 1 to N, and N is the total number of selection signals.

[0029] Step A12: Traverse each S n If S n For the selection signal that requires direct connection to ground or direct connection to power, then S... n Connect directly to ground or directly to the power supply, and connect S n Remove from the selected signal set, update N = N-1, and execute step A13 after traversal is complete.

[0030] Step A13: Obtain the data signal set {D1, D2, ..., D} corresponding to the multiplexer to be mapped. m ,…,D M}, D m Let m be the m-th data signal, where m ranges from 1 to M, and M is the number of data signals, M = 2. N .

[0031] Step A14, if all D m All are driven by constants, or all data signals are indeterminate signals, or all D... mIf all signals are connected to the same signal source, the logic optimization process ends; otherwise, proceed to step A15.

[0032] Step A15: Decompose the multiplexer to be mapped into a multiplexer tree.

[0033] Step A16: Generate an optimized multiplexer based on the multiplexer tree.

[0034] As one embodiment, step A15 includes:

[0035] Step A151: Set the multiplexer to be mapped as the multiplexer to be decomposed, where the number of data signals X = M. Then, set {D1, D2, ..., D...} m ,…,D M Set it as the currently selected signal set and execute step A152.

[0036] Step A152: Select a decomposed selection signal S from the current selection signal set. k , will S k Remove from the current set of selected signals, where k ranges from 1 to N.

[0037] Step A153: Decompose the multiplexer to be mapped into two X / 2 selectors P1 k and P2 k P1 k and P2 k Share the selection signal in the current selection signal set, P1 k The data signal is the S of the multiplexer to be mapped. k The selected data signal when it is 0, P2 k The data signal is the S of the multiplexer to be mapped. k The selected data signal when it is 1.

[0038] Step A154, if P1 k and P2 k If one of the X / 2 selector inputs is an indeterminate signal, then return to the other X / 2 selector; otherwise, return to both X / 2 selectors.

[0039] Step A155: Determine whether the returned X / 2 selector is a leaf node. If all of them are leaf nodes, generate a multiplexer tree. Otherwise, set each X / 2 selector as a multiplexer to be decomposed, update X = X / 2, and return to step A152.

[0040] In the process of decomposing the multiplexer to be optimized into a multiplexer tree, only signals assigned to the same multiplexer that meet the optimization conditions, i.e., a pair of data that are the same signal, are both constants, or are both indeterminate states, can create optimization space. Therefore, in this process, how to select the decomposition selection signal to obtain as much optimization space as possible is particularly important. As an embodiment, step A152 includes:

[0041] Step A1521: Obtain S-based k Decompose P1 k The data signal set is {Q1} k Q2 k ,…,Q i k ,…,Q X / 2 k}, P2 k The data signal set is {R1} k R2 k ,…,R i k ,…,R X / 2 k}, where Q i k For P1 k The i-th data signal in the set of data signals, R i k For P2 k The i-th data signal in the set of data signals, where i ranges from 1 to X / 2, Q i k and R i k The corresponding selection signals are the same.

[0042] Step A1522, Traverse {Q1} k Q2 k ,…,Q i k ,…,Q X / 2 k} and {R1 k R2 k ,…,R i k ,…,R X / 2 k If Q i k and R i k Satisfying Q i k =R i k Or Q i k Ri k All are indeterminate or Q-states i k R i k If all are constants, then (Q) i k ,R i k The data pair was identified as optimizable, and {Q1} was obtained. k Q2 k ,…,Q i k ,…,Q X / 2 k} and {R1 k R2 k ,…,R i k ,…,R X / 2 k} can optimize data pairs (Q) i k ,R i k ) quantity E k .

[0043] Step A1523, E k The smallest k value corresponds to S k Determined as the decomposition selection signal S k .

[0044] Among them, E k The smaller the value, the more it indicates that it is based on S. k The smaller the optimization space destroyed by decomposition.

[0045] As one embodiment, in step A1523, if E k If there are multiple minimum k values, then for E... k The smallest value {Q1 k Q2 k ,…,Q i k ,…,Q X / 2 k} and {R1 k R2 k ,…,R i k ,…,R X / 2 k}implement:

[0046] Step A15231, Traverse {Q1 k Q2 k ,…,Q i k ,…,Q X / 2k If Q i k Q j k Satisfying Q i k =Q j k Or Q i k Q j k All are indeterminate or Q-states i k R i k If all are constants, then (Q) i k Q j k ) was identified as an optimizable data pair, where Q j k For {Q1 k Q2 k ,…,Q i k ,…,Q X / 2 k The j-th data signal in}.

[0047] Traverse {R1 k R2 k ,…,R i k ,…,R X / 2 k If R i k R j k Satisfy R i k =R j k Or R i k R j k All are indeterminate or R i k R i k If all are constants, then (R) i k ,R j k The data pair was identified as optimizable, where R... j k For {R1 k R2 k ,…,R i k ,…,R X / 2 kThe j-th data signal in}.

[0048] The value of j ranges from 1 to X / 2, and i ≠ j.

[0049] Step A15232, obtain {Q1} k Q2 k ,…,Q i k ,…,Q X / 2 k Optimizable data pairs in QE k , and {R1 k R2 k ,…,R i k ,…,R X / 2 k The number of optimizable data pairs RE in} k .

[0050] Step A15233: Obtain QE for each group k and RE k The absolute value of the difference, QE k and RE k The S corresponding to the k value with the largest absolute value of the difference k Determined as the decomposition selection signal S k .

[0051] Among them, QE k and RE k The larger the absolute value of the difference, the larger the optimization space of the multiplexer obtained after decomposition, while destroying the same optimization space.

[0052] If in step A15233, QE k and RE k If there are multiple k values ​​with the largest absolute value of the difference, then QE k and RE k The largest or smallest absolute value of the difference among k is S, which has the largest k value. k Determined as the decomposition selection signal S k .

[0053] As one embodiment, step A2 includes:

[0054] Step A21: If the leaf node is a first-class leaf node, then set the process mapping structure of the leaf node to a net or a lookup table with 1 input.

[0055] Step A22: If the leaf node is a second type of leaf node, determine whether the number of selection signals F of the multiplexer corresponding to the leaf node is less than or equal to 5. If so, directly generate the process mapping structure of the leaf node based on a programmable logic block. Otherwise, proceed to step A23.

[0056] Step A23: Decompose F into F = 5 × g + b, where g is the number of layers in the 32-to-1 selector, b is the number of selection signals in the last layer selector, and b is less than 5. Map the leaf node to a layer of g 32-to-1 selectors connected to a layer of 2 b Selectors for option 1 are arranged in a pyramid structure, and selectors for option 2 are arranged in a pyramid structure. b Each input of a 1-to-1 selector corresponds to the output of a 32-to-1 selector. Each 32-to-1 selector, 2 b A selector that selects 1 corresponds to a programmable logic block.

[0057] Step A24: If the leaf node is a third type of leaf node, determine whether the number of selection signals F of the multiplexer corresponding to the leaf node is less than or equal to 6. If so, directly map it to the lookup table of F input; otherwise, proceed to step A25.

[0058] Step A25: Set H = F - 4, making the multiplexer corresponding to the leaf node equivalent to 2. H Selector 1, select 2 H The structure of the selector for option 1 is determined by the mapping structure corresponding to the leaf node.

[0059] It should be noted that for a regular leaf node, i.e., a second-type leaf node, if implemented using a tree structure, the bottom layer is entirely set to a 6-input lookup table. When implementing a constant leaf node, i.e., a third-type leaf node, if F≤6, a 6-input lookup table can be directly used. However, when F>6, a 6-input lookup table is insufficient, so a similar approach to that of a regular leaf node can be used, also a tree structure. When used on regular nodes, the 6-input lookup table at the bottom implements 2... 2 Option 1, when used on a constant leaf node, the lookup table with 6 inputs at the bottom implements option 2. 6 Option 1: If the regular leaf node and the constant leaf node have the same structure, then except for the bottom 6-input lookup table, the mapping structure of the other parts is the same. Therefore, the difference between the two lies in the bottom 6-input lookup table representing 2. 2 Choose 1 and 2 6 Choose 1, the difference between the two is 2. 4 Therefore, in step A25, setting H = F - 4 makes the multiplexer corresponding to the leaf node equivalent to 2. H A selector that selects 1.

[0060] As one embodiment, in step A23, if b≠0, then jump to step B23: decompose F into F=5×(g-1)+c+d, where g-1 is the number of levels of the 32-to-1 selector, d is the number of selection signals of the second-to-last selector, d is the number of selection signals from the last selector, c is less than 5, d is less than 5, and map the leaf node to a (g-1) level 32-to-1 selector connected to a level 2 c Selector 1, then connect to layer 2. d A selector that selects 1 from 2, and a 32-to-1 selector, and a 2-to-3 selector. c Selector for option 1, 2 d Each selector that selects option 1 corresponds to a programmable logic block, and then step A24 is executed. It should be noted that, compared with the structure that sets F = 5 × (g-1) + c + d, the mapping structure corresponding to F = 5 × g + b will allow the subsequent combinational structure to have more possible mapping schemes, making the mapping structure of the entire tree more balanced, and will not introduce additional delay.

[0061] Step A3 involves processing non-leaf nodes, which are all 2-to-1 selectors, with their input always coming from the output of another node. Due to hardware limitations, some mapping structures are dependent on the mapping structure of the input nodes. As one embodiment, step A3 involves obtaining all possible process mapping structures for each node in the l-th level, including:

[0062] Step A31: Set the process mapping structure of the l-th level node to a lookup table with 3 inputs. The lookup table structure has no requirements on the mapping structure of the input nodes.

[0063] Under the constraint that the last component of the mapping structure of the two input nodes corresponding to the l-th level node is a lookup table, the process mapping structure of this node is set as a multiplexer F7.

[0064] Under the constraint that the last component of the mapping structure of the two input nodes corresponding to the l-th level node is a multiplexer F7, the process mapping structure of this node is set to a multiplexer F8.

[0065] Under the constraint that the last component of the mapping structure of the two input nodes corresponding to the l-th level node is a multiplexer F8, the process mapping structure of this node is set to a multiplexer F9.

[0066] When the last component of the mapping structure of an input node corresponding to the l-th level node is a 2-to-1 selector, the node and the corresponding last component being a 2-to-1 selector are merged into a 5-input lookup table.

[0067] When the last component of the mapping structure of the two input nodes corresponding to the l-th level node is a 2-to-1 selector and the selection signals of the two 2-to-1 selectors are the same, the l-th level node and the two 2-to-1 selectors are merged into a 6-input lookup table.

[0068] As one embodiment, in steps A2 and A3, if the top of the mapping structure corresponding to the current node is a multiplexer F7, then the top multiplexer F7 can be replaced with a 3-input lookup table; if the top of the mapping structure corresponding to the current node is a multiplexer F8 or F9, then the top multiplexer F8 or F9 can be replaced with a 6-input lookup table. These replacement schemes provide more possibilities for subsequent combination structures and can reduce overall latency to a greater extent.

[0069] As one embodiment, in steps A3 and A4, when selecting the optimal combination structure from multiple candidate combination structures, the following steps are performed:

[0070] Step A10: Obtain the number of lookup tables on the critical path of each candidate combination structure. The number of lookup tables on the critical path is proportional to the latency.

[0071] Among them, the critical path is the path with the most lookup tables in the candidate combination structure.

[0072] Step A20: Determine if there is only one candidate combination structure with the smallest number of lookup tables for the critical path. If so, determine the candidate combination structure with the smallest number of lookup tables for the critical path as the optimal candidate combination structure. Otherwise, retain only the candidate combination structure with the smallest number of lookup tables and proceed to step A30.

[0073] Step A30: Obtain the total number of lookup tables for each candidate combination structure. The total number of lookup tables is proportional to the area.

[0074] Step A40: Determine if there is only one candidate combination structure with the smallest total number of lookup tables. If so, determine the candidate combination structure with the smallest total number of lookup tables as the optimal candidate combination structure. Otherwise, only retain the candidate combination structure with the smallest total number of lookup tables and proceed to step A50.

[0075] Step A50: Obtain the total number of dedicated multiplexers for each candidate combination structure. The dedicated multiplexers include multiplexers F7, F8 and F9. The total number of multiplexers is proportional to the area.

[0076] Step A60: Determine whether there is only one candidate combination structure with the smallest total number of multiplexers. If so, determine the candidate combination structure with the smallest total number of dedicated multiplexers as the optimal candidate combination structure. Otherwise, determine the candidate combination structure generated first or last among the candidate combination structures with the smallest total number of multiplexers as the optimal candidate combination structure.

[0077] It should be noted that in step A3, for each possible process mapping structure of each node in the l-th level, steps A10-A60 need to be executed to obtain the corresponding optimal combination structure. Specifically, the candidate combination structure is all possible combinations of each possible process mapping structure of each node with its corresponding child nodes. The optimal candidate combination structure is the optimal combination structure formed by combining each possible process mapping structure of each node in the l-th level with its corresponding child nodes. In step A4, the candidate combination structure is the optimal combination structure corresponding to all possible process mapping structures of the root node, and the optimal candidate combination structure is the optimal target combination structure.

[0078] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the steps as sequential processes, many of these steps can be performed in parallel, concurrently, or simultaneously. Furthermore, the order of the steps can be rearranged. A process can be terminated when its operation is complete, but it may also have additional steps not included in the figures. A process can correspond to a method, function, procedure, subroutine, subroutine, etc.

[0079] This invention also provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the method described in this invention.

[0080] This invention also provides a computer-readable storage medium storing computer-executable instructions for performing the methods described in this invention.

[0081] In this embodiment of the invention, the multiplexer is first decomposed into a multiplexer tree. Then, the process mapping structure of each leaf node is obtained from the bottom up, as well as the optimal combination of each process mapping structure of each non-leaf node with its child nodes. Finally, the optimal target combination structure is selected from the optimal combination of each process mapping structure of the root node. This allows for the selection of a reasonable process mapping method, minimizing the overall area and latency of the FPGA.

[0082] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A process mapping method for multiplexer logic, characterized in that, include: Step A1: Decompose the multiplexer to be mapped into a multiplexer tree. Each node of the multiplexer tree corresponds to a multiplexer. The multiplexer tree includes L levels. The multiplexer tree satisfies the following: each non-leaf node corresponds to a 2-to-1 multiplexer, the input of the 2-to-1 multiplexer corresponding to a non-leaf node is the output of the multiplexers corresponding to the two child nodes of the non-leaf node, all leaf nodes are of the first type, the second type, or the third type, wherein the input and output of the multiplexer corresponding to the first type of leaf node are the same, the multiplexer corresponding to the second type of leaf node has no optimization space, and the input of the multiplexer corresponding to the third type of leaf node is all constant; Step A2: Obtain all possible process mapping structures for each leaf node of the Lth level, set l=L-1, and execute step A3. The process mapping structure is the implementation structure of the multiplexer corresponding to the node on the FPGA. Step A3: Obtain all possible process mapping structures for each node in the l-th level, and based on all possible process mapping structures of the child nodes corresponding to each node in the l-th level, obtain the optimal combination structure of each node in the l-th level and its corresponding child nodes, and record the structure of the child nodes on which the optimal combination structure corresponding to each possible process mapping structure of each node in the l-th level depends. Step A4: Determine if l equals 1. If l equals 1, select the optimal target combination structure from the optimal combination structure corresponding to each possible process mapping structure of the current l-th level node, determine the target process mapping structure of each node based on the optimal target combination structure, and end the process. If l is greater than 1, set l = l - 1 and return to step A3.

2. The method according to claim 1, characterized in that, The FPGA includes multiple programmable logic blocks. The hardware resources of each programmable logic block include 8 lookup tables, 4 multiplexers F7, 2 multiplexers F8, and 1 multiplexer F9. The maximum number of inputs to the lookup tables is 6. A programmable logic block can directly implement a 1-to-1 selector, a 2-to-1 selector, a 4-to-1 selector, an 8-to-1 selector, a 16-to-1 selector, and a 32-to-1 selector.

3. The method according to claim 2, characterized in that, Step A2 includes: Step A21: If the leaf node is a first-type leaf node, then set the process mapping structure of the leaf node to a lookup table with a connection or 1 input. Step A22: If the leaf node is a second type of leaf node, determine whether the number of selection signals F of the multiplexer corresponding to the leaf node is less than or equal to 5. If so, directly generate the process mapping structure of the leaf node based on a programmable logic block. Otherwise, execute step A23. Step A23: Decompose F into F = 5 × g + b, where g is the number of layers in the 32-to-1 selector, b is the number of selection signals in the last layer selector, and b is less than 5. Map the leaf node to a layer of g 32-to-1 selectors connected to a layer of 2 b A selector that selects 1 from 2, and a 32-to-1 selector, and a 2-to- b A selector that selects 1 corresponds to a programmable logic block; Step A24: If the leaf node is a third type of leaf node, determine whether the number of selection signals F of the multiplexer corresponding to the leaf node is less than or equal to 6. If so, directly map it to the lookup table of F input; otherwise, execute step A25. Step A25: Set H=F-4, making the multiplexer corresponding to this leaf node equivalent to 2. H Selector 1, select 2 H The structure of the selector for option 1 is determined by the mapping structure corresponding to the leaf node.

4. The method according to claim 3, characterized in that, In step A23, if b≠0, then jump to step B23: decompose F into F=5×(g-1)+c+d, where g-1 is the number of levels of the 32-to-1 selector, c is the number of selection signals of the second-to-last level selector, and d is the number of selection signals of the last level selector. c is less than 5, and d is less than 5. Map the leaf node to a (g-1) level 32-to-1 selector connected to a level 2 c Selector 1, then connect to layer 2. d A selector that selects 1 from 2, and a 32-to-1 selector, and a 2-to-3 selector. c Selector for option 1, 2 d Each selector that selects option 1 corresponds to a programmable logic block, and then step A24 is executed.

5. The method according to claim 2, characterized in that, In step A3, all possible process mapping structures for each node at level l are obtained, including: Step A31: Set the process mapping structure of the l-th level node to a lookup table with 3 inputs; Under the constraint that the last component of the mapping structure of the two input nodes corresponding to the l-th level node is a lookup table, the process mapping structure of this node is set as a multiplexer F7. Under the constraint that the last component of the mapping structure of the two input nodes corresponding to the l-th level node is a multiplexer F7, the process mapping structure of this node is set to a multiplexer F8. Under the constraint that the last component of the mapping structure of the two input nodes corresponding to the l-th level node is a multiplexer F8, the process mapping structure of this node is set to a multiplexer F9. When the last component of the mapping structure of an input node corresponding to the l-th level node is a 2-to-1 selector, the node and the corresponding last component being a 2-to-1 selector are merged into a 5-input lookup table. When the last component of the mapping structure of the two input nodes corresponding to the l-th level node is a 2-to-1 selector and the selection signals of the two 2-to-1 selectors are the same, the l-th level node and the two 2-to-1 selectors are merged into a 6-input lookup table.

6. The method according to claim 3 or 5, characterized in that, In steps A2 and A3, if the top of the mapping structure corresponding to the current node is a multiplexer F7, then it is allowed to replace the top multiplexer F7 with a 3-input lookup table; if the top of the mapping structure corresponding to the current node is a multiplexer F8 or F9, then it is allowed to replace the top multiplexer F8 or F9 with a 6-input lookup table.

7. The method according to claim 1, characterized in that, In steps A3 and A4, when selecting the optimal combination structure from multiple candidate combination structures, the following steps are performed: Step A10: Obtain the number of lookup tables on the critical path of each candidate combination structure. The number of lookup tables on the critical path is proportional to the latency. Step A20: Determine whether there is only one candidate combination structure with the smallest number of lookup tables for the critical path. If so, determine the candidate combination structure with the smallest number of lookup tables for the critical path as the optimal candidate combination structure. Otherwise, only retain the candidate combination structure with the smallest number of lookup tables and proceed to step A30. Step A30: Obtain the total number of lookup tables for each candidate combination structure. The total number of lookup tables is proportional to the area. Step A40: Determine if there is only one candidate combination structure with the smallest total number of lookup tables. If so, determine the candidate combination structure with the smallest total number of lookup tables as the optimal candidate combination structure. Otherwise, only retain the candidate combination structure with the smallest total number of lookup tables and proceed to step A50. Step A50: Obtain the total number of dedicated multiplexers for each candidate combination structure. The dedicated multiplexers include multiplexers F7, F8 and F9. The total number of multiplexers is proportional to the area. Step A60: Determine whether there is only one candidate combination structure with the smallest total number of multiplexers. If so, determine the candidate combination structure with the smallest total number of dedicated multiplexers as the optimal candidate combination structure. Otherwise, determine the candidate combination structure generated first or last among the candidate combination structures with the smallest total number of multiplexers as the optimal candidate combination structure.

8. An electronic device, characterized in that, include: At least one processor; And, a memory communicatively connected to the at least one processor; The memory stores instructions executable by the at least one processor, the instructions being configured to perform the method described in any one of claims 1-7.

9. A computer-readable storage medium, characterized in that, The device stores computer-executable instructions for performing the method of any one of claims 1-7.

Images