CAN bus controller protocol bit error detection method and device

Abstract

The invention discloses a CAN bus controller protocol bit error detection method and a CAN bus controller protocol bit error detection device, which are characterized in that a CAN bus network is simulated based on integrated circuit automatic test equipment (ATE), a simulation system is designed, normal function logic for driving a CAN bus controller to be detected is simulated, bit error logic is simulated, and the ATE is utilized to detect the protocol bit error of the CAN bus controller. And normal function verification and bit error detection of the to-be-detected CAN bus controller are efficiently realized. The technical problem that whether the CAN bus controller can effectively identify and process the position error when the position overturning phenomenon of the CAN bus is caused by electromagnetic interference, improper wiring or other reasons is effectively solved, so that the situation that the whole bus system is abnormal or paralyzed due to the fact that the error processing is not timely is prevented.

Description

Technical Field

[0001] The invention relates to the technical field of aerospace component quality assurance and testing, and in particular to a method and device for detecting protocol bit errors of a CAN bus controller. Background Art

[0002] Since its introduction, CAN bus has been widely used in the automotive industry, industrial automation and other fields. In recent years, with the continuous improvement of the exchange rate and component standardization requirements of aerospace electronic systems, it has gradually penetrated into aerospace engineering. Its most notable feature is that it cancels the traditional station address encoding and replaces it with encoding the communication data. Through message filtering, it can realize various data transmission methods such as point-to-point, multi-point and broadcast. The entire network connects all nodes through two lines. There is no limit on the number of nodes on the network. Each node can actively send messages, and the communication rate can be as high as 1Mbps. The most important component of the entire CAN bus network is the CAN bus controller, which implements the entire CAN communication protocol, including frame ID, frame data, frame format, frame type, CRC check, processing process and response detection, so that when the CAN bus node is connected, it only needs to consider the communication between the microprocessor and the CAN bus controller, which greatly improves the system design efficiency. However, this design also means that all abnormalities and errors on the CAN bus need to be identified and processed by the CAN bus controller. To this end, it is urgent to test and verify the error recognition and processing capabilities of the CAN bus controller to prevent the entire bus system from being abnormal or paralyzed due to untimely error processing.

[0003] Due to the complex and diverse field environment, the CAN bus will inevitably encounter various interference factors, one of the most common errors is the bit error. A bit error refers to a bit flipping phenomenon caused by electromagnetic interference, improper wiring or other reasons, which causes the information received by the receiver to be inconsistent with the original information of the sender. If this error cannot be identified in time, it will not only affect the communication quality, but in serious cases, it may even cause system dysfunction and become a channel for attackers to attack the system. Summary of the invention

[0004] The technical problem solved by the present invention is: to overcome the deficiencies of the prior art and provide a CAN bus controller protocol bit error detection method and device to verify whether the CAN bus controller has a bit error that cannot be identified vulnerability.

[0005] The technical solution of the present invention is: 1. A CAN bus controller protocol bit error detection method, comprising the following steps:

[0006] (1) Build the hardware environment, simulate the CAN bus network through ATE, and connect the CAN bus controller to be tested to ATE through the test interface board;

[0007] (2) designing and implementing a simulation system to simulate the normal function logic of the CAN bus controller to be tested, simulate the bit error logic, and generate a VCD file and a simulation waveform; the VCD file includes a VCD file generated according to the normal function logic or a VCD file generated after injecting the bit error logic into the normal function logic;

[0008] (3) According to the vector format required by ATE, the VCD file generated according to the normal function logic is converted into a test vector. After verifying that the CAN bus controller to be tested is operating normally, the VCD file generated after injecting bit error logic into the normal function logic is converted into a test vector, imported into ATE, and the CAN bus controller to be tested is triggered to collect the output waveform of the CAN bus controller;

[0009] (4) Compare and analyze the simulation waveform and the output waveform to determine the response of the CAN bus controller to the bit error and obtain the detection result.

[0010] Furthermore, in step (1), the ATE simulates a CAN bus network, including simulating a microprocessor to provide upstream control information to a CAN bus controller, and simulating a bus transceiver to provide a data transmission channel to the CAN bus controller.

[0011] Furthermore, in step (2), according to different functional items of the CAN bus controller to be tested, its input and output signal characteristics are analyzed, and a simulation program for the normal functional logic and simulated bit error logic of the CAN bus controller to be tested is written using the Verilog language.

[0012] Furthermore, in step (2), the simulation waveform is a normal simulation waveform output by the CAN bus controller when it effectively identifies and processes a bit error, or an erroneous simulation waveform output by the CAN bus controller when it fails to effectively identify and process a bit error.

[0013] Furthermore, in the step (3), the operation verification of the CAN bus controller includes verification of the parameters and functions of the CAN bus controller, the parameter verification includes DC parameters and AC parameters, and the function verification is normal function verification; the specific verification method is: according to the data manual of the CAN bus controller, the Level, Timing and test program are defined on the ATE, and a VCD file without injecting bit error logic is obtained by using the simulation system, which is converted into a test vector, imported into ATE, and the CAN bus controller to be tested is triggered. If the output waveform of the CAN bus controller to be tested is normal, the verification is passed.

[0014] Furthermore, different specific bit error logics are simulated to test the CAN bus controller to be tested in turn.

[0015] The present invention also provides a CAN bus controller protocol bit error detection device, comprising:

[0016] ATE, used to simulate the CAN bus network; trigger the CAN bus controller to be tested according to the test vector;

[0017] Test interface board, used to connect ATE and the CAN bus controller to be tested;

[0018] A simulation system is used to simulate the normal function logic of the CAN bus controller to be tested, and simulate the bit error logic to generate a VCD file; the VCD file includes a VCD file generated according to the normal function logic, or a VCD file generated after the bit error logic is injected into the normal function logic; and is also used to generate a simulation waveform;

[0019] Vector conversion tool, used to convert VCD files into test vectors according to the vector format required by ATE and import them into ATE;

[0020] The comparison analysis tool is used to compare and analyze the output waveform of the CAN bus controller and the simulation waveform generated by the simulation system, determine the response of the CAN bus controller to the bit error, and obtain the detection result.

[0021] Furthermore, in the ATE, the ATE simulates a CAN bus network, including simulating a microprocessor to provide upstream control information to a CAN bus controller, and simulating a bus transceiver to provide a data transmission channel to the CAN bus controller.

[0022] Furthermore, in the simulation system, according to different functional items of the CAN bus controller to be tested, its input and output signal characteristics are analyzed, and a simulation program for the normal functional logic and simulated bit error logic of the CAN bus controller to be tested is written using the Verilog language; the generated simulation waveform is a normal simulation waveform output by the CAN bus controller when it effectively identifies and processes bit errors, or an erroneous simulation waveform output by the CAN bus controller when it fails to effectively identify and process bit errors.

[0023] Furthermore, the simulation system simulates different specific bit error logics; the comparison analysis tool performs comparative analysis based on the output waveform of the CAN bus controller and the simulation waveform generated by the simulation system to determine whether the CAN bus controller to be tested can effectively identify and process a certain bit error logic when it occurs, and then detect whether it has a vulnerability that cannot correctly detect a certain bit error.

[0024] The advantages of the present invention compared with the prior art are:

[0025] (1) When testing the CAN bus controller to be tested, the method proposed in the present invention does not establish an actual CAN bus network. Instead, the CAN bus network is simulated based on integrated circuit automatic test equipment (ATE), that is, the operating environment of the CAN bus controller is simulated. There is no need to design upstream and downstream circuits and different nodes to construct the CAN bus network. By designing a simulation system, the normal functional logic of the CAN bus controller to be tested is simulated, and the bit error logic is simulated. Then, ATE is used to efficiently realize the normal verification and bit error detection of the CAN bus controller to be tested.

[0026] (2) The architecture of the device proposed in the present invention is universal, and CAN bus controllers from different manufacturers do not need to be designed from scratch; the use of ATE can detect the operating status of all pins on the bus controller in real time, and can easily inject errors; during the bit error vulnerability detection process, the device can fully control the entire test process and avoid interference with other nodes in the actual network. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic diagram of the device of the present invention. DETAILED DESCRIPTION

[0028] In order to better understand the technical solution of the present invention, the specific implementation mode of the present invention is described in detail below with reference to the accompanying drawings.

[0029] The CAN bus controller protocol bit error detection method proposed by the present invention mainly includes the following steps:

[0030] (1) Build the hardware environment

[0031] The CAN bus network is simulated by ATE, and the CAN bus controller to be tested is connected to ATE through the test interface board; there is no actual CAN bus network in the present invention, so both the upstream processing circuit and the downstream bus transceiver are simulated by ATE. ATE not only simulates the microprocessor to provide upstream control information to the CAN bus controller, but also simulates the bus transceiver to provide a data transmission channel to the CAN bus controller, so as to ensure the normal operation of the CAN bus controller.

[0032] Reference Figure 1 As shown in the figure, the CAN bus controller is connected to the ATE machine through the test interface board, and each pin of the CAN bus controller to be tested is connected to a specified channel of the ATE machine, and connected on the test interface board through a non-destructive fixture. The test interface board is equipped with oscilloscope detection points for the relevant pins of the CAN bus controller to be tested (for some advanced ATE, the waveform capture software provided by the machine can be used).

[0033] (2) Design and implement the simulation system

[0034] The simulation system can simulate the normal functional logic of driving the CAN bus controller, and can also simulate specific bit error logic. By running the simulation system, VCD files and simulation waveforms can be generated; wherein, the VCD file can be the normal functional logic or the VCD file corresponding to the normal functional logic after the bit error logic is injected into the normal functional logic; the simulation waveform can be the normal simulation waveform output by the CAN bus controller when it effectively identifies and processes the bit error, or the error simulation waveform output by the CAN bus controller when it fails to effectively identify and process the bit error.

[0035] Specifically, the simulation program for driving the normal function logic and bit error logic of the CAN bus controller is implemented by the Verilog high-level programming language. The CAN bus controller can be divided into various sub-module designs according to different functions. The simulation program mainly focuses on the input and output signal design of different functions. According to the different functional items of the CAN bus controller to be tested, the input and output signal characteristics are analyzed to write the simulation program for simulating the normal function logic and the bit error logic of the CAN bus controller to be tested. As for the logic circuit inside the CAN bus controller, it can be "black boxed".

[0036] (3) Obtaining the test vector

[0037] The vector conversion tool is used to simulate the system to convert the VCD file into the test vector required by the corresponding ATE machine and import it into ATE.

[0038] ATE test machines from different manufacturers, such as Teradyne and Advantest, have different test software and test vector formats. During the conversion process, tools are selected or written based on the specific machine.

[0039] (4) Parameter and function test

[0040] Because the present invention is not supported by an actual CAN bus network, it is necessary to verify the DC parameters, AC parameters and normal functional logic of the CAN bus controller before performing bit error vulnerability detection. Once all the above tests are passed, it indicates that the CAN bus controller to be tested can operate normally in this environment.

[0041] The specific verification method is: according to the data sheet of the CAN bus controller, define the Level, Timing and test program on the ATE, use the simulation system to obtain the VCD file without injecting bit error logic, convert it into a test vector, import it into ATE, and trigger the CAN bus controller to be tested. If the output waveform of the CAN bus controller to be tested is normal, the verification is passed.

[0042] (5) Bit error vulnerability detection

[0043] After verifying that the CAN bus controller is operating normally, run the simulation system according to the vector format required by ATE, inject bit error logic into the normal functional logic, generate the corresponding VCD file, convert the VCD file into a test vector, import it into ATE, trigger the CAN bus controller to be tested, and collect the output waveform of the CAN bus controller;

[0044] (6) Analysis of test results

[0045] Compare and analyze the simulation waveform and the output waveform to determine the response of the CAN bus controller to the bit error and whether there is a difference between the two. If there is a difference (when the simulation waveform uses the normal simulation waveform output by the CAN bus controller to effectively identify and process the bit error), it indicates that the CAN bus controller under test cannot identify the current bit error and there is a detection vulnerability for the bit error.

[0046] For example: in the non-arbitration area, the CAN bus controller sends "00001" and receives "00000" which cannot be identified as "error" (bit error), which is inconsistent with the manual and relevant standard descriptions. Specifically, when tx_0 sends 1 and rx_0 is 0, the simulation waveform is judged as a bit misalignment. After this moment, tx_0 should send an error frame "6 consecutive 0s" and interrupt int_n is pulled low to meet the bit error detection function requirements in the ISO11898-1 protocol. The execution process of the CAN bus controller to be tested is that tx_0 continues to send the frame "01" and then interrupt int_n is pulled low.

[0047] Repeat steps (5) and (6) for the remaining bit error recognition tests to complete the detection.

[0048] The present invention also provides a CAN bus controller protocol bit error detection device, which can refer to Figure 1 , including the following components:

[0049] ATE, used to simulate the CAN bus network; trigger the CAN bus controller to be tested according to the test vector;

[0050] Test interface board, used to connect ATE and the CAN bus controller to be tested;

[0051] A simulation system is used to simulate the normal function logic of the CAN bus controller to be tested, and simulate the bit error logic to generate a VCD file; the VCD file includes a VCD file generated according to the normal function logic, or a VCD file generated after the bit error logic is injected into the normal function logic; and is also used to generate a simulation waveform;

[0052] Vector conversion tool, used to convert VCD files into test vectors according to the vector format required by ATE and import them into ATE;

[0053] The comparison analysis tool is used to compare and analyze the output waveform of the CAN bus controller and the simulation waveform generated by the simulation system, determine the response of the CAN bus controller to the bit error, and obtain the detection result.

[0054] Specifically, in the ATE, the ATE simulates a CAN bus network, including simulating a microprocessor to provide upstream control information to the CAN bus controller, and simulating a bus transceiver to provide a data transmission channel to the CAN bus controller.

[0055] Specifically, in the simulation system, according to the different functional items of the CAN bus controller to be tested, its input and output signal characteristics are analyzed, and a simulation program that simulates the normal functional logic and the simulated bit error logic of the CAN bus controller to be tested is written using the Verilog language; the generated simulation waveform is a normal simulation waveform output by the CAN bus controller when it effectively identifies and processes bit errors, or an erroneous simulation waveform output by the CAN bus controller when it fails to effectively identify and process bit errors.

[0056] Specifically, the simulation system simulates different specific bit error logics; the comparative analysis tool performs comparative analysis based on the output waveform of the CAN bus controller and the simulation waveform generated by the simulation system to determine whether the CAN bus controller under test can effectively identify and process a certain bit error logic when it occurs, and then detect whether it has a vulnerability that cannot correctly detect a certain bit error.

[0057] It is to be understood that the present invention is described by way of embodiments, and it is known to those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed herein, and embodiments that can fall within the scope of the claims of this application all fall within the scope protected by the present invention.

[0058] The contents not described in detail in the specification of the present invention belong to the common knowledge of those skilled in the art.

Claims

1. A CAN bus controller protocol bit error detection method, characterized in that: The steps include: Build the hardware environment, simulate the CAN bus network through ATE, and connect the CAN bus controller to be tested to ATE through the test interface board; Design and implement a simulation system to simulate and drive the normal functional logic of the CAN bus controller to be tested, simulate the bit error logic, and generate a VCD file and a simulation waveform; the VCD file includes a VCD file generated according to the normal functional logic or a VCD file generated after injecting the bit error logic into the normal functional logic; According to the vector format required by ATE, the VCD file generated according to the normal functional logic is converted into a test vector. After verifying that the CAN bus controller to be tested is operating normally, the VCD file generated after injecting bit error logic into the normal functional logic is converted into a test vector, imported into ATE, and the CAN bus controller to be tested is triggered to collect the output waveform of the CAN bus controller; The simulation waveform and the output waveform are compared and analyzed to determine the response of the CAN bus controller to the bit error and obtain the detection result.

2. The CAN bus controller protocol bit error detection method according to claim 1, characterized in that: ATE simulates the CAN bus network, including simulating a microprocessor to provide upstream control information to the CAN bus controller, and simulating a bus transceiver to provide a data transmission channel to the CAN bus controller.

3. The CAN bus controller protocol bit error detection method according to claim 1, characterized in that: According to the different functional items of the CAN bus controller to be tested, its input and output signal characteristics are analyzed, and the simulation program of the normal functional logic and simulated bit error logic of the CAN bus controller to be tested is written using the Verilog language.

4. The CAN bus controller protocol bit error detection method according to claim 1, characterized in that: The simulation waveform is a normal simulation waveform output by the CAN bus controller when it effectively identifies and processes a bit error, or an erroneous simulation waveform output by the CAN bus controller when it fails to effectively identify and process a bit error.

5. The CAN bus controller protocol bit error detection method according to claim 1, characterized in that: The operation verification of the CAN bus controller includes verification of the parameters and functions of the CAN bus controller. The parameter verification includes DC parameters and AC parameters, and the function verification is normal function verification. The specific verification method is: according to the data manual of the CAN bus controller, the Level, Timing and test program are defined on the ATE, and the VCD file without injecting bit error logic is obtained by using the simulation system, which is converted into a test vector and imported into ATE to trigger the CAN bus controller to be tested. If the output waveform of the CAN bus controller to be tested is normal, the verification is passed.

6. The CAN bus controller protocol bit error detection method according to claim 1, characterized in that: Simulate different specific bit error logics and test the CAN bus controller to be tested in turn.

7. A CAN bus controller protocol bit error detection device, characterized in that: include: ATE, used to simulate CAN bus network; Trigger the CAN bus controller to be tested according to the test vector; Test interface board, used to connect ATE and the CAN bus controller to be tested; A simulation system, used for simulating the normal function logic of the CAN bus controller to be tested, simulating the bit error logic, and generating a VCD file; the VCD file includes a VCD file generated according to the normal function logic, or a VCD file generated after injecting the bit error logic into the normal function logic; It is also used to generate simulation waveforms; Vector conversion tool, used to convert VCD files into test vectors according to the vector format required by ATE and import them into ATE; The comparison analysis tool is used to compare and analyze the output waveform of the CAN bus controller and the simulation waveform generated by the simulation system, determine the response of the CAN bus controller to the bit error, and obtain the detection result.

8. The CAN bus controller protocol bit error detection device according to claim 7, characterized in that: In the ATE, the ATE simulates a CAN bus network, including simulating a microprocessor to provide upstream control information to a CAN bus controller, and simulating a bus transceiver to provide a data transmission channel to the CAN bus controller.

9. The CAN bus controller protocol bit error detection device according to claim 7, characterized in that: In the simulation system, according to the different functional items of the CAN bus controller to be tested, its input and output signal characteristics are analyzed, and the simulation program of the normal functional logic and the simulated bit error logic of the CAN bus controller to be tested is written using the Verilog language; the generated simulation waveform is a normal simulation waveform output by the CAN bus controller when it effectively identifies and processes bit errors, or an erroneous simulation waveform output by the CAN bus controller when it fails to effectively identify and process bit errors.

10. The CAN bus controller protocol bit error detection device according to claim 7, characterized in that: The simulation system simulates different specific bit error logics; the comparison analysis tool compares and analyzes the output waveform of the CAN bus controller and the simulation waveform generated by the simulation system to determine whether the CAN bus controller to be tested can effectively identify and process a certain bit error logic when it occurs, and then detects whether it has a vulnerability that cannot correctly detect a certain bit error.

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