Groove type beta-Ga2O3 thin film transistor and preparation method thereof
By adopting a trench design and a BN dielectric layer in the β-Ga2O3 thin film transistor, the problem of low electron mobility and thermal conductivity of the β-Ga2O3 thin film transistor is solved, and the switching control capability and reliability of the device are improved.
Patent Information
- Application Number
- CN202411877751.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-19
- Publication Date
- 2025-04-08
AI Technical Summary
The existing β-Ga2O3 thin film transistors have low electron mobility and thermal conductivity, which limits their application in high-frequency and high-power devices, and the gate has insufficient switching control capabilities for electron mobility layer.
The design of a trench type β-Ga2O3 thin film transistor includes growing an undoped β-Ga2O3 layer and an N-doped β-Ga2O3 layer on an insulating substrate, and etching the trench on the top surface of the N-doped β-Ga2O3 layer, covering the trench with an oxide dielectric layer, and inserting the BN dielectric layer under the gate.
Through this design, the leakage current is reduced, the phonon scattering ability is improved, the switching control capability of the electron migration layer is improved, and the gate breakdown voltage threshold is increased, improving the reliability of the device.
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Figure CN119789494A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor device technology, and in particular to a trench-type β-Ga2O3 thin film transistor and a preparation method thereof. Background Art
[0002] The fourth-generation semiconductor gallium oxide (Ga2O3) is an important material in the ultra-wide bandgap semiconductor material system. Its ultra-wide bandgap of 4.8eV makes it a potential candidate material for high-power devices for next-generation applications. Ga2O3 has five crystal structures, namely rhombohedral (α), monoclinic (β), defective spinel (γ), cubic (δ) and orthorhombic (ε). β-Ga2O3 has gradually become the preferred material device at home and abroad in recent years due to its stability at high temperatures.
[0003] Since the critical electric field value of β-Ga2O3 is 8MV / cm, which is much higher than more mature power semiconductor materials such as 2.5 MV / cm of 4H-SiC and 3.3 MV / cm of GaN, β-Ga2O3 devices can have a larger breakdown voltage, smaller on-resistance, lower energy consumption, and stronger resistance to extreme environments. It is considered to be an important basic material to support the rapid development of information, energy, transportation, manufacturing, national defense and other fields in the future.
[0004] However, the electron mobility and thermal conductivity of β-Ga2O3 are low, which limits its application in high-frequency and high-power devices. In order to solve the existing problems of electron mobility and low thermal conductivity of β-Ga2O3, more designs need to be made on the substrate and structure of the device. The existing technology usually prepares MOSFET, bottom-gate thin-film transistor, and top-gate thin-film transistor. Due to the thin thickness and low crystal quality of the electron transfer layer, trench preparation is usually not performed, resulting in insufficient control of the gate over the switch of the electron transfer layer.
[0005] In view of the various existing research directions, how to improve the breakdown voltage capability under the premise of ensuring the electron mobility and low thermal conductivity of the existing β-Ga2O3 thin film transistor is the main research direction of the present invention. Summary of the invention
[0006] In view of the problems in the related art, the present invention proposes a trench-type β-Ga2O3 thin film transistor and a preparation method thereof to overcome the technical defects existing in the existing related art.
[0007] The technical solution of the present invention is as follows: a trench-type β-Ga2O3 thin film transistor and a preparation method thereof, wherein the thin film transistor uses an insulating substrate as a growth substrate, grows an ultra-thin heteroepitaxial layer of undoped β-Ga2O3 on the substrate surface, and then continues to epitaxially grow an N-type doped β-Ga2O3 layer on the ultra-thin heteroepitaxial layer, etches a trench on the top surface of the N-type doped β-Ga2O3 layer, and coats the trench with an oxide dielectric layer to isolate the gate and the source and drain, and can also insert a 5-8 nm thick BN dielectric layer between the oxide dielectric layer and the N-type doped β-Ga2O3 layer under the gate. The specific content of the invention is as follows: A trench type β-Ga2O3 thin film transistor comprises an insulating substrate, an undoped β-Ga2O3 layer, an N-type doped β-Ga2O3 layer, an oxide dielectric layer, a source electrode, a gate electrode, a drain electrode and an insulating protective layer.
[0008] The insulating substrate, the undoped β-Ga2O3 layer, and the N-type doped β-Ga2O3 layer are arranged in sequence from bottom to top.
[0009] A source metal electrode layer and a drain metal electrode layer are symmetrically arranged on both sides of the top surface of the N-type doped β-Ga2O3 layer.
[0010] A groove is etched in the middle of the top surface of the N-type doped β-Ga2O3 layer, and the groove is covered by an oxide dielectric layer. A gate metal electrode layer is arranged in the groove covered by the oxide dielectric layer.
[0011] The insulating protective layer covers the surface of the thin film transistor and etches the electrode welding points of the exposed source, gate and drain.
[0012] More preferably, a BN dielectric layer is deposited below the oxide dielectric layer between the source and the drain.
[0013] More preferably, the BN insulating layer has a thickness of less than 10 nm.
[0014] More preferably, the source metal electrode layer and the drain metal electrode layer conformally cover the side surfaces of the undoped β-Ga2O3 layer and the N-type doped β-Ga2O3 layer and extend onto the insulating substrate.
[0015] More preferably, the oxide dielectric layer partially covers the source metal electrode layer and the drain metal electrode layer.
[0016] More preferably, the electrode welding points of the source and the drain are arranged in the extension areas of the source metal electrode layer and the drain metal electrode layer on the insulating substrate.
[0017] The method for preparing the thin film transistor comprises the following steps: S1) cleaning and drying the insulating substrate, epitaxially preparing a 50-55 nm thick undoped β-Ga2O3 layer and a 50-55 nm thick N-type doped β-Ga2O3 layer at 850-900°C; S2) Activate the N-type doped β-Ga2O3 layer at 900-1000℃ for 1min, then anneal in N2 for 1-2min at 500℃; S3) The N-type doped β-Ga2O3 layer is etched by ICP dry etching to prepare a 20-50 nm deep groove, and then the source and drain electrode regions are left by photolithography patterning, and the metal electrode layer is deposited by electron beam evaporation. After cleaning and drying, it is annealed in N2 for 1 min at an annealing temperature of 400-500°C; S4) ALD atomic layer deposition of oxide dielectric layer, photolithography patterning to prepare gate, electron beam evaporation deposition of metal electrode layer, cleaning and drying, annealing in N2 for 1-2 minutes, annealing temperature 500°C; S5) Deposit 150-200nm thick SiO2 or SiN x Insulating protection layer, photolithography patterning and etching to expose gate, source and drain electrode welding points.
[0018] Preferably, in step S1), MOCVD is used to epitaxially grow an undoped β-Ga2O3 layer, triethylgallium and high-purity oxygen are used as precursors of gallium and oxygen, the flow rates of TEGa and O2 are 100 sccm and 500 sccm respectively, while maintaining a growth pressure of 15 Torr, and the growth time is 25 to 40 minutes.
[0019] Preferably, in step S1), MOCVD is used to epitaxially grow an N-type doped β-Ga2O3 layer, and a donor organic source, triethylgallium and high-purity oxygen are used as precursors of gallium and oxygen. The flow rates of the donor organic source, TEGa and O2 are 60-80 sccm, 100 sccm and 800 sccm, respectively, while maintaining a growth pressure of 15 Torr, and the growth time is 30-50 min.
[0020] More preferably, the donor ion of the donor organic source in step S1) is one of Ge, Si and Sn.
[0021] More preferably, the donor organic source is one of germane, silane and triethyltin.
[0022] More preferably, in step S3), the groove depth is 20-30 nm.
[0023] Preferably, the etching gas used for dry etching in step S3) is one of Ar or Cl2.
[0024] Preferably, the metal electrode layers of the source and drain in step S3) are Ti / Au with a thickness of 20-30 nm / 150-200 nm.
[0025] Preferably, the metal electrode layers of the source and drain in step S3) are Ti / Al / Ni / Au, with thicknesses of 20-30 nm / 100-150 nm / 50-70 nm / 50-70 nm.
[0026] Preferably, the material of the oxide dielectric layer in step S4) is Al2O3 or SiO2.
[0027] More preferably, the oxide dielectric layer has a thickness of 20-25 nm.
[0028] Preferably, the metal electrode layer in step S4) is Ni / Au, and has a thickness of 30-50 nm / 150-200 nm.
[0029] Preferably, the metal electrode layer in step S4) is Ti / Au / Ti / Al, and has a thickness of 20-30 nm / 100-150 nm / 40-60 nm / 50-70 nm.
[0030] More preferably, in step S4), a BN dielectric layer is deposited before depositing the oxide dielectric layer.
[0031] Beneficial effects of the present invention: Compared with the prior art, the trench-type β-Ga2O3 thin-film transistor provided by the present invention prepares an undoped β-Ga2O3 layer and then epitaxially grows a high-crystallinity N-type doped β-Ga2O3 thin film thereon, thereby reducing leakage current and improving phonon scattering capability.
[0032] Furthermore, the use of a trench top gate can provide better switching control capability of the electron transport layer.
[0033] Furthermore, a BN dielectric layer is added to further improve the problem of increased leakage current caused by etching the grooves and increase the gate breakdown voltage threshold.
[0034] Furthermore, the conformal coating of the metal electrodes of the source and drain provides better electrode welding points, avoids damage to the doped layer film caused by wire crimping, and improves device reliability. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0036] Figure 1 This is a schematic diagram of the structure of a Ge-doped β-Ga2O3 thin film transistor prepared in Example 1 of the present invention.
[0037] Figure 2 This is a schematic diagram of the structure of the BN inserted layer Si-doped β-Ga2O3 thin film transistor prepared in Example 2 of the present invention.
[0038] Figure 3 Schematic diagram of the structure of the Sn-doped β-Ga2O3 thin film transistor conformally coated with a metal electrode prepared in Example 3 of the present invention.
[0039] Among them, 1-insulating substrate, 2-undoped β-Ga2O3 layer, 3-Ge-doped β-Ga2O3 layer, 4-source metal electrode layer, 5-drain metal electrode layer, 6-gate metal electrode layer, 7-BN dielectric layer, 8-oxide dielectric layer, 9-SiO2 insulating protection layer, 10-Si-doped β-Ga2O3 layer, 11-Sn-doped β-Ga2O3 layer, 12-SiN x Insulation protective layer. DETAILED DESCRIPTION
[0040] In order to make the purpose, technical scheme and advantages of the present invention clearer, the technical scheme in the embodiment of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. It should be understood by those skilled in the art that the embodiments are only to help understand the present invention and should not be regarded as specific limitations of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present invention. The process parameters of the following embodiments that do not specify specific conditions are usually based on conventional conditions.
[0041] The endpoints and any values of the ranges disclosed in the present invention are not limited to the precise ranges or values, and these ranges or values should be understood to include values close to these ranges or values. For numerical ranges, the endpoint values of each range, the endpoint values of each range and the individual point values, and the individual point values can be combined with each other to obtain one or more new numerical ranges, which should be regarded as specifically disclosed in the present invention.
[0042] Example 1, preparing a Ge-doped β-Ga2O3 thin film transistor, comprising the following steps: S1) using a 4-inch (0001) flat sapphire wafer as an insulating substrate 1, cleaning the insulating substrate 1, using acetone, methanol, isopropyl ketone and deionized water for ultrasonic cleaning for 20 minutes in sequence to remove surface grease, residual acetone, other organic impurities and residual organic solvents, and finally drying with high-pressure nitrogen and drying in an oven at 100° C. for 40 minutes; S2) After MOCVD vacuuming and preheating at 800°C, epitaxially prepare a 50-55 nm thick undoped β-Ga2O3 layer 2 and a 50-55 nm thick Ge-doped β-Ga2O3 layer 3; S2a) The epitaxial temperature of the undoped β-Ga2O3 layer 2 is 900°C, triethylgallium and high-purity oxygen are used as gallium and oxygen precursors, the flow rates of TEGa and O2 are 100 sccm and 500 sccm respectively, the growth pressure is maintained at 15 Torr, and the growth time is 35 min; S2b) Ge-doped β-Ga2O3 layer 3 epitaxial growth temperature is 850°C, germane, triethylgallium and high-purity oxygen are used as precursors of germanium, gallium and oxygen, the flow rates of GeH4, TEGa and O2 are 80 sccm, 100 sccm and 800 sccm respectively, the growth pressure is maintained at 15 Torr, and the growth time is 40 min; S3) The temperature in the MOCVD chamber is raised to 1000°C to activate the Ge-doped β-Ga2O3 layer 3 for 1 min, then the temperature is lowered to 500°C and annealed in N2 for 2 min; S4) The Ge-doped β-Ga2O3 layer 3 is etched by ICP dry Cl2 to prepare a groove with a depth of 20 nm, and then patterned by photolithography to leave the source and drain positions, and the source 4 and drain metal electrode layer 5 are deposited by electron beam evaporation. After cleaning and drying, annealing is performed in N2 at 400°C for 1 min; The metal electrode layer structure of the source and drain is Ti / Al / Ni / Au, with a thickness of 20 / 100 / 50 / 50nm. The metal electrode layer covers both sides of the top surface of the Ge-doped β-Ga2O3 layer 3, leaving electrode welding points on both sides; S5) ALD deposits a 25 nm Al2O3 dielectric layer 8, photolithography patterning is used to prepare a gate at the groove position, and electron beam evaporation is used to deposit a Ti / Au / Ti / Al (20 / 100 / 40 / 50 nm) metal electrode layer 6. After cleaning and drying, annealing is performed in N2 for 2 min at an annealing temperature of 500°C. S5) ALD equipment is used to deposit a 200 nm SiO2 insulating protection layer 9, and the electrode contact points of the exposed gate, source and drain are etched by photolithography patterning. After cleaning and drying, the thin film transistor functional unit is prepared.
[0043] A β-Ga2O3 thin film transistor invented in this embodiment selects a c-plane sapphire substrate, which is conducive to preparing an undoped β-Ga2O3 film with a (010) crystal phase, and growing a Ge-doped β-Ga2O3 film thereon, which can achieve a higher degree of crystallinity, thereby helping to reduce leakage current and increase phonon scattering ability. At the same time, the use of sapphire as a substrate saves manufacturing costs and is competitive. Finally, the trench embedded gate design improves the gate control capability and increases the narrowness of the device switching threshold.
[0044] Example 2, preparing a BN insertion layer Si-doped β-Ga2O3 thin film transistor, comprising the following steps: S1) using a 4-inch (0001) flat sapphire wafer as an insulating substrate 1, cleaning the insulating substrate 1, using acetone, methanol, isopropyl ketone and deionized water for ultrasonic cleaning for 10 minutes in sequence, respectively removing surface grease, residual acetone, other organic impurities, and residual organic solvents, and finally drying with high-pressure nitrogen and drying in an oven at 100° C. for 30 minutes; S2) After MOCVD is vacuumed and preheated at 800°C, a 50-55 nm thick undoped β-Ga2O3 layer 2 and a 50-55 nm thick Si-doped β-Ga2O3 layer 10 are epitaxially prepared; S2a) The epitaxial temperature of the undoped β-Ga2O3 layer 2 is 900°C, triethylgallium and high-purity oxygen are used as gallium and oxygen precursors, the flow rates of TEGa and O2 are 100 sccm and 500 sccm respectively, the growth pressure is maintained at 15 Torr, and the growth time is 25 min; S2b) The epitaxial temperature of Si-doped β-Ga2O3 layer 10 is 850°C. Silane, triethylgallium and high-purity oxygen are used as precursors of silicon, gallium and oxygen. The flow rates of SiH4, TEGa and O2 are 60 sccm, 100 sccm and 800 sccm respectively. The growth pressure is maintained at 15 Torr and the growth time is 30 min. S3) the temperature in the MOCVD chamber is raised to 1000°C to activate the Si-doped β-Ga2O3 layer 10 for 1 minute, then the temperature is lowered to 500°C and annealed in a nitrogen environment for 2 minutes; S4) The Si-doped β-Ga2O3 layer 10 is etched by ICP dry Cl2 etching to prepare a groove with a depth of 30 nm, and then patterned by photolithography to leave the source and drain positions, and the source and drain metal electrode layers are deposited by electron beam evaporation. After cleaning and drying, annealing is performed in N2 at 500°C for 1 min; The source and drain metal layer structures are Ti / Al / Ni / Au, with thicknesses of 20 / 100 / 50 / 50 nm. The metal electrode layer covers both sides of the top surface of the Si-doped β-Ga2O3 layer 10, leaving electrode welding points on both sides; S5) PECVD magnetron sputtering of 5 nm BN film 7, photolithography patterning to expose the source and drain, and dry etching to remove the BN film on the source and drain metal layers; S6) ALD equipment is used to deposit a 20 nm Al2O3 dielectric layer 8, and a gate is prepared at the groove position after photolithography patterning. Ni / Au (50 / 200 nm) metal electrode layer 6 is deposited by electron beam evaporation. After cleaning and drying, it is annealed in N2 for 2 min at an annealing temperature of 500°C; S7) ALD equipment deposits 150nm SiN x The insulating protective layer 12 is patterned by photolithography and etched to expose the electrode contact points of the gate, source and drain. After cleaning and drying, the thin film transistor functional unit is prepared.
[0045] The β-Ga2O3 thin film transistor of the present embodiment further improves the device breakdown voltage capability by inserting a boron nitride BN dielectric layer 7 .
[0046] Example 3, preparing a Sn-doped β-Ga2O3 thin film transistor conformally coated with a metal electrode, comprising the following steps: S1) Using a 4-inch (0001) flat sapphire wafer as an insulating substrate 1, the insulating substrate 1 is cleaned by ultrasonic cleaning with acetone, methanol, isopropyl ketone and deionized water for 15 minutes in sequence to remove surface grease, residual acetone, other organic impurities and residual organic solvents, and finally dried with high-pressure nitrogen and dried in an oven at 100° C. for 30 minutes; S2) After MOCVD vacuum preheating at 800°C, epitaxially prepare a 50-55 nm thick undoped β-Ga2O3 layer 2 and a 50-55 nm thick Sn-doped β-Ga2O3 layer 11; S2a) The epitaxial temperature of the undoped β-Ga2O3 layer 2 is 900°C, triethylgallium and high-purity oxygen are used as gallium and oxygen precursors, the flow rates of TEGa and O2 are 100 sccm and 500 sccm respectively, the growth pressure is maintained at 15 Torr, and the growth time is 30 min; S2b) The epitaxial temperature of Sn-doped β-Ga2O3 layer 11 is 850°C, triethyltin, triethylgallium and high-purity oxygen are used as precursors of silicon, gallium and oxygen, the flow rates of TESn, TEGa and O2 are 70 sccm, 100 sccm and 800 sccm respectively, the growth pressure is maintained at 15 Torr, and the growth time is 30 min; S3) the temperature in the MOCVD chamber is raised to 950°C to activate the Sn-doped β-Ga2O3 layer 11 for 1 min, then the temperature is lowered to 500°C and annealed in a nitrogen environment for 2 min; S4) The Sn-doped β-Ga2O3 layer 11 is etched by ICP dry Cl2 to prepare a groove with a depth of 25 nm, and then patterned by photolithography to leave the source and drain positions, and the source and drain metal electrode layers are deposited by electron beam evaporation. After cleaning and drying, annealing is performed in N2 at 500°C for 1 min; The source and drain metal electrode layer structures are Ti / Al / Ni / Au, with thicknesses of 20 / 100 / 50 / 50 nm, conformally covering the undoped β-Ga2O3 layer 2 and the Sn-doped β-Ga2O3 layer 11 and their sides, and the metal electrode layer extends onto the insulating substrate 1, leaving electrode welding point positions on the substrate; S5) Sputter magnetron sputtering 5nm BN film 7, photolithography patterning to expose the source and drain, dry etching to remove the BN film on the source and drain metal layers; S6) ALD equipment is used to deposit a 25 nm SiO2 dielectric layer 8, and a gate is prepared at the groove position after photolithography patterning. Ni / Au (50 / 200 nm) metal electrode layer is deposited by electron beam evaporation. After cleaning and drying, it is annealed in N2 for 2 min at an annealing temperature of 500°C. S7) ALD equipment is used to deposit a 200 nm SiO2 insulating protection layer 9, and the electrode contact points of the exposed gate, source and drain are etched by photolithography patterning. After cleaning and drying, the thin film transistor functional unit is prepared.
[0047] A trench-type β-Ga2O3 thin-film transistor invented in this embodiment further conformally coats the metal electrode layer to change the position of the electrode solder joint and improve the device reliability problem caused by solder joint crimping.
[0048] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A trench-type β-Ga2O3 thin film transistor, characterized in that: It comprises an insulating substrate (1), an undoped β-Ga2O3 layer (2), an N-type doped β-Ga2O3 layer, an oxide dielectric layer (8), a source electrode, a drain electrode, a gate electrode and an insulating protective layer (9); The insulating substrate (1), the undoped β-Ga2O3 layer (2), and the N-type doped β-Ga2O3 layer are arranged in sequence from bottom to top; A source metal electrode layer (4) and a drain metal electrode layer (5) are symmetrically arranged on both sides of the top surface of the N-type doped β-Ga2O3 layer; A groove is etched in the middle of the top surface of the N-type doped β-Ga2O3 layer, the groove and part of the metal electrode layer of the source and drain are covered by the oxide dielectric layer (8), and a gate metal electrode layer (6) is arranged in the groove covered by the oxide dielectric layer (8); The insulating protective layer (9) covers the surface of the thin film transistor and etches the electrode welding points of the exposed source, gate and drain.
2. The trench-type β-Ga2O3 thin film transistor according to claim 1, characterized in that: A BN dielectric layer (7) is deposited below the oxide dielectric layer (8) between the source and the drain, and the thickness of the BN dielectric layer (7) is less than 10 nm.
3. The trench-type β-Ga2O3 thin film transistor according to claim 1, characterized in that: The source metal electrode layer (4) and the drain metal electrode layer (5) conformally cover the side surfaces of the undoped β-Ga2O3 layer (2) and the Ge-doped β-Ga2O3 layer (3) and extend onto the insulating substrate (1).
4. The trench-type β-Ga2O3 thin film transistor according to claim 1, characterized in that: The oxide dielectric layer (8) partially covers the source metal electrode layer (4) and the drain metal electrode layer (5), and the electrode welding points of the source and drain are arranged in the extension areas of the source metal electrode layer (4) and the drain metal electrode layer (5) on the insulating substrate layer.
5. The trench-type β-Ga2O3 thin film transistor according to claim 1, characterized in that: The insulating substrate (1) is made of one of sapphire, silicon carbide, diamond, silicon, quartz, ceramic or glass.
6. A method for preparing a thin film transistor according to any one of claims 1 to 5, characterized in that: The following steps are involved: S1) cleaning and drying the insulating substrate, epitaxially preparing a 50-55 nm thick undoped β-Ga2O3 layer and a 50-55 nm thick N-type doped β-Ga2O3 layer at 850-900°C; S2) Activate the N-type doped β-Ga2O3 layer at 900-1000℃ for 1min, then anneal in N2 for 1-2min at 500℃; S3) The N-type doped β-Ga2O3 layer is etched by ICP dry etching to prepare a 20-50 nm deep groove, and then the source and drain electrode regions are left by photolithography patterning, and the metal electrode layer is deposited by electron beam evaporation. After cleaning and drying, it is annealed in N2 for 1 min at an annealing temperature of 400-500°C; S4) ALD atomic layer deposition of oxide dielectric layer, photolithography patterning to prepare gate, electron beam evaporation deposition of metal electrode layer, cleaning and drying, annealing in N2 for 1-2 minutes, annealing temperature 500°C; S5) Deposit 150-200nm thick SiO2 or SiN x Insulating protection layer, photolithography patterning and etching to expose gate, source and drain electrode welding points.
7. The method for preparing a thin film transistor according to claim 5, characterized in that: The donor ion for N-type doping in step S1) is one of Ge, Si and Sn.
8. The method for preparing a thin film transistor according to claim 5, characterized in that: Before depositing the oxide dielectric layer in step S3), a BN dielectric layer is first deposited.
9. The method for preparing a thin film transistor according to claim 5, characterized in that: The metal electrode layer of the source and drain in step S3) is Ti / Au or Ti / Al / Ni / Au, and the metal electrode layer of the gate in step S4) is Ni / Au or Ti / Au / Ti / Al.
10. The method for preparing a thin film transistor according to claim 5, characterized in that: In step S4), the material of the oxide dielectric layer is Al2O3 or SiO2, and the dielectric layer thickness is 20-25 nm.