A method for improving power supply performance using multi-phase interleaved circuits

Abstract

The present invention belongs to the technical field of resonant converters and discloses a method for improving power supply performance using a multi-phase interleaved circuit. By using an interleaved LLC asymmetric wave generation method, the secondary-side driver detects the commutation zone of the primary-side resonant network. Within the energy transmission area of ​​the A-phase primary side, the upper / lower SRB or SRC tubes on the secondary side with different phases (off-phase) are simultaneously briefly and periodically turned on, storing energy in the resonant network. Before shutdown, the SR inserted into the commutation zone drives energy storage in the resonant network. After the SRB or SRC is briefly turned on, the energy is released, thereby extending the output hold time of the entire device. The present invention has the beneficial effects of increasing the gain of the resonant converter, extending the input power-off hold time, and improving the dynamic performance of the power supply.

Description

Technical Field

[0001] The present invention relates to the technical field of resonant converters, and in particular to a method for improving power supply performance using a multi-phase interleaved circuit. Background Art

[0002] LLC (LLC) has become a popular DC / DC topology in power supply applications due to its high efficiency and excellent EMI performance. As power requirements for single PSUs increase, interleaving technology has become an effective method for increasing power levels without significantly upgrading power supply components. In recent years, three-phase interleaved LLC (LLC), a typical interleaved topology, has been widely adopted in telecom and server PSUs. Compared to parallel topologies, three-phase interleaved LLC significantly reduces current ripple and facilitates current balancing. Combined with specialized magnetic component design, the size of the inductor and transformer can also be reduced. Combined with intelligent drive control strategies, hold-up time can be extended. Under the same output power conditions, LLC hold-up time is limited by the size of the input bulk capacitor. Improving output hold-up time is difficult without replacing the bulk capacitor or adding specialized circuitry, such as a baby-boost circuit. However, for multi-phase interleaved LLC converters, the conduction angle of the secondary-side SR rectifiers can be adjusted to store some energy in the transformer, releasing it when the input is shut down, thereby extending hold-up time.

[0003] Therefore, it is necessary to provide a method for improving power supply performance by using a multi-phase interleaved circuit, thereby increasing the gain of the resonant converter, extending the input power-off hold time, and improving the dynamic performance of the power supply. Summary of the Invention

[0004] The present invention discloses a method for improving power supply performance by using a multi-phase interleaved circuit, relating to a three-phase LLC resonant converter, and in particular to a three-phase interleaved LLC resonant full-wave rectifier converter, which is suitable for three-phase interleaved LLC full-wave rectification and can effectively solve the technical problems involved in the background technology.

[0005] To achieve the above object, the technical solution of the present invention is:

[0006] A method for improving power supply performance using a multi-phase interleaved circuit comprises the following steps:

[0007] S1. Determine the circuit structure. The circuit is divided into a primary side and a secondary side. The primary side has multiple primary phases, and the secondary side has multiple secondary phases. The primary phases and secondary phases correspond one to one. The dead zone interval of each phase has a fixed phase difference, and the dead zone time of each primary phase is determined.

[0008] S2, monitor the input voltage or output voltage to determine whether the power is off;

[0009] S3. When power is off, the dead time of a certain primary phase causes a secondary phase that does not correspond to it to be turned on.

[0010] Specifically, a three-phase interleaved LLC circuit is disclosed. It is suitable for applications with high power density and limited space, eliminating the need for adding large input capacitors and extending the output voltage holdover time through staggered short-circuiting. The circuit's primary side comprises three LLC half-bridges, six MOSFETs, and three driver groups. The secondary side comprises three full-bridge rectifiers, twelve MOSFETs, and six driver groups. Three resonant networks comprise a main transformer, a resonant inductor, and a resonant capacitor. The output end features an output electrolytic filter, and intelligent control of the switches in the secondary full-wave rectifier circuit. By intelligently controlling the switches in the secondary rectifier circuit, the present invention improves the gain of the resonant converter, extends the input power-off holdover time, and enhances the dynamic performance of the power supply.

[0011] As a preferred improvement of the present invention: the primary phase is an LLC half-bridge, and the secondary phase is a full-bridge rectifier.

[0012] As a preferred improvement to the present invention, the number of primary phases is 3-6. Specifically, through a three-phase interleaved LLC asymmetric wave generation method, the secondary-side driver detects the commutation zone of the primary-side resonant network. During the dead zone of the A-phase primary operation, the upper / lower switches of the secondary-side staggered SRB or SRC are briefly and periodically turned on simultaneously, storing energy in the resonant network. Before shutdown, the SR drive energy inserted into the commutation zone is stored in the resonant network. After shutdown, the energy is released, thereby extending the output hold time of the entire device. This technical implementation is not limited to three-phase architectures and can be expanded to six-phase architectures. This wave generation method uses existing switching time nodes for asymmetric wave generation, while conventional technologies require complex calculations for the SR leading edge. This wave generation method differs from conventional technologies in that the behavior of the primary-side resonant current (ILr) and the excitation current (ILm) is inconsistent. Conventional technologies implement this method when the two currents are equal, while this patent implements it when the two currents are different.

[0013] As a preferred improvement of the present invention: the number of primary phases is 3, which are defined as phase A, phase B and phase C in sequence according to the phase sequence. When power is off, the secondary phase corresponding to phase B is turned on during the dead time of phase A, or the secondary phase corresponding to phase C is turned on during the dead time of phase B.

[0014] As a preferred improvement of the present invention: when the circuit is powered off, the conduction time is T phaseshift , T setting.max is the maximum pulse width, T seting.min is the minimum pulse width, V error is the output voltage feedback error, V error.max is the maximum value of the output voltage feedback error, V error =(V fb -V ref)*K p *K i , V fb is the output voltage, V ref is the output voltage reference value, K p , K i is the loop operation coefficient.

[0015] As a preferred improvement of the present invention: seting.min 50ns, T setting.max is the corresponding dead time of the primary, V error.max When the voltage is 5%, the circuit performs voltage loop control.

[0016] As a preferred improvement of the present invention: in the step S2, when the input voltage is less than the set value Vac_out, the circuit is judged to be powered off; when the output voltage drops by more than 5%, the circuit is judged to be powered off.

[0017] As a preferred improvement of the present invention: in step S3, when power is off, the circuit switching frequency is first reduced, and when the switching frequency drops to Tfp, the secondary phase is turned on.

[0018] As a preferred improvement of the present invention: Tfp=Fswmin=Frmin+10kHz, where Frmin is the lowest resonant frequency of the primary phase.

[0019] The beneficial effects of the present invention are as follows:

[0020] During the HVDC bus voltage discharge process, the transformer's turns ratio and maximum LLC resonant network gain are fixed, which eventually causes the output voltage to drop. After the countermeasure is implemented (by turning on the SR drive during the primary-side dead band), the gain can be increased, temporarily pulling the output voltage back up, thereby extending the output hold time. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. Those skilled in the art can also derive other drawings based on these drawings without inventive work, among which:

[0022] Figure 1 A schematic diagram of an interleaved circuit;

[0023] Figure 2 This is a flow chart of a method for improving power supply performance using a multi-phase interleaved circuit according to the present invention;

[0024] Figure 3 It is a schematic diagram of three-phase interleaved LLC drive;

[0025] Figure 4 This is a schematic diagram of the dead-zone control of three-phase LLC and SR drive;

[0026] Figure 5 is a schematic diagram of the phase shift curve;

[0027] Figure 6 This is a schematic diagram of driving dead zone phase shift pulse width control;

[0028] Figure 7 It is the three-phase interleaved LLC drive and resonant current;

[0029] Figure 8 It is a three-phase interleaved LLC drive and a phase-out short circuit of the resonant current;

[0030] Figure 9 It is the three-phase resonant current and output voltage of the phase-out short circuit. DETAILED DESCRIPTION

[0031] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0032] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the various components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0033] In addition, the terms "first," "second," and so on, used in this disclosure are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referenced. Thus, a feature specified as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of this disclosure, "plurality" means at least two, such as two or three, unless otherwise specifically defined.

[0034] In the present invention, unless otherwise specified or limited, the terms "connection" and "fixation" should be understood in a broad sense. For example, "fixation" can mean fixed connection, detachable connection, or integration; mechanical connection or electrical connection; direct connection or indirect connection through an intermediate medium; internal communication between two elements or interaction between two elements, unless otherwise specified. Those skilled in the art will be able to understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0035] In addition, the technical solutions between the various embodiments of the present invention can be combined with each other, but it must be based on the fact that ordinary technicians in this field can implement it. When the combination of technical solutions is mutually contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0036] The technical problem to be solved by the present invention is to extend the holding time of the three-phase LLC interleaved topology and improve the power supply performance, such as Figure 1 As shown, the primary side adopts a three-phase interleaved LLC "Y" topology, and the secondary side adopts synchronous SR full-wave rectification. The drivers of the three-phase LLC on the primary side are phase A DRV_A, which is defined as a set of complementary drivers QA1 and QA2; phase B DRV_B, which is defined as a set of complementary drivers QB1 and QB2; and phase C DRV_C, which is defined as a set of complementary drivers QC1 and QC2. The wave interval of each driver group is 1 / 3π, and there is an operating dead zone, as shown in Figure 1. Figure 3 As shown. In the DRV_A diagram, the solid line is the driving waveform of QA1, and the dotted line is the driving waveform of QA2. In the DRV_B diagram, the solid line is the driving waveform of QB1, and the dotted line is the driving waveform of QB2. In the DRV_C diagram, the solid line is the driving waveform of QC1, and the dotted line is the driving waveform of QC2. The circuit control flow chart is shown in FIG. Figure 2 shown.

[0037] The present invention is implemented as follows:

[0038] The input voltage is sampled from the input terminal and compared with the set value Vac_out to determine whether there is a power failure (CASE 1). The power failure is triggered when the AC sampling signal on the primary side is less than the set value of Vac_out. The converted output voltage Vfb gain drops by 5% (CASE 2), which can also trigger the SR to conduct in the primary side dead zone.

[0039] When the three-phase interleaved circuit is operating in steady state, the secondary-side drive of the three-phase interleaved LLC is bound to the primary-side drive. The binding relationship is as follows:

[0040] The primary side QA1, QA2 is divided into two groups corresponding to the secondary side. In the positive half cycle of the resonant current, QA3 and QA6 form a group and switch at the same time. In the negative half cycle of the resonant current, QA4 and QA5 form a group and switch at the same time.

[0041] The primary side QB1, QB2 is divided into two groups corresponding to the secondary side. In the positive half cycle of the resonant current, QB3 and QB6 form a group and switch at the same time. In the negative half cycle of the resonant current, QB4 and QB5 form a group and switch at the same time.

[0042] The primary side QA1 and QA2 are divided into two groups corresponding to the secondary side. In the positive half cycle of the resonant current, QC3 and QC6 are a group and switch at the same time. In the negative half cycle of the resonant current, QC4 and QC5 are a group and switch at the same time.

[0043] LLC and SR dead zone Figure 4 As shown in the figure, there are four comparators inside the MCU and two groups of PWM controllers, namely PWM_H / PWM_L, which control the upper / lower tube drive and reserve the leading / trailing edge adjustment area. For example, the shaded area of ​​LLC_HG / LLC_LG drive is the fixed dead zone inserted by the primary side according to the resonant frequency.

[0044] After the transformer topology is confirmed, the LLC resonant network parameters Lm, Lr, and Cr for each phase are known, and the highest resonant frequency is The lowest resonant frequency is

[0045] In the above circuit, when the input power is off or the output drops out of specification, the primary side resonant network frequency will first be reduced to increase the gain until the switching frequency reaches Tfp (which can be set at Fswmin = Frmin + 10kHz). Figure 5 As shown in the phase shift curve, after the switching frequency drops to the Tfp point, the frequency will not be further reduced to increase the gain and maintain the output holding time; the secondary side SRMOS will be driven to briefly turn on the SRMOS in the primary side dead zone of the other two phases. The Tphaseshift on time is limited by the MCU to the maximum / minimum pulse width. The minimum pulse width can be set to a fixed value Tsetting.min. For example, if the STM32G4 series is used, the typical value can be set to 50ns. The maximum pulse width Tsetting.max is also Tdead_llc, which is updated in real time according to the resonant frequency. Tphaseshift requires the error Verror between Vfb and the feedback. Verror.max is the maximum value of the output voltage Vfb error range, which is generally +5%. The reference value Vref loop proportional (Kp) integral (Ki) is calculated as follows: V error =(V fb -V ref )*K p *K i , The energy after triggering the out-of-phase conduction is stored in the LLC resonant cavity and released cycle by cycle to improve the output gain of the power supply.

[0046] The three-phase interleaved LLC symmetrical wave working waveform is as follows: Figure 7 The three-phase interleaved LLC asymmetric wave working waveform is mainly aimed at the SR drive on the secondary side, such as Figure 7-8As shown in the figure, after the condition is triggered, the phase difference of the resonant current of the three-phase interleaved LLC on the primary side is 60°. It can be seen that there are two dead zones Td1 / Td2 at the beginning and end of each phase complete cycle; the figure shows the LLC resonant current of phase A on the primary side and the SR drive of phase B, and Td1_B and Td2_B are the dead zones of phase B on the primary side.

[0047] IL1 is the primary side A phase resonant current, IL2 is the primary side B phase resonant current, IL3 is the primary side C phase primary current; Short1 is the secondary side B phase pre-conduction SR drive 3 groups (driving QB3 and QB5 at the same time), Short2 is the secondary side B phase pre-conduction SR drive 4 groups (driving QB4 and QB6 at the same time).

[0048] Abnormal converter gain or output voltage conditions (Case 1 or Case 2) trigger the resonant frequency to adjust to the phase shift region. Short3 is activated Td1_B before primary-side phase A, during the positive half-cycle of the resonant current. Short4 is activated Td2_B after primary-side phase A, during the negative half-cycle of the resonant current. The pulse width of Short3 and Short4 is adjustable; refer to the Tphaseshift calculation formula.

[0049] The SR drive conduction in the phase shift region has the following principles:

[0050] (1) Phase staggered conduction: SRB short-circuit trigger conduction occurs in the dead zone of DRV_A phase, and SRC short-circuit trigger conduction occurs in the dead zone of DRV_B phase;

[0051] (2) Conditional triggering moment: To facilitate control, PWM is triggered in the entire cycle. That is, the secondary side SR opening point is at SRB and SRC. After power failure, the triggering mechanism starts at the end of the cycle and the secondary side is turned on during the dead time of phase A in the next cycle.

[0052] During the HVDC bus voltage discharge process, the transformer's turns ratio and maximum LLC resonant network gain are fixed, which eventually causes the output voltage to drop. After the countermeasure is implemented (by turning on the SR drive during the primary-side dead band), the gain can be increased, temporarily pulling the output voltage back up, thereby extending the output hold time.

[0053] The circuit diagram of the three-phase LLC "Y" type interleaved full-wave rectifier resonant converter is as follows Figure 1 During normal operation, the three drive groups are 60° out of phase. Through asymmetric wave generation, the SR drive of QB3, QB6 (or QB4, QB5) on the secondary side is turned on to one of the LLC resonant networks on the primary side, such as DRV_B, DRV_C. When extended to a multi-interleaved circuit (six-interleaved), referring to the above working logic, the derivation relationship is as follows Table 1.1:

[0054] Table 1.1 Six-phase LLC interleaved drive and SR drive phase relationship

[0055]

[0056] from Figure 9 It can be seen in the figure that after using the three-phase LLC staggered phase control strategy, the three output voltages can be temporarily raised by 2.0V, which is converted to about 30Vdc on the primary side through the transformer turns ratio of 15:1. That is, the gain of the three-phase LLC converter is increased by 30V during this period, and the output voltage holding time is extended.

[0057] Although the embodiments of the present invention have been disclosed above, they are not limited to the applications listed in the description and the embodiments. They can be fully applied to various fields suitable for the present invention. For those familiar with the art, additional modifications can be easily implemented. Therefore, without departing from the general concept defined by the claims and the scope of equivalents, the present invention is not limited to the specific details and illustrations shown and described herein.

Claims

1. A method for improving power supply performance by using a multi-phase interleaved circuit, characterized in that: The following steps are involved: S1. Determine the circuit structure. The circuit is divided into a primary side and a secondary side. The primary side has multiple primary phases, and the secondary side has multiple secondary phases. The primary phases and secondary phases correspond one to one. The dead zone interval of each phase has a fixed phase difference, and the dead zone time of each primary phase is determined. S2, monitor the input voltage or output voltage to determine whether the power is off; S3. When power is off, the dead time of a certain primary phase causes a secondary phase that does not correspond to it to be turned on.

2. The method for improving power supply performance using a multi-phase interleaved circuit according to claim 1, wherein: The primary phase is LLC half-bridge, and the secondary phase is full-bridge rectifier.

3. The method for improving power supply performance using a multi-phase interleaved circuit according to claim 1, wherein: The number of the primary phases is 3-6.

4. The method for improving power supply performance using a multi-phase interleaved circuit according to claim 1, wherein: The number of primary phases is 3, which are defined as phase A, phase B and phase C according to the phase sequence. When power is off, the secondary phase corresponding to phase B is turned on during the dead time of phase A, or the secondary phase corresponding to phase C is turned on during the dead time of phase B.

5. The method for improving power supply performance using a multi-phase interleaved circuit according to claim 1, wherein: When the circuit is powered off, the conduction time is T phaseshift , T setting.max is the maximum pulse width, T seting.min is the minimum pulse width, V error is the output voltage feedback error, V error.max is the maximum value of the output voltage feedback error, V error =(V fb -V ref )*K p *K i , V fb is the output voltage, V ref is the output voltage reference value, K p , K i is the loop operation coefficient.

6. The method for improving power supply performance using a multi-phase interleaved circuit according to claim 5, characterized in that: The T seting.min 50ns, T setting.max is the corresponding dead time of the primary, V error.max When the voltage is 5%, the circuit performs voltage loop control.

7. The method for improving power supply performance using a multi-phase interleaved circuit according to claim 1, wherein: In step S2, when the input voltage is less than the set value Vac_out, the circuit is determined to be powered off; when the output voltage drops by more than 5%, the circuit is determined to be powered off.

8. The method for improving power supply performance using a multi-phase interleaved circuit according to claim 1, wherein: In step S3, when power is off, the circuit switching frequency is first reduced, and when the switching frequency drops to Tfp, the secondary phase is turned on.

9. The method for improving power supply performance by using a multi-phase interleaved circuit according to claim 8, characterized in that: The Tfp=Fswmin=Frmin+10kHz, where Frmin is the lowest resonant frequency of the primary phase.

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