Bottom pinning SOT-MRAM bit structure and preparation method thereof
By forming a hard mask pattern on the SOT track layer material of SOT-MRAM as a mask for etching, the problem of too small MTJ etching window in traditional SOT-MRAM preparation is solved, and a larger process window and higher preparation accuracy are achieved.
Patent Information
- Application Number
- CN202311317739.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-10
- Publication Date
- 2025-04-11
AI Technical Summary
In the preparation of traditional SOT-MRAM, the MTJ etching window is too small and difficult to accurately control, resulting in increased process difficulty.
A bottom pinning structure is used to form a structure with a hard mask pattern on the SOT track layer material, a conductive wire layer/space dielectric layer/conductive wire layer, and etched as a mask to form a magnetic tunnel junction and a SOT track layer.
The process window for MTJ etching has been expanded, the flexibility and accuracy of the preparation process has been improved, and the process difficulty has been reduced.
Smart Images
Figure CN119816191A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of memory technology, and in particular to a bottom pinned SOT-MRAM bit structure and a preparation method thereof. Background Art
[0002] Spin-Orbit-Torque Magnetic Random Access Memory (SOT-MRAM) uses the spin current generated by the spin-orbit torque effect to drive the flipping of the free layer as a way to write information. Its characteristics are that it adopts a three-terminal magnetic tunnel junction (MTJ) structure, separates read and write, and has a faster write speed and a higher number of erasable times.
[0003] In traditional SOT-MRAM preparation, MTJ uses a top pinning (TP) structure. MTJ etching stops on the SOT track layer, which is difficult to control accurately. The MTJ etching window is too small, and the SOT-MRAM preparation process is more difficult. Therefore, it is necessary to improve the structure and preparation process of SOT-MRAM. Summary of the invention
[0004] In view of this, the present invention provides a bottom pinned SOT-MRAM bit structure and a preparation method thereof, which has a larger process window.
[0005] In a first aspect, the present invention provides a method for preparing a bottom pinned SOT-MRAM bit structure, comprising:
[0006] Depositing a plurality of thin film materials and a layer of SOT track layer material in sequence on the bottom interconnect structure, wherein the plurality of thin film materials include a pinned layer film, a reference layer film, a barrier layer film and a free layer film stacked from bottom to top;
[0007] Forming a hard mask pattern on the SOT track layer material, wherein the hard mask pattern is a structure of a conductive line layer / spacer dielectric layer / conductive line layer;
[0008] Using the hard mask pattern as a mask, etching the SOT track layer material and the multilayer thin film material to form a magnetic tunnel junction and a SOT track layer;
[0009] depositing a protective layer material;
[0010] Depositing a dielectric and performing chemical mechanical polishing until the hard mask pattern is exposed;
[0011] A top interconnect structure is formed.
[0012] Optionally, a hard mask pattern is formed on the SOT track layer material, and the hard mask pattern is a structure of a conductive line layer / spacer dielectric layer / conductive line layer, including:
[0013] forming a sacrificial layer on the SOT track layer material;
[0014] patterning the sacrificial layer to form grooves on the sacrificial layer;
[0015] Depositing a layer of conductive material, wherein the conductive material covers the sidewalls and the bottom of the trench;
[0016] Etching the conductive material to retain the conductive material located on the sidewall of the trench;
[0017] Depositing a dielectric and performing chemical mechanical polishing to form a surface structure having a cross section of sacrificial layer / conductive material / dielectric / conductive material / sacrificial layer;
[0018] The surface structure is patterned to retain the conductive material / medium / conductive material as a conductive line layer / spacer dielectric layer / conductive line layer in sequence to form the hard mask pattern.
[0019] Optionally, a hard mask pattern is formed on the SOT track layer material, and the hard mask pattern is a structure of a conductive line layer / spacer dielectric layer / conductive line layer, including:
[0020] Forming a long strip of photoresist layer on the SOT track layer material;
[0021] forming two sidewall dielectric layers on the sidewalls of the photoresist layer, and then removing the photoresist layer;
[0022] Depositing a layer of conductive material, the conductive material covers the sidewalls of the spacer dielectric layer and the surface of the SOT track layer material;
[0023] Etching the conductive material to retain the conductive material located on the side walls of the two sidewall dielectric layers;
[0024] Depositing a dielectric and performing chemical mechanical polishing to form a surface structure with a cross section of dielectric / conductive material / sidewall dielectric layer / conductive material / dielectric / conductive material / sidewall dielectric layer / conductive material / dielectric;
[0025] The surface structure is patterned, and the innermost conductive material / medium / conductive material is retained as a conductive line layer / spacer dielectric layer / conductive line layer in sequence to form the hard mask pattern.
[0026] Optionally, etching the conductive material includes:
[0027] The conductive material is etched using a reactive ion etching process.
[0028] Optionally, the conductive material is any one of Ta, TaN, Ti and TiN.
[0029] Optionally, the protective layer material is SiN or SiO2.
[0030] In a second aspect, the present invention provides a bottom pinned SOT-MRAM bit structure, comprising:
[0031] a bottom interconnect structure;
[0032] A magnetic tunnel junction located on the bottom interconnect structure, wherein the magnetic tunnel junction is a bottom pinned structure, including a pinned layer, a reference layer, a barrier layer and a free layer stacked from bottom to top;
[0033] A SOT track layer located on the magnetic tunnel junction;
[0034] Two conductive wire layers located at both ends of the SOT track layer;
[0035] A spacing dielectric layer located between the two conductive line layers;
[0036] Two top electrodes are located above the two conductive line layers and extend outwards in a horizontal direction respectively, and each of the two top electrodes is electrically connected to the SOT track layer through one of the conductive line layers.
[0037] Optionally, the material of the conductive line layer is any one of Ta, TaN, Ti and TiN.
[0038] Optionally, the magnetic tunnel junction and the SOT track layer are surrounded by a protection layer.
[0039] The bottom pinned SOT-MRAM bit structure and preparation method thereof provided by the present invention prepare a hard mask pattern before MTJ etching, and the hard mask pattern is a conductive wire layer / spacer dielectric layer / conductive wire layer structure, that is, the conductive wire layer structure at both ends of the SOT track layer is prepared before MTJ etching, and compared with preparing it after MTJ etching, there is a larger process window when preparing the conductive wire layer structure at both ends of the SOT track layer. And the present application is compatible with existing processes and is easy to implement. BRIEF DESCRIPTION OF THE DRAWINGS
[0040] Figures 1 to 9 A schematic diagram of a process flow of a method for preparing a bottom pinned SOT-MRAM bit structure according to an embodiment of the present invention;
[0041] Figures 10 to 20 FIG. 4 is a schematic diagram of a process flow of a method for preparing a bottom pinned SOT-MRAM bit structure according to an embodiment of the present invention. DETAILED DESCRIPTION
[0042] In order to make the purpose, technical scheme and advantages of the embodiments of the present invention clearer, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention, but it should be understood that these descriptions are only exemplary and are not intended to limit the scope of the present disclosure. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. In addition, in the following description, the description of well-known structures and technologies is omitted to avoid unnecessary confusion of the concepts of the present disclosure.
[0043] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may further design regions / layers with different shapes, sizes, and relative positions according to actual needs.
[0044] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element or an intervening layer / element may exist therebetween. In addition, if a layer / element is "on" another layer / element in one orientation, the layer / element may be "below" the other layer / element when the orientation is reversed.
[0045] Some embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.
[0046] An embodiment of the present invention provides a method for preparing a bottom pinned SOT-MRAM bit structure, the method comprising the following steps:
[0047] S101, depositing a plurality of thin film materials and a layer of SOT track layer material in sequence on the bottom interconnect structure, wherein the plurality of thin film materials include a pinned layer film, a reference layer film, a barrier layer film and a free layer film stacked from bottom to top;
[0048] S102, forming a hard mask pattern on the SOT track layer material, wherein the hard mask pattern has a structure of a conductive line layer / spacer dielectric layer / conductive line layer;
[0049] S103, using the hard mask pattern as a mask, etching the SOT track layer material and the multilayer thin film material to form a magnetic tunnel junction and a SOT track layer;
[0050] S104, depositing a protective layer material;
[0051] S105, depositing a dielectric and performing chemical mechanical polishing until a hard mask pattern is exposed;
[0052] S106, forming a top interconnection structure.
[0053] As an implementation method, Figures 1 to 9 A structural schematic diagram of each step of a method for preparing a bottom pinned SOT-MRAM bit structure according to an embodiment is shown.
[0054] like Figure 1 As shown, first, a bottom interconnect structure 101 is formed. This step can be implemented using conventional processes. In this embodiment, the bottom interconnect structure 101 includes a bottom metal (BM) and a bottom via (BV). Then, a multilayer thin film material 102 and a layer of SOT track layer material 103 are sequentially deposited on the bottom interconnect structure 101, wherein the multilayer thin film material 102 is used to prepare a bottom pinned magnetic tunnel junction, and the multilayer thin film material 102 at least includes a pinned layer film, a reference layer film, a barrier layer film, and a free layer film stacked from bottom to top. The SOT track layer material 103 uses a heavy metal or topological material with a large spin Hall angle, which can be W, Ta, Pt, or BiSe, etc.
[0055] like Figure 2 As shown in (a), a sacrificial layer 104 is formed on the SOT track layer material 103, and the sacrificial layer 104 is patterned to form a groove on the sacrificial layer 104. Here, the size of the groove is larger than the size of the magnetic tunnel junction to be formed subsequently.
[0056] The function of the sacrificial layer 104 is to provide a mold of the hard mask pattern. Since the sacrificial layer 104 is completely etched away in the subsequent process, it is called a sacrificial layer. In this embodiment, the material of the sacrificial layer 104 can be a dielectric, such as SiN, SiO2, etc.
[0057] Figure 2 (b) shows that Figure 2 (a) is a top view of the cross-sectional structure shown.
[0058] like Figure 3 As shown, a layer of conductive material 105 is deposited to cover the sidewalls and bottom of the trench and the top of the remaining sacrificial layer 104 .
[0059] like Figure 4As shown in (a), the conductive material 105 is etched, and the etching endpoint stops on the SOT track layer material 103. After etching, only the conductive material located on the side wall of the groove is retained to form a conductive side wall. In this embodiment, the conductive material 105 is etched by a reactive ion etching (RIE) process, so that the etching of the conductive material and the SOT track layer material has a certain selectivity, and the etching time is accurately controlled through the Endpoint mode, so that the SOT track layer material loss can be ensured to be less after etching.
[0060] Figure 4 (b) shows that Figure 4 (a) is a top view of the cross-sectional structure shown.
[0061] like Figure 5 As shown, a dielectric 106 is deposited and chemical mechanical polishing is performed to form a surface structure with a cross section of sacrificial layer 104 / conductive material 105 / dielectric 106 / conductive material 105 / sacrificial layer 104.
[0062] like Figure 6 As shown in (a), the surface structure is patterned, and the conductive material / medium / conductive material are retained as the conductive line layer 1051 / spacer dielectric layer 1061 / conductive line layer 1052 in sequence to form a hard mask pattern. The patterning process includes photolithography and etching. During this etching process, part of the conductive material may also be etched.
[0063] Figure 6 (b) shows that Figure 6 (a) is a top view of the cross-sectional structure shown in FIG. 1 , where the preparation of a magnetic tunnel junction with a circular cross-sectional shape is used as an example for illustrative explanation, and therefore the cross-sectional shape of the hard mask pattern is circular.
[0064] After the above Figures 2 to 6 In the step of forming a hard mask pattern on the SOT track layer material 103, the hard mask pattern is a structure of a conductive line layer 1051 / spacer dielectric layer 1061 / conductive line layer 1052.
[0065] Then, if Figure 7 As shown, the SOT track layer material 103 and the multilayer thin film material 102 are etched using the hard mask pattern as a mask to form a magnetic tunnel junction 1021 and a SOT track layer 1031. After etching, a protective layer material 107 is deposited. In this embodiment, the protective layer material 107 is a dielectric layer, such as SiN, SiO2, etc.
[0066] like Figure 8 As shown, the dielectric is deposited continuously, and SiO2 is generally selected as the dielectric, and chemical mechanical polishing is performed until the hard mask pattern is exposed. The thickness of the hard mask pattern after polishing is 5-40nm, preferably 5-20nm.
[0067] like Fig. 9 As shown, a top interconnection structure 108 is formed. Since the SOT-MRAM bit structure is a three-terminal device, the top interconnection structure 108 includes two top electrodes 1081 and 1082 and their respective corresponding top through vias (TV).
[0068] The method for preparing the bottom pinned SOT-MRAM bit structure provided by the embodiment of the present invention prepares a hard mask pattern before MTJ etching, and the hard mask pattern is a conductive line layer / spacer dielectric layer / conductive line layer structure, that is, the conductive line layer structure at both ends of the SOT track layer is prepared before MTJ etching, which has a larger process window than preparing it after MTJ etching. In addition, the present application is compatible with existing processes and is easy to implement.
[0069] As an implementation method, Figures 10 to 20 A structural schematic diagram of each step of a method for preparing a bottom pinned SOT-MRAM bit structure according to another embodiment is shown.
[0070] like Fig.10 As shown, first, a bottom interconnect structure 201 is formed. This step can be implemented using conventional processes. In this embodiment, the bottom interconnect structure 201 includes a bottom metal (BM) and a bottom via (BV). Then, a multilayer thin film material 202 and a layer of SOT track layer material 203 are sequentially deposited on the bottom interconnect structure 201, wherein the multilayer thin film material 202 is used to prepare a bottom pinned magnetic tunnel junction, and the multilayer thin film material 202 at least includes a pinned layer film, a reference layer film, a barrier layer film, and a free layer film stacked from bottom to top. The SOT track layer material 203 uses a heavy metal or topological material with a large spin Hall angle, which can be W, Ta, Pt, or BiSe, etc.
[0071] like Fig.11 As shown in (a), a long strip photoresist layer 200 is formed on the SOT track layer material 203, where the size of the photoresist layer 200 is larger than the size of the magnetic tunnel junction formed subsequently. This step is formed by one-time photolithography, including coating, exposure and development.
[0072] Fig.11 (b) shows that Fig.11 (a) is a top view of the cross-sectional structure shown.
[0073] Then, two sidewall dielectric layers 2041 and 2042 are formed on the sidewalls of the photoresist layer 200. One implementation method is as follows: Fig.12 As shown, a dielectric layer 204 is deposited to cover the sidewalls and surface of the photoresist layer 200, and then Fig.13As shown, the dielectric 204 is etched to remove the dielectric in the horizontal direction, leaving only the dielectric in the vertical direction of the sidewall of the photoresist layer, thereby obtaining two sidewall dielectric layers 2041 and 2042. Then the photoresist layer 200 is removed.
[0074] Then, if Fig.14 As shown, a layer of conductive material 205 is deposited to cover the sidewalls of the spacer dielectric layers 2041 and 2042 and the surface of the SOT track layer material 203 .
[0075] like Fig.15 As shown in (a), the conductive material 205 is etched, and the etching endpoint stops on the SOT track layer material 203. After etching, only the conductive material located on the left and right side walls of the two sidewall dielectric layers 2041 and 2042 is retained to form a conductive sidewall. In this embodiment, the conductive material 105 is etched by a reactive ion etching (RIE) process, so that the etching of the conductive material and the SOT track layer material has a certain selectivity, and the etching time is accurately controlled through the Endpoint mode, so that the SOT track layer material loss can be ensured to be small after etching.
[0076] Fig.15 (b) shows that Fig.15 (a) is a top view of the cross-sectional structure shown.
[0077] like Fig.16 As shown, dielectric 206 is deposited and chemical mechanical polishing is performed to form a surface structure with a cross section of dielectric 206 / conductive material 205 / sidewall dielectric layer 2041 / conductive material 205 / dielectric 206 / conductive material 205 / sidewall dielectric layer 2042 / conductive material 205 / dielectric 206.
[0078] like Fig.17 As shown in (a), the surface structure is patterned, and the innermost conductive material / medium / conductive material is retained as the conductive line layer 2051 / spacer dielectric layer 2061 / conductive line layer 2052 in sequence to form a hard mask pattern. The patterning process includes photolithography and etching. During this etching process, part of the conductive material may also be etched.
[0079] Fig.17 (b) shows that Fig.17 (a) is a top view of the cross-sectional structure shown in FIG. 1 , where the preparation of a magnetic tunnel junction with a circular cross-sectional shape is used as an example for illustrative explanation, and therefore the cross-sectional shape of the hard mask pattern is circular.
[0080] After the above Figures 11 to 17In the step of forming a hard mask pattern on the SOT track layer material 203, the hard mask pattern is a structure of a conductive line layer 2051 / spacer dielectric layer 2061 / conductive line layer 2052.
[0081] Then, if Fig.18 As shown, the SOT track layer material 203 and the multilayer thin film material 202 are etched using the hard mask pattern as a mask to form a magnetic tunnel junction 2021 and a SOT track layer 2031. After etching, a protective layer material 207 is deposited. In this embodiment, the protective layer material 207 is a dielectric layer, such as SiN, SiO2, etc.
[0082] like Fig.19 As shown, the dielectric is deposited continuously, and SiO2 is generally selected as the dielectric, and chemical mechanical polishing is performed until the hard mask pattern is exposed. The thickness of the hard mask pattern after polishing is 5-40nm, preferably 5-20nm.
[0083] like Fig. 20 As shown, a top interconnect structure 208 is formed. Since the SOT-MRAM bit structure is a three-terminal device, the top interconnect structure 208 includes two top electrodes 2081 and 2082 and their respective corresponding top through vias (TV).
[0084] The method for preparing the bottom pinned SOT-MRAM bit structure provided by the embodiment of the present invention prepares a hard mask pattern before MTJ etching, and the hard mask pattern is a conductive line layer / spacer dielectric layer / conductive line layer structure, that is, the conductive line layer structure at both ends of the SOT track layer is prepared before MTJ etching, which has a larger process window than preparing it after MTJ etching. In addition, the present application is compatible with existing processes and is easy to implement.
[0085] On the other hand, an embodiment of the present invention provides a bottom pinned SOT-MRAM bit structure, which can be referred to Fig. 9 or Fig. 20 , here with Fig. 9 The bottom pinned SOT-MRAM bit structure shown is used as an example for explanation.
[0086] The bottom pinned SOT-MRAM bit structure of this embodiment includes:
[0087] A bottom interconnect structure 101;
[0088] A magnetic tunnel junction 1021 located on the bottom interconnect structure 101, wherein the magnetic tunnel junction 1021 is a bottom pinned structure, including a pinned layer, a reference layer, a barrier layer, and a free layer stacked from bottom to top;
[0089] A SOT track layer 1031 located on the magnetic tunnel junction 1021;
[0090] Two conductive line layers 1051 and 1052 located at two ends of the SOT track layer 1031;
[0091] A spacing dielectric layer 1061 located between the two conductive line layers 1051 and 1052;
[0092] Two top electrodes 1081 and 1082 are located above the two conductive wire layers 1051 and 1052 and extend outward in the horizontal direction respectively. The top electrode 1081 is electrically connected to the SOT track layer 1031 through the conductive wire layer 1051 , and the top electrode 1082 is electrically connected to the SOT track layer 1031 through the conductive wire layer 1052 .
[0093] Furthermore, the material of the conductive wire layers 1051 and 1052 may be any one of Ta, TaN, Ti and TiN. The material of the spacing dielectric layer 1061 may be SiN, SiO2 or the like.
[0094] In addition, the magnetic tunnel junction 1021 and the SOT track layer 1031 are surrounded by a protection layer 107 .
[0095] The bottom pinned SOT-MRAM bit structure provided by the embodiment of the present invention realizes the electrical connection between the top electrode and the SOT track layer through the conductive wire layers at both ends of the SOT track layer, has a large preparation process window, and has more superior electrical properties.
[0096] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.
[0097] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.
Claims
1. A method for preparing a bottom pinned SOT-MRAM bit structure, characterized in that: include: Depositing a plurality of thin film materials and a layer of SOT track layer material in sequence on the bottom interconnect structure, wherein the plurality of thin film materials include a pinned layer film, a reference layer film, a barrier layer film and a free layer film stacked from bottom to top; Forming a hard mask pattern on the SOT track layer material, wherein the hard mask pattern is a structure of a conductive line layer / spacer dielectric layer / conductive line layer; Using the hard mask pattern as a mask, etching the SOT track layer material and the multilayer thin film material to form a magnetic tunnel junction and a SOT track layer; depositing a protective layer material; Depositing a dielectric and performing chemical mechanical polishing until the hard mask pattern is exposed; A top interconnect structure is formed.
2. The method according to claim 1, characterized in that: A hard mask pattern is formed on the SOT track layer material, and the hard mask pattern is a structure of a conductive line layer / spacer dielectric layer / conductive line layer, including: forming a sacrificial layer on the SOT track layer material; patterning the sacrificial layer to form grooves on the sacrificial layer; Depositing a layer of conductive material, wherein the conductive material covers the sidewalls and the bottom of the trench; Etching the conductive material to retain the conductive material located on the sidewall of the trench; Depositing a dielectric and performing chemical mechanical polishing to form a surface structure having a cross section of sacrificial layer / conductive material / dielectric / conductive material / sacrificial layer; The surface structure is patterned to retain the conductive material / medium / conductive material as a conductive line layer / spacer dielectric layer / conductive line layer in sequence to form the hard mask pattern.
3. The method according to claim 1, characterized in that: A hard mask pattern is formed on the SOT track layer material, and the hard mask pattern is a structure of a conductive line layer / spacer dielectric layer / conductive line layer, including: Forming a long strip of photoresist layer on the SOT track layer material; forming two sidewall dielectric layers on the sidewalls of the photoresist layer, and then removing the photoresist layer; Depositing a layer of conductive material, the conductive material covers the sidewalls of the spacer dielectric layer and the surface of the SOT track layer material; Etching the conductive material to retain the conductive material located on the side walls of the two sidewall dielectric layers; Depositing a dielectric and performing chemical mechanical polishing to form a surface structure with a cross section of dielectric / conductive material / sidewall dielectric layer / conductive material / dielectric / conductive material / sidewall dielectric layer / conductive material / dielectric; The surface structure is patterned, and the innermost conductive material / medium / conductive material is retained as a conductive line layer / spacer dielectric layer / conductive line layer in sequence to form the hard mask pattern.
4. The method according to claim 2 or 3, characterized in that: The etching of the conductive material comprises: The conductive material is etched using a reactive ion etching process.
5. The method according to claim 2 or 3, characterized in that: The conductive material is any one of Ta, TaN, Ti and TiN.
6. The method according to claim 1, characterized in that The protective layer material is SiN or SiO2.
7. A bottom pinned SOT-MRAM bit structure, characterized in that: include: a bottom interconnect structure; A magnetic tunnel junction located on the bottom interconnect structure, wherein the magnetic tunnel junction is a bottom pinned structure, including a pinned layer, a reference layer, a barrier layer and a free layer stacked from bottom to top; A SOT track layer located on the magnetic tunnel junction; Two conductive wire layers located at both ends of the SOT track layer; A spacing dielectric layer located between the two conductive line layers; Two top electrodes are located above the two conductive line layers and extend outwards in a horizontal direction respectively, and each of the two top electrodes is electrically connected to the SOT track layer through one of the conductive line layers.
8. The bottom pinned SOT-MRAM bit structure according to claim 7, wherein: The material of the conductive line layer is any one of Ta, TaN, Ti and TiN.
9. The bottom pinned SOT-MRAM bit structure according to claim 7, wherein: The magnetic tunnel junction and the SOT track layer are surrounded by a protection layer.