Chip, packaging method thereof and electronic equipment
By designing alternately stacked metal pattern layers and dielectric layers interconnection layers in the chip package, the problem of large signal return loss in the chip package is solved, and signal integrity is improved.
Patent Information
- Application Number
- CN202411975340.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-30
- Publication Date
- 2025-04-15
AI Technical Summary
In chip package, the diameter of the core layer drilling hole is large, resulting in impedance mismatch in the signal transmission path, resulting in large return loss, seriously affecting signal integrity.
A chip is designed that includes dies, support plates and interconnection layers. The interconnection layer consists of alternately stacked metal pattern layers and dielectric layers. The opening of the cavity exposes the metal pattern layer. The metal pattern layer is coupled with the grains, and the grains are fixed to the cavity surface through the bonding layer to form an effective signal transmission path.
By improving the impedance consistency of the signal transmission path, the return loss of the signal is effectively reduced and signal integrity is improved.
Smart Images
Figure CN119833505A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuit packaging, and in particular to a chip and a packaging method thereof, and electronic equipment. Background Art
[0002] As the performance of chips such as CPU (central processing unit) and GPU (graphics processing unit) continues to improve, signal transmission rates are also getting faster and faster. As a result, chip packaging faces huge challenges and needs to achieve high-speed signal interconnection in a limited space.
[0003] In the related art, the chip packaging substrate is mostly supported by the core layer, and stacking layers are formed on both sides of the core layer for signal transmission. The signal on one side of the core layer needs to be transmitted to the other side of the core layer through the drilled holes in the core layer. Due to the large diameter of the drilled holes in the core layer, there will be impedance mismatch in the signal transmission path, resulting in a large return loss of the signal, which seriously affects the signal integrity. Summary of the invention
[0004] In view of this, an embodiment of the present invention provides a chip and a packaging method thereof, and an electronic device, which can effectively reduce the return loss of the signal and improve the signal integrity.
[0005] In the first aspect, an embodiment of the present invention provides a chip, comprising a crystal grain and a support plate and an interconnection layer arranged in sequence; a cavity for accommodating the crystal grain is arranged on the support plate, and the opening direction of the cavity is toward the interconnection layer; the interconnection layer comprises alternately stacked metal pattern layers and dielectric layers, wherein the opening of the cavity exposes the metal pattern layer, and the exposed metal pattern layer couples the crystal grain; the chip also comprises an adhesive layer arranged on the surface of the cavity, and the adhesive layer is used to fix the crystal grain to the surface of the cavity.
[0006] In one embodiment, the die includes a first surface and a second surface, the first surface is opposite to the second surface; the first surface is coupled to the interconnect layer, and the second surface is against the bottom of the cavity.
[0007] In one embodiment, a heat conducting layer is disposed on the second surface of the die.
[0008] In one embodiment, the metal pattern layer includes a first metal pattern layer, the first metal pattern layer is located on the surface of the support plate, the first metal pattern layer includes a plurality of first metal contacts, and the opening of the cavity exposes the plurality of first metal contacts.
[0009] In one embodiment, the first metal pattern layer further includes a metal pattern portion, wherein a width of the metal pattern portion is greater than a width of the first metal contact.
[0010] In one embodiment, the first metal contact comprises a metal bump.
[0011] In one embodiment, the metal pattern layer includes a last metal pattern layer, the last metal pattern layer is located on a surface of a dielectric layer away from the first metal pattern layer; the last metal pattern layer includes a plurality of second metal contacts.
[0012] In one embodiment, the second metal contact comprises a pad.
[0013] In one embodiment, each of the dielectric layers includes a conductive via, and different metal pattern layers are coupled through the corresponding conductive via.
[0014] In one embodiment, the number of the cavities is at least two; the chip further includes a packaging substrate, and the interconnect layer serves as an intermediate layer between the die and the packaging substrate, and is coupled to the die and the packaging substrate respectively.
[0015] In a second aspect, an embodiment of the present invention further provides an electronic device, characterized in that it comprises a printed circuit board and any chip provided by the embodiments of the present invention, wherein the chip is arranged on the printed circuit board.
[0016] In a third aspect, an embodiment of the present invention further provides a chip packaging method, comprising: providing a support plate; forming an opening on the support plate; fixing a crystal grain in the opening; setting an interconnection layer on the support plate, wherein the opening is directed toward the interconnection layer, wherein the interconnection layer comprises alternately stacked metal pattern layers and dielectric layers, the opening exposes the metal pattern layer, and the exposed metal pattern layer is coupled to the crystal grain.
[0017] In one embodiment, fixing the die in the opening includes: placing the die in the opening so that the first surface of the die faces the opening and the second surface of the die abuts against the bottom of the opening; and forming an adhesive layer in the opening to fix the die to the opening through the adhesive layer.
[0018] In one embodiment, before placing the die in the opening, the method further includes: providing a heat conducting layer on the second surface of the die.
[0019] In one embodiment, after placing the die in the opening and before forming an adhesive layer in the opening, the method further includes: providing a die metal bump on a pad of the die.
[0020] In one embodiment, the bonding pad of the die is located in the opening, and the top of the metal bump of the die protrudes from the opening or is flush with the opening.
[0021] In one embodiment, after forming the adhesive layer in the opening and before setting the interconnection layer on the support plate, the method further includes: polishing the adhesive layer so that the adhesive layer and the grain metal bump are flush with the opening and the grain metal bump is exposed from the adhesive layer.
[0022] In one embodiment, providing an interconnection layer on the support plate includes: forming the interconnection layer on the support plate, the grain metal bumps and the adhesive layer, wherein the interconnection layer is electrically connected to the grain metal bumps.
[0023] In one embodiment, forming the interconnect layer on the support plate, the grain metal bumps and the adhesive layer includes: forming the metal pattern layers and the dielectric layers stacked alternately on the support plate, the grain metal bumps and the adhesive layer.
[0024] In one embodiment, forming the metal pattern layer includes: forming a first metal pattern layer on the support plate, the grain metal bump and the adhesive layer, wherein the first metal pattern layer includes a plurality of first metal contacts, and the opening exposes the plurality of first metal contacts.
[0025] In one embodiment, the support plate includes a glass plate or a ceramic plate; before forming the first layer of metal pattern layer on the support plate, the grain metal bumps and the adhesive layer, the method also includes: forming an adhesion layer on the support plate; forming the first layer of metal pattern layer on the adhesion layer, the grain metal bumps and the adhesive layer.
[0026] In one embodiment, the metal pattern layer of the first layer formed on the support plate, the grain metal bump and the adhesive layer includes: forming a first metal layer on the support plate, the grain metal bump and the adhesive layer; patterning a portion of the first metal layer to form a metal pattern portion of the metal pattern layer of the first layer; patterning the remaining portion of the first metal layer to form the multiple first metal contacts, each of the first metal contacts is electrically connected to the corresponding grain metal bump, wherein the width of the metal pattern portion is greater than the width of the first metal contact.
[0027] In one embodiment, forming the metal pattern layer further comprises: forming a final metal pattern layer on a dielectric layer away from the first metal pattern layer, wherein the final metal pattern layer comprises a plurality of second metal contacts.
[0028] In one embodiment, the method further includes: performing surface treatment on the second metal contact to form an anti-oxidation layer on the surface of the second metal contact.
[0029] In one embodiment, forming the dielectric layer includes: providing a dielectric material layer and providing through-holes on the dielectric material layer; filling the through-holes with metal to form conductive vias to obtain the dielectric layer, wherein the conductive vias are used to couple two adjacent metal pattern layers.
[0030] In one embodiment, the number of the openings is at least two; after the interconnection layer is set on the support plate, the method further includes: providing a packaging substrate; coupling the surface of the interconnection layer away from the support plate with the packaging substrate so that the interconnection layer becomes an intermediate layer between the grain and the packaging substrate. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0032] Figure 1 A schematic diagram of the structure of a chip provided by an embodiment of the present invention; Figure 2 Another schematic diagram of the structure of a chip provided by an embodiment of the present invention; Figure 3 Another schematic diagram of the structure of a chip provided by an embodiment of the present invention; Figure 4 A schematic diagram of another structure of a chip provided by an embodiment of the present invention; Figure 5 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention; Figure 6 A flow chart of a chip packaging method provided by an embodiment of the present invention; Figure 7 for Figure 6 A process flow chart corresponding to the embodiment shown; Figure 8A schematic diagram of a positional relationship between a grain metal bump and an opening in an embodiment of the present invention; Fig. 9 A schematic diagram of another positional relationship between a grain metal bump and an opening in an embodiment of the present invention; Fig.10 A process flow chart of a method for manufacturing a metal pattern layer in an interconnect layer in an embodiment of the present invention; Fig.11 A process flow chart of a method for manufacturing a dielectric layer in an interconnect layer in an embodiment of the present invention; Fig.12 The present invention is a process flow chart of filling metal in a through hole and setting a next metal layer in an embodiment of the present invention. DETAILED DESCRIPTION
[0033] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0034] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0035] The embodiment of the present invention provides a chip that can effectively reduce the return loss of a signal and improve signal integrity.
[0036] like Figure 1 As shown, the chip 4 provided by the embodiment of the present invention may include a crystal grain 101 and a support plate 116 and an interconnection layer 103 arranged in sequence; a cavity 120 for accommodating the crystal grain 101 is arranged on the support plate 116, and the opening direction of the cavity 120 is toward the interconnection layer 103; the interconnection layer 103 includes alternately stacked metal pattern layers 114 and dielectric layers 110, wherein the opening of the cavity 120 exposes the metal pattern layer 114, and the exposed metal pattern layer 114 is coupled to the crystal grain 101; the chip 4 may also include an adhesive layer 122 arranged on the surface of the cavity 120, and the adhesive layer 122 is used to fix the crystal grain 101 to the surface of the cavity 120.
[0037] The chip 4 provided by the embodiment of the present invention has a cavity 120 for accommodating a crystal grain 101 on its support plate 116, and the crystal grain 101 is fixed on the surface of the cavity 120 by an adhesive layer 122, so as to be supported by the support plate 116. The opening direction of the cavity 120 faces the interconnection layer 103; the interconnection layer 103 includes an alternately stacked metal pattern layer 114 and a dielectric layer 110, and the opening of the cavity 120 exposes the metal pattern layer 114, and the exposed metal pattern layer 114 couples the crystal grain 101, so that the signal in the crystal grain 101 can enter the interconnection layer 103, and the signal transmission is realized through the metal pattern layer 114 separated by the dielectric layer 110 in the interconnection layer 103. There is no core layer in the entire chip 4, and there is no situation where the signal is transmitted from one side of the core layer to the other side of the core layer. Therefore, it can greatly improve the consistency of impedance in the signal transmission line, effectively reduce the return loss of the signal, and improve the signal integrity.
[0038] In the embodiment of the present invention, the support plate 116 mainly supports the interconnection layer 103 and does not participate in signal transmission. Therefore, any plate whose hardness and strength meet the support requirements can be used as the support plate 116. Exemplarily, in one embodiment of the present invention, the support plate 116 can include any of the following: a resin plate, a glass plate, and a ceramic plate.
[0039] In one embodiment of the present invention, a cavity 120 may be provided on the support plate 116, and the specific position of the cavity 120 on the support plate 116 is not limited, as long as it does not affect the supporting effect of the support plate 116 on the interconnection layer 103. For example, in one example, the cavity 120 may be located in the center of the support plate 116.
[0040] The shape and size of the cavity 120 can be adapted to the shape and size of the grain 101 so as to place and accommodate the corresponding grain 101. Adaptation means that after the grain 101 is placed in the corresponding cavity 120, the grain 101 can be coupled with the interconnection layer 103 without causing excessive waste of space. For example, in one example, the shape of the cavity 120 can be the same as that of the grain 101, and the size of the cavity 120 can be slightly larger than that of the grain 101, for example, the side length of the cavity 120 can be 1 mm to 2 mm longer than the corresponding side length of the grain 101.
[0041] In one embodiment of the present invention, the die 101 may be fixed to the inner wall of the cavity 120 by an adhesive layer 122, so that the die 101 may be stably combined with the support plate 116. The adhesive layer 122 may be formed by curing an adhesive, for example.
[0042] Furthermore, the number of cavities 120 in the support plate 116 may be different according to the number of die 101 to be packaged. For example, in one example, the number of cavities 120 may be one, and in another example, the number of cavities 120 may be two or more, wherein each cavity 120 is used to place and accommodate a corresponding die 101.
[0043] In one embodiment of the present invention, the die 101 may include a first surface and a second surface, the first surface being opposite to the second surface; wherein the first surface may be coupled to the interconnect layer 103 , and the second surface may be against the bottom of the cavity 120 .
[0044] Furthermore, if Figure 2 As shown, in another embodiment of the present invention, the second surface of the grain 101 may also be provided with a heat conducting layer 121, so that the heat generated during the operation of the grain 101 can be dissipated more quickly. The specific material of the heat conducting layer 121 is not limited, as long as it can accelerate the heat conduction between the grain 101 and the inner wall of the cavity 120. For example, in one example, the heat conducting layer 121 may include a graphene material or an indium material.
[0045] In an embodiment of the present invention, the interconnection layer 103 may include alternately stacked metal pattern layers 114 and dielectric layers 110. The metal pattern layers 114 may be used for signal transmission, and the dielectric layers 110 may be used for insulating and isolating different metal pattern layers 114.
[0046] In a specific implementation, the dielectric layer 110 may include various insulating materials. For example, in one example, the material of the dielectric layer 110 may include polyimide, and in another example, the material of the dielectric layer 110 may include ABF (Ajinomoto Build-up Film). The materials of the dielectric layers 110 may be the same or different, and the embodiments of the present invention are not limited thereto.
[0047] The number of metal pattern layers 114 may be multiple, and the specific structures of the metal pattern layers 114 may be different according to the different positions of the metal pattern layers 114 in the interconnection layer 103. Figure 3 As shown, in one embodiment of the present invention, the metal pattern layer 114 may include a first metal pattern layer 1141, the first metal pattern layer 1141 is located on the surface of the support plate 116, the first metal pattern layer 1141 includes a plurality of first metal contacts 21, and the opening of the cavity 120 exposes the plurality of first metal contacts 21. In a specific implementation, the specific form of the first metal contact 21 can be set and adjusted as needed, for example, in one example, the first metal contact 21 may include a metal bump.
[0048] In one embodiment, the metal pattern layer 1141 of the first layer may further include a metal pattern portion 23, wherein the width of the metal pattern portion 23 may be greater than the width of the first metal contact 21. The metal pattern portion 23 may be electrically connected to the first metal contact 21, or may not be electrically connected to the first metal contact 21, which is not limited in the embodiment of the present invention. In one embodiment, the metal pattern portion 23 may be located in an area of the metal pattern layer 1141 of the first layer that is not exposed by the opening 120.
[0049] See again Figure 3 In another embodiment of the present invention, in addition to the first metal pattern layer 1141, the metal pattern layer 114 may also include a last metal pattern layer 1142, and the last metal pattern layer 1142 is located on the surface of the dielectric layer 110 away from the first metal pattern layer 1141; the last metal pattern layer 1142 may include a plurality of second metal contacts 22, which are used to electrically connect the chip 4 to other components or devices, such as a mainboard. Exemplarily, in one example, the second metal contact 22 may include a pad.
[0050] Furthermore, in addition to the first metal pattern layer 1141 and the second metal pattern layer 1142, in one embodiment of the present invention, the metal pattern layer 114 may also include at least one metal wiring layer 1143, and the at least one metal wiring layer 1143 may be located between the first metal pattern layer 1141 and the second metal pattern layer 1142. The metal wiring layer 1143 may be used to redistribute the signal drawn from one crystal grain 101, or to interconnect two or more crystal grains 101, which is not limited in the embodiment of the present invention.
[0051] In one embodiment of the present invention, the metal pattern layers 114 such as the first metal pattern layer 1141, the second metal pattern layer 1142 and the metal wiring layer 1143 can be separated by different dielectric layers 110. Each dielectric layer 110 can include a conductive via 104, and different metal pattern layers 114 can be coupled through the corresponding conductive via 104.
[0052] In the above embodiment, the chip 4 mainly performs signal redistribution or inter-die interconnection through the interconnection layer 103, but the embodiments of the present invention are not limited thereto. In other embodiments of the present invention, the chip 4 may further include a packaging substrate, and further perform signal redistribution or inter-die interconnection through the packaging substrate, thereby realizing 2.5D packaging of the chip 4. For example, Figure 4As shown, in one embodiment of the present invention, the number of cavities 120 may be at least two; the chip 4 may further include a packaging substrate 3, and the interconnection layer 103 serves as an interposer between the die 101 and the packaging substrate 3, and is coupled to the die 101 and the packaging substrate 3 respectively. In this way, the interconnection layer 103 can serve as an interposer of 2.5D packaging, interconnecting a part of the signals between the die 101, and transmitting another part of the signals in the die 101 to the packaging substrate 3, and interconnecting or redistributing through the packaging substrate 3.
[0053] Accordingly, if Figure 5 As mentioned above, an embodiment of the present invention further provides an electronic device 5 , which may include a printed circuit board 51 and any chip 4 provided in the aforementioned embodiments, and the chip 4 is disposed on the printed circuit board 51 .
[0054] Since the electronic device 5 provided in the embodiment of the present invention includes any one of the chips 4 provided in the aforementioned embodiments, the corresponding beneficial technical effects can also be achieved, which have been described in detail above and will not be repeated here.
[0055] Corresponding to the aforementioned chip, an embodiment of the present invention further provides a chip packaging method. Figure 6 A flow chart of a chip packaging method provided by an embodiment of the present invention, Figure 7 for Figure 6 The corresponding process flow chart. Figure 6 and Figure 7 , the chip packaging method provided by the embodiment of the present invention may include: S61, providing a support plate 116; S62, forming an opening 120 on the support plate 116; S63, fixing the die 101 in the opening 120; S64, setting an interconnection layer 103 on the support plate 116, with the opening 120 facing the interconnection layer 103, wherein the interconnection layer 103 includes alternately stacked metal pattern layers 114 and dielectric layers 110, the opening 120 exposes the metal pattern layer 114, and the exposed metal pattern layer 114 is coupled to the grain 101.
[0056] The chip packaging method provided by the embodiment of the present invention can provide a support plate 116, form an opening 120 on the support plate 116, fix the crystal grain 101 in the opening 120, and set an interconnection layer 103 on the support plate 116, with the opening 120 facing the interconnection layer 103, wherein the interconnection layer 103 includes metal pattern layers 114 and dielectric layers 110 stacked alternately, and the opening 120 exposes the metal pattern layer 114, and the exposed metal pattern layer 114 is coupled with the crystal grain 101. In this way, the signal in the crystal grain 101 can enter the interconnection layer 103, and the signal transmission is realized through the metal pattern layer 114 separated by the dielectric layer 110 in the interconnection layer 103. There is no core layer in the entire chip 4, and there is no situation where the signal is transmitted from one side of the core layer to the other side of the core layer. Therefore, the impedance consistency in the signal transmission line can be greatly improved, the return loss of the signal can be effectively reduced, and the signal integrity can be improved.
[0057] In an embodiment of the present invention, the support plate 116 provided in step S61 mainly supports the interconnect layer 103 and does not participate in signal transmission. Therefore, any plate whose hardness and strength meet the support requirements can be used as the support plate 116. Exemplarily, in an embodiment of the present invention, the support plate 116 may include any of the following: a resin plate, a glass plate, or a ceramic plate.
[0058] After obtaining the support plate 116, an opening 120 can be formed on the support plate 116 in step S62. Depending on the specific material of the support plate 116, the method of forming the opening 120 may also be different. For example, in one example, the support plate 116 is an organic material such as resin, and the opening 120 can be formed on the support plate 116 by laser burning. Optionally, after laser burning, a chemical method can be further used to remove the remaining substances after burning. In another example, the support plate 116 is an inorganic material such as glass, and the opening 120 can be formed on the support plate 116 by laser induction and chemical etching. Here, laser induction can refer to breaking the chemical bonds in materials such as glass by irradiating laser, thereby making it easier to chemically react with the etching solution to form the opening 120.
[0059] Optionally, in the embodiment of the present invention, the specific position of the opening 120 on the support plate 116 is not limited, as long as it does not affect the supporting effect of the support plate 116 on the interconnection layer 103. For example, in one example, the opening 120 can be located in the center of the support plate 116.
[0060] The shape and size of the opening 120 can be adapted to the shape and size of the grain 101 so as to place and accommodate the corresponding grain. Adaptation means that after the grain is placed in the corresponding opening 120, it is convenient for the grain 101 to couple with the interconnection layer 103 without causing excessive waste of space. For example, in one example, the shape of the opening 120 can be the same as the shape of the grain, and the size of the opening 120 can be slightly larger than the grain 101, for example, the side length of the opening 120 can be 1 mm to 2 mm longer than the corresponding side length of the grain.
[0061] In a specific implementation, the number of openings 120 in the support plate 116 may be different depending on the number of die to be packaged. For example, in one example, the number of openings 120 may be one, and in another example, the number of openings 120 may be two or more, wherein each opening 120 is used to place and accommodate a corresponding die.
[0062] After the opening 120 is formed in the support plate 116, the die 101 may be fixed in the opening 120 in step S63. In a specific implementation, the die 101 may be placed in the opening 120 so that the first surface of the die 101 faces the opening 120, and the second surface of the die 101 abuts against the bottom of the opening 120, wherein the first surface of the die 101 is opposite to the second surface of the die 101; an adhesive layer 122 is formed in the opening 120 to fix the die 101 to the opening 120 through the adhesive layer 122. The specific material and composition of the adhesive layer are not limited, as long as the die 101 can be fixed in the opening 120. For example, in one example, the adhesive layer may be a resin.
[0063] Furthermore, in one embodiment of the present invention, before the die 101 is placed in the opening 120, a heat conducting layer 121 may be provided on the second surface of the die 101. Since the heat conducting layer 121 is provided on the second surface of the die 101, after the die 101 is placed in the opening 120, the second surface of the die 101 may abut against the inner wall of the opening 120, that is, the support plate 116, so that the heat generated by the die 101 during operation can be dissipated more quickly through the heat conducting layer 121 and the support plate 116.
[0064] In the embodiment of the present invention, the specific material of the heat conducting layer 121 is not limited, as long as it can accelerate the heat conduction between the die 101 and the inner wall of the opening 120. For example, in one example, the heat conducting layer 121 may include graphene material or indium material.
[0065] In one embodiment of the present invention, after placing the die 101 in the opening 120 and before forming the adhesive layer 122 in the opening 120, the chip packaging method provided by the embodiment of the present invention may further include: providing a die metal bump 1011 on the pad of the die 101. The die metal bump 1011 is a metal bump formed on the pad of the die 101, and can be used to electrically connect the die 101 to the interconnect layer 103.
[0066] like Figure 8 and Fig. 9 As shown, in one embodiment of the present invention, the pad of the die 101 may be located in the opening 120, and the die metal bump 1011 may be disposed on the pad of the die 101 by, for example, electroplating. The top of the die metal bump 1011 may protrude from the opening 120, or be flush with the opening 120. That is, when the die 101 is placed in the opening 120, the first surface of the die 101 is located in the opening 120, but the die metal bump 1011 formed on the pad of the die 101 may be flush with the opening 120 or protrude from the opening 120.
[0067] In one embodiment of the present invention, the adhesive layer 122 can be obtained by filling the adhesive into the opening 120 and curing it. Since the adhesive is fluid, it is possible to cover the grain metal bump 1011. For this reason, in one embodiment of the present invention, after the adhesive layer 122 is formed in the opening 120 and before the interconnection layer 103 is set on the support plate 116, the chip packaging method provided by the embodiment of the present invention may also include: polishing the adhesive layer 122 so that the adhesive layer 122 and the grain metal bump 1011 are flush with the opening 120, and the grain metal bump 1011 is exposed from the adhesive layer 122.
[0068] Based on this, step S64 of setting the interconnection layer 103 on the support plate 116 may specifically include: forming the interconnection layer 103 on the support plate 116, the grain metal bumps 1011 and the adhesive layer 122, wherein the interconnection layer 103 is electrically connected to the grain metal bumps 1011. Specifically, the metal pattern layers 114 and the dielectric layers 110 stacked alternately may be formed on the support plate 116, the grain metal bumps 1011 and the adhesive layer 122.
[0069] The formation of the metal pattern layer 114 and the dielectric layer 110 will be described in detail below.
[0070] First, the formation of the metal pattern layer 114 is described.
[0071] Specifically, in one embodiment of the present invention, forming the metal pattern layer 114 may include: forming a first metal pattern layer 1141 on the support plate 116, the grain metal bump 1011 and the adhesive layer 122, wherein the first metal pattern layer 1141 may include a plurality of first metal contacts 21, and the opening 120 exposes the plurality of first metal contacts 21.
[0072] In an embodiment of the present invention, the support plate 116 may include a resin plate, a glass plate, a ceramic plate, and the like. In one example, the support plate 116 is a glass plate or a ceramic plate; based on this, before forming the first metal pattern layer 1141 on the support plate 116, the grain metal bump 1011, and the adhesive layer 122, the chip packaging method provided by the embodiment of the present invention may also include: forming an adhesion layer on the support plate 116; forming the first metal pattern layer 1141 on the adhesion layer, the grain metal bump 1011, and the adhesive layer 122. In this way, the adhesion layer can greatly enhance the bonding strength between the first metal seed layer and the support plate 116 such as a glass plate and a ceramic plate. Optionally, the specific material of the adhesion layer is not limited, as long as it can enhance the adhesion strength between the first metal seed layer and the support plate 116. For example, in one embodiment, the adhesion layer may be a metal oxide, and in another embodiment, it may be a titanium alloy, etc.
[0073] Specifically, in one embodiment of the present invention, forming a first metal pattern layer 1141 on the support plate 116, the grain metal bump 1011 and the adhesive layer 122 may include: forming a first metal layer on the support plate 116, the grain metal bump 1011 and the adhesive layer 122; patterning a portion of the first metal layer to form a metal pattern portion 23 of the first metal pattern layer 1141; patterning the remaining portion of the first metal layer 1141 to form a plurality of first metal contacts 21, each first metal contact 21 being electrically connected to the corresponding grain metal bump 1011, wherein the width of the metal pattern portion 23 is greater than the width of the first metal contact 21.
[0074] Exemplarily, in one example, the metal pattern portion 23 may include a metal line or a metal plane. The metal pattern portion 23 may be electrically connected to the first metal contact 21, or may not be electrically connected to the first metal contact 21, and the embodiment of the present invention is not limited to this. In one embodiment, the metal pattern portion 23 may be located in an area of the first metal pattern layer 1141 that is not exposed by the opening 120.
[0075] It should be noted that, in the embodiment of the present invention, in terms of the manufacturing process, the first metal contact 21 and the metal pattern portion 23 may be formed simultaneously or successively, and the embodiment of the present invention is not limited thereto.
[0076] In addition to forming the first metal pattern layer 1141, in another embodiment of the present invention, forming the metal pattern layer 114 may further include: forming a last metal pattern layer 1142 on the dielectric layer 110 away from the first metal pattern layer 1141, and the last metal pattern layer 1142 may include a plurality of second metal contacts 22. In one embodiment, the second metal contacts 22 may be surface treated to form an anti-oxidation layer on the surface of the second metal contacts 22 to prevent them from being oxidized or damaged by stress. For example, the second metal contacts 22 may be surface treated by an electroless nickel-palladium immersion gold (ENEPIG) process.
[0077] The process flow of forming the metal pattern layer 114 is briefly introduced below.
[0078] In one embodiment, if Fig.10 As shown, the method for forming the metal pattern layer 114 may include: providing a metal layer 130 ; and etching the metal layer 130 to form a corresponding metal pattern layer 114 .
[0079] Specifically, in one embodiment of the present invention, providing the metal layer 130 may include depositing a first metal seed layer; and performing electroplating based on the first metal seed layer to obtain the metal layer 130. The first metal seed layer may be, for example, a thinner metal layer formed by chemical deposition or the like, and based on the first metal seed layer, a thicker metal layer may be formed by electroplating to obtain the metal layer 130. The metal layer 130 may include any conductive metal, for example, copper.
[0080] Specifically, in one embodiment of the present invention, etching the metal layer 130 to form the corresponding metal pattern layer 114 may include: setting a photosensitive material on the metal layer 130; exposing and developing the photosensitive material to obtain an etching mask; under the mask of the etching mask, etching the metal layer 130 to obtain the metal pattern layer 114; and then removing the etching mask, for example, the photolithography mask may be removed by a chemical method.
[0081] For example, in one example, when the photosensitive material is disposed on the metal layer 130, a photosensitive dry film may be laminated on the metal layer 130. In another example, when the photosensitive material is disposed on the metal layer 130, a photoresist may also be coated on the metal layer 130. The embodiments of the present invention are not limited to this.
[0082] The formation of the dielectric layer 110 is described below.
[0083] like Fig.11As shown, in one embodiment, the method for forming the dielectric layer 110 may include: setting a dielectric material layer 131 and setting a through hole 140 on the dielectric material layer 131; filling metal in the through hole 140 to form a conductive via 104 to obtain the dielectric layer 110, and the conductive via 104 is used to couple two adjacent metal pattern layers 114.
[0084] Specifically, in one embodiment of the present invention, providing the dielectric material layer 131 and providing the through-hole 140 on the dielectric material layer 131 may include: laminating the dielectric material layer 131; and providing the through-hole 140 on the dielectric material layer 131 by laser or chemical etching.
[0085] In an embodiment of the present invention, the laminated dielectric material layer 131 may include various dielectric materials, such as polyimide, ABF, etc. The size of the perforation 140 can be more accurately controlled by laser or chemical etching, so that the size of the perforation 140 is much smaller than that of mechanical drilling. In one embodiment, before laminating the dielectric material layer 131, the metal pattern layer 114 may be roughened so that the metal pattern layer 114 can be better connected to the dielectric material layer 131.
[0086] In one embodiment of the present invention, filling the through-hole 140 with metal to form the conductive via 104 may include: depositing a second metal seed layer on the inner wall of the through-hole 140; and electroplating based on the second metal seed layer to form the conductive via 104. The second metal seed layer may be, for example, a thinner layer of metal formed by chemical deposition or the like, and based on the second metal seed layer, a thicker layer of metal may be formed by electroplating to fill the through-hole 140 to form the conductive via 104. The metal filling the through-hole 140 may include any conductive metal, for example, may include metal copper.
[0087] Furthermore, since both filling the metal in the through hole 140 and forming the next metal layer 130 require the deposition of metal, in one embodiment, Fig.12 As shown, the step of filling metal in the through hole 140 to form the conductive via 104 and the step of forming the next metal layer 130 can be performed continuously.
[0088] In the embodiment of the present invention, the interconnection layer 103 may include alternately stacked metal pattern layers 114 and dielectric layers 110. There may be multiple metal pattern layers 114, and the specific structures of the metal pattern layers 114 may be different according to the different positions of the metal pattern layers 114 in the interconnection layer 103. Specifically, the metal material, metal thickness, mask pattern, etc. may be adjusted accordingly when forming each metal pattern layer 114.
[0089] In an embodiment of the present invention, the number of openings 120 formed on the support plate 116 is not limited, and can be one or more. Specifically, in an embodiment of the present invention, the number of openings 120 can be at least two; based on this, after the interconnection layer 103 is set on the support plate 116 in step S64, the chip packaging method provided by the embodiment of the present invention can also include: providing a packaging substrate 3; coupling the surface of the interconnection layer 103 away from the support plate 116 with the packaging substrate 3, so that the interconnection layer 103 becomes an intermediate layer between the die 101 and the packaging substrate 3, thereby realizing 2.5D packaging of the chip.
[0090] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.
[0091] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.
[0092] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims
1. A chip, characterized in that: It comprises a crystal grain, and a supporting plate and an interconnection layer which are arranged in sequence; the supporting plate is provided with a cavity for accommodating the crystal grain, and the opening direction of the cavity faces the interconnection layer; The interconnection layer includes metal pattern layers and dielectric layers that are alternately stacked, wherein the opening of the cavity exposes the metal pattern layer, and the exposed metal pattern layer is coupled to the grains; The chip further comprises an adhesive layer disposed on the surface of the cavity, and the adhesive layer is used for fixing the die to the surface of the cavity.
2. The chip according to claim 1, characterized in that: The die includes a first surface and a second surface, wherein the first surface is opposite to the second surface; the first surface is coupled to the interconnection layer, and the second surface is against the bottom of the cavity.
3. The chip according to claim 2, characterized in that: The second surface of the die is provided with a heat conducting layer.
4. The chip according to claim 1, characterized in that: The metal pattern layer includes a first metal pattern layer, the first metal pattern layer is located on the surface of the support plate, the first metal pattern layer includes a plurality of first metal contacts, and the opening of the cavity exposes the plurality of first metal contacts.
5. The chip according to claim 4, wherein: The first metal pattern layer further includes a metal pattern portion, wherein a width of the metal pattern portion is greater than a width of the first metal contact.
6. The chip according to claim 4, characterized in that: The first metal contact includes a metal bump.
7. The chip according to claim 4, characterized in that: The metal pattern layer includes a last metal pattern layer, and the last metal pattern layer is located on a surface of a dielectric layer away from the first metal pattern layer; the last metal pattern layer includes a plurality of second metal contacts.
8. The chip according to claim 7, characterized in that: The second metal contact includes a pad.
9. The chip according to any one of claims 1 to 8, characterized in that: Each of the dielectric layers includes a conductive via, and different metal pattern layers are coupled through the corresponding conductive via.
10. The chip according to any one of claims 1 to 8, characterized in that: The number of the cavities is at least two; the chip further includes a packaging substrate, and the interconnection layer serves as an intermediate layer between the crystal grain and the packaging substrate, and is coupled to the crystal grain and the packaging substrate respectively.
11. An electronic device, characterized in that: The invention comprises a printed circuit board and the chip according to any one of claims 1 to 10, wherein the chip is arranged on the printed circuit board.
12. A chip packaging method, characterized in that: include: Provide support plates; forming an opening on the support plate; securing a die in the opening; An interconnection layer is arranged on the support plate, and the opening is oriented toward the interconnection layer, wherein the interconnection layer includes metal pattern layers and dielectric layers stacked alternately, the opening exposes the metal pattern layer, and the exposed metal pattern layer is coupled with the grains.
13. The method according to claim 12, characterized in that The fixing of the die in the opening comprises: placing the die in the opening so that a first surface of the die faces the opening and a second surface of the die abuts against a bottom of the opening; An adhesive layer is formed in the opening to fix the die to the opening through the adhesive layer.
14. The method according to claim 13, characterized in that Before placing the die in the opening, the method further includes: A heat conducting layer is disposed on the second surface of the die.
15. The method according to claim 13, characterized in that After placing the die in the opening and before forming an adhesive layer in the opening, the method further includes: A crystal grain metal bump is disposed on the bonding pad of the crystal grain.
16. The method according to claim 15, characterized in that The bonding pad of the die is located in the opening, and the top of the metal bump of the die protrudes from the opening or is flush with the opening.
17. The method according to claim 15, characterized in that After forming the adhesive layer in the opening and before providing the interconnection layer on the support plate, the method further includes: The bonding layer is polished so that the bonding layer and the die metal bump are flush with the opening and the die metal bump is exposed from the bonding layer.
18. The method according to claim 15, characterized in that The provision of an interconnection layer on the support plate comprises: The interconnection layer is formed on the support plate, the grain metal bumps and the adhesive layer, wherein the interconnection layer is electrically connected to the grain metal bumps.
19. The method according to claim 18, characterized in that The forming of the interconnection layer on the support plate, the grain metal bumps and the adhesive layer comprises: The metal pattern layers and the dielectric layers are alternately stacked on the support plate, the grain metal bumps and the adhesive layer.
20. The method according to claim 19, characterized in that Forming the metal pattern layer includes: A first metal pattern layer is formed on the support plate, the grain metal bumps and the adhesive layer, wherein the first metal pattern layer includes a plurality of first metal contacts, and the opening exposes the plurality of first metal contacts.
21. The method according to claim 20, characterized in that The support plate includes a glass plate or a ceramic plate; Before forming the first metal pattern layer on the support plate, the grain metal bumps and the adhesive layer, the method further comprises: forming an adhesive layer on the support plate; The first metal pattern layer is formed on the adhesion layer, the grain metal bumps and the bonding layer.
22. The method according to claim 20, characterized in that The first metal pattern layer formed on the support plate, the grain metal bumps and the adhesive layer comprises: forming a first metal layer on the support plate, the grain metal bumps and the adhesive layer; patterning a portion of the first metal layer to form a metal pattern portion of a first metal pattern layer; The remaining portion of the first metal layer is patterned to form the plurality of first metal contacts, each of which is electrically connected to a corresponding grain metal bump, wherein a width of the metal pattern portion is greater than a width of the first metal contact.
23. The method according to claim 20, characterized in that Forming the metal pattern layer further includes: A final metal pattern layer is formed on the dielectric layer away from the first metal pattern layer, wherein the final metal pattern layer includes a plurality of second metal contacts.
24. The method according to claim 23, characterized in that The method further comprises: The second metal contact is subjected to surface treatment to form an anti-oxidation layer on the surface of the second metal contact.
25. The method according to claim 19, characterized in that Forming the dielectric layer includes: Providing a dielectric material layer and providing perforations on the dielectric material layer; The through-hole is filled with metal to form a conductive via to obtain the dielectric layer. The conductive via is used to couple two adjacent metal pattern layers.
26. The method according to any one of claims 12 to 25, characterized in that The number of the openings is at least two; After the interconnection layer is provided on the support plate, the method further comprises: Providing a packaging substrate; A surface of the interconnection layer away from the support plate is coupled to the packaging substrate, so that the interconnection layer becomes an intermediate layer between the die and the packaging substrate.