Packaging structure and manufacturing method thereof, chip and packaging method thereof, and electronic equipment

Abstract

The embodiment of the invention discloses a packaging structure and a manufacturing method thereof, a chip and a packaging method thereof, and electronic equipment, relates to the technical field of integrated circuit packaging, and can effectively reduce return loss of signals and improve signal integrity. The packaging structure comprises an interconnection layer and at least one crystal grain bearing cavity. The crystal grain bearing cavity is formed by the interconnection layer located on a supporting plate and at least one opening of the supporting plate; the interconnection layer comprises a metal pattern layer and a dielectric layer which are alternately stacked, and each opening penetrates through the supporting plate and exposes the surface of the metal pattern layer; wherein the surface of the exposed metal pattern layer forms a crystal grain bearing surface of the crystal grain bearing cavity, and the crystal grain bearing surface is used for being coupled with crystal grains placed in the crystal grain bearing cavity. The embodiment of the invention is suitable for chip packaging.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit packaging, and in particular to a packaging structure and a manufacturing method thereof, a chip and a packaging method thereof, and an electronic device. Background Art

[0002] As the performance of chips such as CPU (central processing unit) and GPU (graphics processing unit) continues to improve, the signal transmission rate is also getting faster and faster. As a result, the design of packaging substrates faces huge challenges and needs to achieve high-speed signal interconnection in a limited space.

[0003] In related technologies, packaging substrates are mostly supported by a core layer, and stacking layers are formed on both sides of the core layer for signal transmission. The signal on one side of the core layer needs to be transmitted to the other side of the core layer through the drilled holes in the core layer. Due to the large diameter of the drilled holes in the core layer, there will be impedance mismatch in the signal transmission path, resulting in a large return loss of the signal, which seriously affects the signal integrity. Summary of the invention

[0004] In view of this, the embodiments of the present invention provide a packaging structure and a manufacturing method thereof, a chip and a packaging method thereof, and an electronic device, which can effectively reduce the return loss of the signal and improve the signal integrity.

[0005] In a first aspect, an embodiment of the present invention provides a packaging structure, comprising an interconnection layer and at least one grain-carrying cavity; the grain-carrying cavity is formed by the interconnection layer located on a support plate and at least one opening of the support plate; the interconnection layer comprises alternatingly stacked metal pattern layers and dielectric layers, each of the openings passes through the support plate and exposes the surface of the metal pattern layer; wherein the exposed surface of the metal pattern layer forms a grain-carrying surface of the grain-carrying cavity, and the grain-carrying surface is used to couple with a grain placed in the grain-carrying cavity.

[0006] In one embodiment, the metal pattern layer includes a first metal pattern layer, the first metal pattern layer is located on the surface of the support plate, the first metal pattern layer includes a plurality of first metal contacts, and the opening exposes the surface of the plurality of first metal contacts as the grain bearing surface.

[0007] In one embodiment, the first metal pattern layer further includes a metal pattern portion, wherein a width of the metal pattern portion is greater than a width of the first metal contact.

[0008] In one embodiment, the first metal contact comprises a metal bump.

[0009] In one embodiment, the metal pattern layer includes a last metal pattern layer, the last metal pattern layer is located on a surface of a dielectric layer away from the first metal pattern layer; the last metal pattern layer includes a plurality of second metal contacts.

[0010] In one embodiment, the second metal contact comprises a pad.

[0011] In one embodiment, each of the dielectric layers includes a conductive via, and different metal pattern layers are coupled through the corresponding conductive via.

[0012] In a second aspect, an embodiment of the present invention further provides a chip, comprising a die and any packaging structure provided by an embodiment of the present invention, wherein the die is disposed in the die bearing cavity and coupled to the die bearing surface.

[0013] In one embodiment, the chip further includes an adhesive layer, wherein the adhesive layer is located between the die and the die-bearing cavity and is used to bond the die to the die-bearing cavity.

[0014] In one embodiment, the number of the die-carrying cavities is at least two; the chip further includes a packaging substrate, and the interconnect layer serves as an intermediate layer between the die and the packaging substrate, and is coupled to the die and the packaging substrate respectively.

[0015] In a third aspect, an embodiment of the present invention further provides an electronic device, comprising a printed circuit board and any one of the chips provided by the embodiments of the present invention, wherein the chip is arranged on the printed circuit board.

[0016] In a fourth aspect, an embodiment of the present invention further provides a method for manufacturing a packaging structure, the method comprising: providing a support plate; forming an interconnection layer on the support plate, the interconnection layer comprising alternatingly stacked metal pattern layers and dielectric layers; forming at least one opening passing through the support plate, wherein the opening exposes a surface of the metal pattern layer as a grain bearing surface, wherein the grain bearing surface and the opening form a grain bearing cavity for accommodating a grain, and the grain bearing surface is used to couple with the grain.

[0017] In one embodiment, forming the interconnection layer on the support plate includes: forming the metal pattern layers and the dielectric layers stacked alternately on the support plate.

[0018] In one embodiment, forming the metal pattern layer includes: forming a first metal pattern layer on the support plate, wherein the first metal pattern layer includes a plurality of first metal contacts, and the opening exposes the surface of the plurality of first metal contacts as the grain bearing surface.

[0019] In one embodiment, forming a first metal pattern layer on the support plate includes: forming a first metal layer on the support plate; patterning a portion of the first metal layer to form a metal pattern portion of the first metal pattern layer; and patterning the remaining portion of the first metal layer to form the plurality of first metal contacts, wherein a width of the metal pattern portion is greater than a width of the first metal contact.

[0020] In one embodiment, after forming at least one opening penetrating the support plate, the method further comprises: performing surface treatment on the first metal contact to form an anti-oxidation layer on the surface of the first metal contact.

[0021] In one embodiment, forming the metal pattern layer further comprises: forming a final metal pattern layer on a dielectric layer away from the first metal pattern layer, wherein the final metal pattern layer comprises a plurality of second metal contacts.

[0022] In one embodiment, after forming at least one opening penetrating the support plate, the method further comprises: performing surface treatment on the second metal contact to form an anti-oxidation layer on the surface of the second metal contact.

[0023] In one embodiment, forming the dielectric layer includes: providing a dielectric material layer and providing through-holes on the dielectric material layer; filling the through-holes with metal to form conductive vias to obtain the dielectric layer, wherein the conductive vias are used to couple two adjacent metal pattern layers.

[0024] In one embodiment, filling the through-hole with metal to form the conductive via comprises: depositing a metal seed layer on an inner wall of the through-hole; and performing electroplating based on the metal seed layer to form the conductive via.

[0025] In a fourth aspect, an embodiment of the present invention further provides a chip packaging method, comprising: providing a die and any packaging structure provided by an embodiment of the present invention; disposing the die in the die-carrying cavity of the packaging structure so that the die is coupled to the die-carrying surface.

[0026] In one embodiment, the metal pattern layer includes a first metal pattern layer, the first metal pattern layer is located on the surface of the support plate, the first metal pattern layer includes a plurality of first metal contacts, and the opening exposes the surface of the plurality of first metal contacts as the grain bearing surface; the step of arranging the grain in the grain bearing cavity of the packaging structure so that the grain is coupled to the grain bearing surface includes: forming a grain metal bump on the grain; placing the grain in the corresponding grain bearing cavity in the packaging structure; and welding the grain metal bump to the first metal contact.

[0027] In one embodiment, after welding the die metal bump to the first metal contact, the method further comprises: forming an adhesive layer in the die bearing cavity to fix the die to the die bearing cavity through the adhesive layer.

[0028] In one embodiment, the number of the grain-carrying cavities is at least two; after the grain is disposed in the grain-carrying cavity of the packaging structure, the method further includes: providing a packaging substrate; coupling the surface of the interconnection layer away from the support plate with the packaging substrate so that the interconnection layer becomes an intermediate layer between the grain and the packaging substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0030] Figure 1 A schematic diagram of a packaging structure provided by an embodiment of the present invention; Figure 2 Another schematic diagram of the structure of the packaging structure provided by the embodiment of the present invention; Figure 3 A schematic diagram of the structure of a chip provided by an embodiment of the present invention; Figure 4 Another schematic diagram of the structure of a chip provided by an embodiment of the present invention; Figure 5 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention; Figure 6 A flow chart of a method for manufacturing a packaging structure provided by an embodiment of the present invention; Figure 7 for Figure 6A process flow chart corresponding to the embodiment shown; Figure 8 A manufacturing process flow chart of a metal pattern layer in an embodiment of the present invention; Fig. 9 A manufacturing process flow chart of a dielectric layer in an embodiment of the present invention; Fig.10 A process flow chart of filling metal in a through hole and setting a next metal layer in an embodiment of the present invention; Fig.11 A flow chart of a chip packaging method provided by an embodiment of the present invention; Fig.12 A process flow chart of a chip packaging method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0031] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0032] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0033] The embodiment of the present invention provides a packaging structure, which can effectively reduce the return loss of the signal and improve the signal integrity.

[0034] like Figure 1 As shown, the packaging structure 42 provided by the embodiment of the present invention may include an interconnection layer 103 and at least one grain-carrying cavity 80; the grain-carrying cavity 80 is formed by the interconnection layer 103 located on the support plate 116 and at least one opening 120 of the support plate 116; the interconnection layer 103 includes alternately stacked metal pattern layers 114 and dielectric layers 110, and each opening 120 passes through the support plate 116 and exposes the metal pattern layer 114; wherein the exposed metal pattern layer 114 forms a grain-carrying surface 1031 of the grain-carrying cavity 80, and the grain-carrying surface 1031 is used to couple with the grain placed in the grain-carrying cavity 80.

[0035] In the packaging structure 42 provided by the embodiment of the present invention, the interconnection layer 103 is arranged on the support plate 116 to provide support for the interconnection layer 103, the interconnection layer 103 and the opening 120 of the support plate 116 can form a grain bearing cavity 80, and the metal pattern layer 114 exposed from the opening 120 can form a grain bearing surface 1031. Since the grain bearing surface 1031 can be used to couple with the grain placed in the grain bearing cavity 80, the signal in the grain can enter the interconnection layer 103 through the grain bearing surface 1031, and the signal transmission is realized through the metal pattern layer 114 in the interconnection layer 103. There is no core layer in the entire packaging structure, and there is no situation where the signal is transmitted from one side of the core layer to the other side of the core layer. Therefore, it can greatly improve the consistency of impedance in the signal transmission line, effectively reduce the return loss of the signal, and improve the signal integrity.

[0036] In the embodiment of the present invention, the support plate 116 mainly supports the interconnection layer 103 and does not participate in signal transmission. Therefore, any plate whose hardness and strength meet the support requirements can be used as the support plate 116. Exemplarily, in one embodiment of the present invention, the support plate 116 can include any of the following: a resin plate, a glass plate, and a ceramic plate.

[0037] In one embodiment of the present invention, the support plate 116 may be provided with an opening 120, and the specific position of the opening 120 on the support plate 116 is not limited, as long as it does not affect the supporting effect of the support plate 116 on the interconnection layer 103. For example, in one example, the opening 120 may be located in the center of the support plate 116.

[0038] The shape and size of the opening 120 can be adapted to the shape and size of the grain, so that the grain bearing cavity 80 can place and accommodate the corresponding grain. Wherein, adaptation means that after the grain is placed in the corresponding grain bearing cavity 80, the grain can be coupled with the grain bearing surface 1031 without causing excessive waste of space. For example, in one example, the shape of the opening 120 can be the same as the shape of the grain, and the size of the opening can be slightly larger than the grain, for example, the side length of the opening 120 can be 1 mm to 2 mm longer than the corresponding side length of the grain.

[0039] Furthermore, depending on the number of dies to be packaged, the number of openings 120 in the support plate 116 may also be different. For example, in one example, the number of openings 120 may be one, and in another example, the number of openings 120 may be two or more, wherein the die-bearing cavity 80 formed by each opening 120 is used to place and accommodate a corresponding die.

[0040] In an embodiment of the present invention, the interconnection layer 103 may include alternately stacked metal pattern layers 114 and dielectric layers 110. The metal pattern layers 114 may be used for signal transmission, and the dielectric layers 110 may be used for insulating and isolating different metal pattern layers 114.

[0041] In a specific implementation, the dielectric layer 110 may include various insulating materials. For example, in one example, the material of the dielectric layer 110 may include polyimide, and in another example, the material of the dielectric layer 110 may include ABF film. The materials of the dielectric layers 110 may be the same or different, and the embodiments of the present invention are not limited thereto.

[0042] The number of the metal pattern layers 114 may be multiple, and the specific structures of the metal pattern layers 114 may be different according to the different positions of the metal pattern layers 114 in the interconnection layer 103. Figure 2 As shown, the metal pattern layer 114 may include a first metal pattern layer 1141, the first metal pattern layer 1141 is located on the surface of the support plate 116, the first metal pattern layer 1141 includes a plurality of first metal contacts 21, and the opening 120 exposes the surface of the plurality of first metal contacts 21 as the grain bearing surface 1031. In a specific implementation, the specific form of the first metal contact 21 can be set and adjusted as needed, for example, in one example, the first metal contact 21 can include a metal bump. The first metal contact 21 can be used to electrically connect to the grain.

[0043] In one embodiment of the present invention, the first metal pattern layer 1141 may further include a metal pattern portion 23, wherein the width of the metal pattern portion 23 is greater than the width of the first metal contact 21. The metal pattern portion 23 may be located in an area of ​​the first metal pattern layer 1141 that is not exposed by the opening 120.

[0044] See again Figure 2 In another embodiment of the present invention, the metal pattern layer 114 may further include a last metal pattern layer 1142, the last metal pattern layer 1142 being located on a surface of the dielectric layer 110 away from the first metal pattern layer 1141; the last metal pattern layer 1142 may include a plurality of second metal contacts 22. In one example, the second metal contacts 22 may include pads. The second metal contacts 22 may be used to electrically connect the package structure to other components or devices, such as to electrically connect to a mainboard.

[0045] Further, in addition to the metal pattern layer 1141 of the first layer and the metal pattern layer 1142 of the second layer, in one embodiment of the present invention, the metal pattern layer 114 may also include at least one metal wiring layer 1143, and the at least one metal wiring layer 1143 may be located between the metal pattern layer 1141 of the first layer and the metal pattern layer 1142 of the second layer. The metal wiring layer 1143 may be used to redistribute the signal drawn from a crystal grain, or to interconnect two or more crystal grains, which is not limited in the embodiment of the present invention. In one embodiment of the present invention, the metal pattern layer 1141 of the first layer, the metal pattern layer 1142 of the second layer, and the metal wiring layer 1143 may be separated by different dielectric layers 110. Each dielectric layer 110 may include a conductive via 104, and different metal pattern layers 114 such as the metal pattern layer 1141 of the first layer, the metal pattern layer 1142 of the second layer, and the metal wiring layer 1143 may be coupled through corresponding conductive vias 104. Compared with the mechanical drilling of the core layer in the prior art, the sizes of the conductive vias 104 in the interconnect layer 103 are smaller and more consistent, so there is no impedance mutation and the resulting return loss.

[0046] Corresponding to the packaging structure provided in the above-mentioned embodiment, as Figure 3 As shown, an embodiment of the present invention further provides a chip 4, which may include a die 101 and a packaging structure 42, wherein the packaging structure 42 is any packaging structure provided in the above embodiments. The die 101 is disposed in the die bearing cavity 80 and coupled to the die bearing surface 1031.

[0047] Since the chip 4 provided in the embodiment of the present invention includes any one of the packaging structures 42 provided in the aforementioned embodiments, corresponding beneficial technical effects can also be achieved, which have been described in detail above and will not be repeated here.

[0048] In one implementation, the chip 4 may further include an adhesive layer, where the adhesive layer is located between the die 101 and the die-carrying cavity 80 and is used to bond the die 101 and the die-carrying cavity 80 .

[0049] Furthermore, if Figure 4 As shown, in one embodiment of the present invention, the number of the die bearing cavities 80 may be at least two; the chip 4 may further include a packaging substrate 3, and the interconnection layer 103 may serve as an interposer between the die 101 and the packaging substrate 3, and is coupled with the die 101 and the packaging substrate 3, respectively, so as to form a 2.5D package for the die 101. In this way, the interconnection layer 103 may interconnect a part of the signals between the die 101, and transmit another part of the signals in the die 101 to the packaging substrate 3, and interconnect or redistribute through the packaging substrate 3.

[0050] Accordingly, if Figure 5 As mentioned above, an embodiment of the present invention further provides an electronic device 5 , which may include a printed circuit board 51 and any chip 4 provided in the aforementioned embodiments, and the chip 4 is disposed on the printed circuit board 51 .

[0051] Since the electronic device 5 provided in the embodiment of the present invention includes any one of the chips 4 provided in the aforementioned embodiments, the corresponding beneficial technical effects can also be achieved, which have been described in detail above and will not be repeated here.

[0052] Corresponding to the aforementioned packaging structure, an embodiment of the present invention further provides a method for manufacturing a packaging structure. Figure 6 A flow chart of a method for manufacturing a packaging structure provided by an embodiment of the present invention, Figure 7 for Figure 6 The corresponding process flow chart. Figure 6 and Figure 7 , the manufacturing method of the packaging structure provided by the embodiment of the present invention may include: S61, providing a support plate 116; S62, forming an interconnection layer 103 on the support plate 116; the interconnection layer 103 includes metal pattern layers 114 and dielectric layers 110 that are alternately stacked; S63. Form at least one opening 120 penetrating the support plate 116, wherein the opening 120 exposes the metal pattern layer 114 as a grain bearing surface 1031, wherein the grain bearing surface 1031 and the opening 120 form a grain bearing cavity 80 for accommodating a grain, and the grain bearing surface 1031 is used to couple with the grain.

[0053] The manufacturing method of the packaging structure provided by the embodiment of the present invention can provide a support plate 116, form an interconnection layer 103 on the support plate 116 to provide support for the interconnection layer 103, and form at least one opening 120 penetrating the support plate 116, thereby exposing the metal pattern layer 114 as a grain bearing surface 1031, wherein the grain bearing surface 1031 and the opening 120 form a grain bearing cavity 80 for accommodating the grain, and the grain bearing surface 1031 is used to couple with the grain. In this way, the signal in the grain can enter the interconnection layer 103 through the grain bearing surface 1031, and realize signal transmission through the metal pattern layer 114 in the interconnection layer 103. The packaging structure 42 manufactured by this method does not have a core layer, and there is no situation where the signal is transmitted from one side of the core layer to the other side of the core layer. Therefore, it can greatly improve the consistency of impedance in the signal transmission line, effectively reduce the return loss of the signal, and improve the signal integrity.

[0054] In an embodiment of the present invention, the support plate 116 provided in step S61 mainly supports the interconnect layer 103 and does not participate in signal transmission. Therefore, any plate whose hardness and strength meet the support requirements can be used as the support plate 116. Exemplarily, in an embodiment of the present invention, the support plate 116 may include any of the following: a resin plate, a glass plate, or a ceramic plate.

[0055] After the support plate 116 is obtained in step S61, an interconnection layer 103 may be formed on the support plate 116 in step S62. In one embodiment of the present invention, forming the interconnection layer 103 on the support plate 116 may specifically include: forming alternately stacked metal pattern layers 114 and dielectric layers 110 on the support plate 116. The formation of the metal pattern layers 114 and the dielectric layers 110 is described in detail below.

[0056] First, the formation of the metal pattern layer 114 is described.

[0057] Specifically, in one embodiment of the present invention, forming the metal pattern layer 114 may include: forming a first metal pattern layer 1141 on a support plate 116, wherein the first metal pattern layer 1141 may include a plurality of first metal contacts 21, and the opening 120 exposes the surfaces of the plurality of first metal contacts 21 as a grain bearing surface 1031.

[0058] In one example, forming the first metal pattern layer 1141 on the support plate 116 may include: forming a first metal layer on the support plate 116; patterning a portion of the first metal layer to form a metal pattern portion 23 of the metal pattern layer of the first layer; and patterning the remaining portion of the first metal layer to form a plurality of first metal contacts 21, wherein the width of the metal pattern portion 23 may be greater than the width of the first metal contact 21. Exemplarily, in one example, the metal pattern portion 23 may include a metal line or a metal plane. The metal pattern portion 23 may be electrically connected to the first metal contact 21, or may not be electrically connected to the first metal contact 21, and the embodiment of the present invention is not limited to this. In one embodiment, the metal pattern portion 23 may be located in an area of ​​the metal pattern layer 1141 of the first layer that is not exposed by the opening 120.

[0059] It should be noted that, in the embodiment of the present invention, in terms of the manufacturing process, the first metal contact 21 and the metal pattern portion 23 may be formed simultaneously or successively, and the embodiment of the present invention is not limited thereto.

[0060] In addition to forming the first metal pattern layer 1141, in another embodiment of the present invention, forming the metal pattern layer 114 may also include: forming a last metal pattern layer 1142 on the dielectric layer 110 away from the first metal pattern layer 1141, and the last metal pattern layer 1142 may include multiple second metal contacts 22.

[0061] The process flow of forming the metal pattern layer 114 is briefly introduced below.

[0062] In one embodiment, Figure 8 As shown, the method for forming the metal pattern layer 114 may include: providing a metal layer 130; etching the metal layer 130 to form a corresponding metal pattern layer 114. In one example, providing the metal layer 130 may include laminating the metal layer 130, and in another example, providing the metal layer 130 may also include electroplating the metal layer 130. The metal layer 130 may be any conductive metal, for example, copper. In one embodiment of the present invention, etching the metal layer 130 to form the corresponding metal pattern layer 114 may include: providing a photosensitive material on the metal layer 130; exposing and developing the photosensitive material to obtain an etching mask; under the mask of the etching mask, etching the metal layer 130 to obtain the metal pattern layer 114; and then removing the etching mask, for example, the photolithography mask may be removed by a chemical method.

[0063] For example, in one example, when the photosensitive material is disposed on the metal layer 130, a photosensitive dry film may be laminated on the metal layer 130. In another example, when the photosensitive material is disposed on the metal layer 130, a photoresist may also be coated on the metal layer 130. The embodiments of the present invention are not limited to this.

[0064] In an embodiment of the present invention, there may be multiple metal pattern layers 114. Depending on the position of the metal pattern layer 114 in the interconnect layer 103, the specific structure of each metal pattern layer 114 may also be different. Specifically, when forming each metal pattern layer 114, the metal material, metal thickness, mask pattern, etc. may be adjusted accordingly.

[0065] The formation of the dielectric layer 110 is described below.

[0066] In one embodiment, Fig. 9 As shown, the method for forming the dielectric layer may include: setting a dielectric material layer 131 and setting a through hole 140 on the dielectric material layer 131; filling metal in the through hole 140 to form a conductive via 104 to obtain a dielectric layer 110, and the conductive via 104 is used to couple two adjacent metal pattern layers 114.

[0067] Specifically, in one embodiment of the present invention, providing the dielectric material layer 131 and providing the through-hole 140 on the dielectric material layer 131 may include: laminating the dielectric material layer 131; and providing the through-hole 140 on the dielectric material layer 131 by laser or chemical etching.

[0068] In one implementation, before laminating the dielectric material layer 131 , the metal pattern layer 114 may be roughened so that the metal pattern layer 114 can be better connected to the dielectric material layer 131 .

[0069] In another embodiment of the present invention, filling metal in the through-hole 140 to form the conductive via 104 may include: depositing a metal seed layer on the inner wall of the through-hole 140 ; ​​and performing electroplating based on the metal seed layer to form the conductive via 104 .

[0070] Since both filling the through hole 140 with metal and forming the next metal layer 130 require metal deposition, in one embodiment, Fig.10 As shown, the step of filling metal in the through hole 140 to form the conductive via 104 and the step of forming the next metal layer 130 can be performed continuously, that is, the process of filling metal in the through hole 140 and forming the next metal layer 130 can be formed integrally.

[0071] Furthermore, after obtaining the interconnection layer 103, at least one opening 120 penetrating the support plate 116 may be formed in step S63. Depending on the specific material of the support plate 116, the method of forming the opening 120 may also be different. For example, in one example, the support plate 116 is an organic material such as resin, and the opening 120 penetrating the support plate 116 may be formed by laser burning. Optionally, after laser burning, a chemical method may be further used to remove the remaining substances after burning. In another example, the support plate 116 is an inorganic material such as glass, and the opening 120 penetrating the support plate 116 may be formed by laser induction and chemical etching. Here, laser induction may refer to breaking chemical bonds in materials such as glass by irradiating laser, thereby making it easier to chemically react with the etching solution to form the opening 120.

[0072] Optionally, in the embodiment of the present invention, the specific position of the opening 120 on the support plate 116 is not limited, as long as it does not affect the supporting effect of the support plate 116 on the interconnection layer 103. For example, in one example, the opening 120 can be located in the center of the support plate 116.

[0073] The shape and size of the opening 120 can be adapted to the shape and size of the grain, so that the formed grain bearing cavity 80 can place and accommodate the corresponding grain. Wherein, adaptation means that after the grain is placed in the corresponding grain bearing cavity 80, the grain can be coupled with the grain bearing surface 1031 without causing excessive waste of space. For example, in one example, the shape of the opening 120 can be the same as the shape of the grain, and the size of the opening can be slightly larger than the grain, for example, the side length of the opening 120 can be 1 mm to 2 mm longer than the corresponding side length of the grain.

[0074] In a specific implementation, the number of openings 120 in the support plate 116 may be different depending on the number of die to be packaged. For example, in one example, the number of openings 120 may be one, and in another example, the number of openings 120 may be two or more, wherein the die-bearing cavity 80 formed by each opening 120 may be used to place and accommodate a corresponding die.

[0075] After the opening 120 penetrating the support plate 116 is formed in step S63, the first metal contact 21 can be exposed from the opening 120. Based on this, the method for manufacturing the package structure provided by the embodiment of the present invention can also include: performing surface treatment on the first metal contact 21 and the second metal contact 22 to form an anti-oxidation layer on the surface of the first metal contact 21 and the second metal contact 22 to prevent them from being oxidized or damaged by stress. For example, the first metal contact 21 and the second metal contact 22 can be surface treated by an electroless nickel-palladium immersion gold (ENEPIG) process.

[0076] Accordingly, if Fig.11 As shown, an embodiment of the present invention further provides a chip packaging method, which may include: S71, providing a die 101 and a packaging structure 42, wherein the packaging structure 42 is any packaging structure 42 provided in the above embodiments; S72 , disposing the die 101 in the die-carrying cavity 80 of the package structure 42 , so that the die 101 is coupled to the die-carrying surface 1031 .

[0077] The chip packaging method provided in the embodiment of the present invention utilizes any packaging structure 42 provided in the aforementioned embodiments, and thus can also achieve corresponding beneficial technical effects, which have been described in detail above and are not limited in the embodiment of the present invention.

[0078] Specifically, in the embodiment of the present invention, the metal pattern layer 114 may include a first metal pattern layer 114, the first metal pattern layer 114 may be located on the surface of the support plate 116, the first metal pattern layer 114 may include a plurality of first metal contacts 21, and the opening 120 exposes the surface of the plurality of first metal contacts 21 as a die bearing surface 1031. Based on this, step S72 of disposing the die 101 in the die bearing cavity 80 of the package structure 42 so that the die 101 is coupled to the die bearing surface 1031 may specifically include: forming a die metal bump 115 on the die 101; Placing the die 101 in the corresponding die-carrying cavity 80 in the packaging structure 42; The die metal bump 115 is welded to the first metal contact 21 .

[0079] Furthermore, in one embodiment of the present invention, after welding the grain metal bump 115 to the first metal contact 21, the chip packaging method provided by the embodiment of the present invention may also include: forming an adhesive layer in the grain carrying cavity 80 to fix the grain 101 to the grain carrying cavity 80 through the adhesive layer.

[0080] For example, a process flow chart of a chip packaging method provided by an embodiment of the present invention can be as follows: Fig.12 shown.

[0081] In another embodiment of the present invention, the number of the die-carrying cavities 80 is at least two; after the die 101 is disposed in the die-carrying cavity 80 of the packaging structure 42, the chip packaging method provided by the embodiment of the present invention may further include: Providing a packaging substrate 3; The surface of the interconnection layer 103 away from the support plate 116 is coupled to the packaging substrate 3 so that the interconnection layer 103 becomes an intermediate layer between the die 101 and the packaging substrate 3, thereby realizing 2.5D packaging.

[0082] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0083] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0084] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A packaging structure, characterized in that: comprising an interconnection layer and at least one die-bearing cavity; the die-bearing cavity is formed by the interconnection layer located on a support plate and at least one opening of the support plate; The interconnection layer includes alternately stacked metal pattern layers and dielectric layers, and each of the openings penetrates the support plate and exposes the surface of the metal pattern layer; wherein the exposed surface of the metal pattern layer forms a grain-bearing surface of the grain-bearing cavity, and the grain-bearing surface is used to couple with a grain placed in the grain-bearing cavity.

2. The packaging structure according to claim 1, characterized in that: The metal pattern layer includes a first metal pattern layer, the first metal pattern layer is located on the surface of the support plate, the first metal pattern layer includes a plurality of first metal contacts, and the opening exposes the surface of the plurality of first metal contacts as the grain bearing surface.

3. The packaging structure according to claim 2, wherein: The first metal pattern layer further includes a metal pattern portion, wherein a width of the metal pattern portion is greater than a width of the first metal contact.

4. The packaging structure according to claim 2, characterized in that: The first metal contact includes a metal bump.

5. The packaging structure according to claim 2, characterized in that: The metal pattern layer includes a last metal pattern layer, and the last metal pattern layer is located on a surface of a dielectric layer away from the first metal pattern layer; the last metal pattern layer includes a plurality of second metal contacts.

6. The packaging structure according to claim 5, characterized in that: The second metal contact includes a pad.

7. The packaging structure according to claim 1, characterized in that: Each of the dielectric layers includes a conductive via, and different metal pattern layers are coupled through the corresponding conductive via.

8. A chip, characterized in that: A packaging structure comprising a die and any one of claims 1 to 9, wherein the die is disposed in the die-bearing cavity and coupled to the die-bearing surface.

9. The chip according to claim 8, characterized in that: It also includes an adhesive layer, which is located between the die and the die-bearing cavity and is used to bond the die and the die-bearing cavity.

10. The chip according to claim 8, characterized in that: The number of the die bearing cavities is at least two; the chip further includes a packaging substrate, and the interconnection layer serves as an intermediate layer between the die and the packaging substrate, and is coupled to the die and the packaging substrate respectively.

11. An electronic device, characterized in that: The invention comprises a printed circuit board and the chip according to any one of claims 8 to 10, wherein the chip is arranged on the printed circuit board.

12. A method for manufacturing a packaging structure, characterized in that: include: Provide support plates; forming an interconnection layer on the support plate, wherein the interconnection layer comprises metal pattern layers and dielectric layers stacked alternately; At least one opening is formed through the support plate, wherein the opening exposes the surface of the metal pattern layer as a grain bearing surface, wherein the grain bearing surface and the opening form a grain bearing cavity for accommodating a grain, and the grain bearing surface is used to couple with the grain.

13. The method according to claim 12, characterized in that The forming of an interconnection layer on the support plate comprises: The metal pattern layers and the dielectric layers are alternately stacked and formed on the support plate.

14. The method according to claim 13, characterized in that Forming the metal pattern layer includes: A first metal pattern layer is formed on the support plate, wherein the first metal pattern layer includes a plurality of first metal contacts, and the opening exposes surfaces of the plurality of first metal contacts as the grain bearing surface.

15. The method according to claim 14, characterized in that The first metal pattern layer formed on the support plate includes: forming a first metal layer on the support plate; patterning a portion of the first metal layer to form a metal pattern portion of a first metal pattern layer; The remaining portion of the first metal layer is patterned to form the plurality of first metal contacts, wherein a width of the metal pattern portion is greater than a width of the first metal contacts.

16. The method according to claim 14, characterized in that After forming at least one opening through the support plate, the method further comprises: The first metal contact is subjected to surface treatment to form an anti-oxidation layer on the surface of the first metal contact.

17. The method according to claim 13, characterized in that Forming the metal pattern layer further includes: A final metal pattern layer is formed on the dielectric layer away from the first metal pattern layer, wherein the final metal pattern layer includes a plurality of second metal contacts.

18. The method according to claim 17, characterized in that After forming at least one opening through the support plate, the method further comprises: The second metal contact is subjected to surface treatment to form an anti-oxidation layer on the surface of the second metal contact.

19. The method according to claim 13, characterized in that Forming the dielectric layer includes: Providing a dielectric material layer and providing perforations on the dielectric material layer; The through-hole is filled with metal to form a conductive via to obtain the dielectric layer. The conductive via is used to couple two adjacent metal pattern layers.

20. The method according to claim 19, characterized in that Filling metal in the through hole to form a conductive via comprises: depositing a metal seed layer on an inner wall of the through hole; Electroplating is performed based on the metal seed layer to form the conductive via.

21. A chip packaging method, characterized in that: include: Provide a die and a packaging structure as described in any one of claims 1 to 9; The die is disposed in the die-bearing cavity of the packaging structure so that the die is coupled to the die-bearing surface.

22. The method according to claim 21, characterized in that The metal pattern layer comprises a first metal pattern layer, the first metal pattern layer is located on the surface of the support plate, the first metal pattern layer comprises a plurality of first metal contacts, and the opening exposes the surfaces of the plurality of first metal contacts as the grain bearing surface; The step of disposing the die in the die-bearing cavity of the packaging structure so that the die is coupled to the die-bearing surface comprises: forming a grain metal bump on the grain; Placing the die in the corresponding die-carrying cavity in the packaging structure; The die metal bump is welded to the first metal contact.

23. The method according to claim 22, characterized in that After welding the grain metal bump to the first metal contact, the method further comprises: An adhesive layer is formed in the die-carrying cavity to fix the die to the die-carrying cavity through the adhesive layer.

24. The method according to claim 21, characterized in that The number of the grain-carrying cavities is at least two; After the die is disposed in the die-carrying cavity of the packaging structure, the method further includes: Providing a packaging substrate; A surface of the interconnection layer away from the support plate is coupled to the packaging substrate, so that the interconnection layer becomes an intermediate layer between the die and the packaging substrate.

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