Broadband phase interpolator

Abstract

A phase interpolator includes a sampling circuit configured to capture samples of an output of the phase interpolator; a delay circuit configured to delay the sampling by the sampling circuit; a comparator configured to provide a comparison signal indicating whether a voltage of the sample exceeds a reference voltage; and a counter responsive to the comparison signal and configured to provide an output to control an operating point of the phase interpolator. The phase interpolator may also include a pair of drive circuits configured to concurrently drive the output of the phase interpolator.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to pending U.S. Provisional Application No. 17 / 946,798, filed on September 16, 2022, which is assigned to the assignee of the present application and is hereby expressly incorporated herein by reference as if fully set forth below and for all applicable purposes. Technical Field

[0003] The present disclosure relates generally to clock and data recovery circuits, and more particularly, to circuits for generating multiple clock signals at different phases. Background Art

[0004] Electronic device technology has exploded over the past few years. For example, better communications, hardware, larger networks, and more reliable protocols have driven the development of cellular and wireless communication technologies. Wireless service providers are now able to offer their customers an ever-expanding array of features and services, and provide users with unprecedented levels of access to information, resources, and communications. To keep pace with these service enhancements, mobile electronic devices (e.g., cellular phones, tablet devices, laptop computers, etc.) have become more powerful and complex than ever before. Wireless devices may include high-speed bus interfaces for signal communication between hardware components.

[0005] High-speed serial buses offer advantages over parallel communication links when reduced power consumption and a smaller footprint are required, such as in integrated circuit (IC) devices. In a serial interface, a serializer is used to convert data from parallel words to a serial bit stream, and a deserializer is used to convert the data back to parallel words at the receiver. For example, a high-speed bus interface can be implemented using a peripheral component interconnect express (PCIe) bus, a universal serial bus (USB), or a serial advanced technology attachment (SATA), etc.

[0006] IC devices may include a serializer / deserializer (SERDES) for transmission and reception over a serial communication link. In high-speed applications, the timing of the operation of the SERDES may be controlled by multiple clock signals. The use of multiple clock signals with increasing frequencies results in increased power consumption. In addition, the SERDES typically receives clock signals with the same frequency but different phases. The performance, accuracy, or reliability of the SERDES may depend on the frequency and phase relationship of the clock signals, and deviations or other variations in the phase relationship of the clock signals may result in errors in the received data. Therefore, there is a continuing need for new technologies that provide reliable low-power clock generation and calibration circuits for components that receive clock signals over high-speed serial links. Summary of the invention

[0007] Certain aspects of the present disclosure relate to systems, apparatus, methods, and techniques for implementing and calibrating a phase interpolator that can be used with a clock signal that can have a frequency that varies over a wide range of frequencies.

[0008] In various aspects of the present disclosure, a phase interpolator includes: a sampling circuit configured to capture a sample of an output of the phase interpolator; a delay circuit configured to delay a sample taken by the sampling circuit; a comparator configured to provide a comparison signal indicating whether a voltage of the sample exceeds a reference voltage; and a counter responsive to the comparison signal and configured to provide an output controlling an operating point of the phase interpolator. The phase interpolator may also include a pair of drive circuits configured to concurrently drive the output of the phase interpolator.

[0009] In various aspects of the present disclosure, a device includes a component for capturing a sample of an output of the device. The component for capturing the sample may include a delay circuit configured to delay sampling performed by a sampling circuit. The device may also include: a component for providing a comparison signal indicating whether the voltage of the sample exceeds a reference voltage, and a component for generating a control signal responsive to the comparison signal and configured to control an operating point of the device. The device may also include a component for generating an output signal representing a weighted sum of a pair of input signals received by the device. The component for generating the output signal may include a pair of drive circuits configured to concurrently drive the output of the device. The pair of input signals may have the same frequency and be phase-shifted relative to each other.

[0010] In various aspects of the present disclosure, a method for operating a phase interpolator circuit includes: capturing a sample of an output of the phase interpolator circuit using a sampling circuit and a delay circuit configured to delay a sample taken by the sampling circuit; providing a comparison signal indicating whether a voltage of the sample exceeds a reference voltage; and generating a control signal responsive to the comparison signal and configured to control an operating point of the phase interpolator circuit. The method may also include generating an output signal representing a weighted sum of a pair of input signals received by the phase interpolator circuit using a pair of drive circuits configured to concurrently drive the output of the phase interpolator circuit. The pair of input signals may have the same frequency and be phase shifted relative to each other.

[0011] In certain aspects, the output of the counter can be used to configure one or more bias circuits in the pair of driver circuits. The output of the counter can be configured to configure one or more current sources of the pair of driver circuits. The output of the counter can configure a digitally controlled voltage source that controls an operating point for the pair of driver circuits.

[0012] In some aspects, the pair of drive circuits are coupled to a pair of input signals having the same frequency and phase shifted relative to each other. The pair of drive circuits can be configured to generate a weighted sum of the pair of input signals. Each drive circuit in the pair of drive circuits can include one or more load transistors configured to control a level of current contributed by the drive circuit to an output of the phase interpolator.

[0013] In certain aspects, the operating point of the phase interpolator may be configurable for the frequency of the pair of input signals. The operating point of the phase interpolator may be one of a plurality of operating points configured for different frequencies of the input signal received by the phase interpolator. The sampling circuit may be configured to capture a sample during a pulse in the input signal received by the phase interpolator. The counter may be configured to count cycles of the clock signal until the comparison signal indicates that the voltage of the sample exceeds the reference voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 Example components and interconnections in a system on a chip (SoC) that may be suitable for implementing certain aspects of the present disclosure are illustrated.

[0015] Figure 2 An example of a system employing a multi-channel data communication link to couple a transmitting device with a receiving device in accordance with certain aspects of the present disclosure is illustrated.

[0016] Figure 3 Certain aspects of a phase interpolator circuit configured in accordance with certain aspects of the present disclosure are illustrated.

[0017] Figure 4 Illustrate some aspects of the present disclosure Figure 3 The operation of the phase interpolator circuit after the phase interpolator circuit has been calibrated.

[0018] Figure 5 An example of a phase interpolator circuit including a calibration circuit in accordance with certain aspects of the present disclosure is illustrated.

[0019] Figure 6 The operation of a calibration circuit according to certain aspects of the present disclosure is illustrated.

[0020] Figure 7 is a flow chart illustrating an example of a method for operating a phase interpolator circuit in accordance with certain aspects of the present disclosure. DETAILED DESCRIPTION

[0021] The specific embodiments described below in conjunction with the accompanying drawings are intended as descriptions of various configurations and are not intended to represent the only configurations with which the concepts described herein can be practiced. In order to provide a thorough understanding of the various concepts, the specific embodiments include specific details. However, it is obvious to those skilled in the art that these concepts can be practiced without these specific details. In some instances, in order to avoid blurring such concepts, known structures and components are shown in block diagram form.

[0022] Referring now to the accompanying drawings, several exemplary aspects of the present disclosure are described. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0023] The terms "computing device" and "mobile device" are used interchangeably herein to refer to any or all of the following: servers, personal computers, smart phones, cellular phones, tablet computers, laptop computers, netbooks, ultrabooks, palmtop computers, personal data assistants (PDAs), wireless email receivers, multimedia Internet-enabled cellular phones, global positioning system (GPS) receivers, wireless game controllers, and similar personal electronic devices that include programmable processors. While various aspects are particularly useful in mobile devices (e.g., smart phones, laptop computers, etc.) with limited resources (e.g., processing power, battery, size, etc.), these aspects are generally useful in any computing device that can benefit from increased processor performance and reduced energy consumption.

[0024] The term "multi-core processor" is used herein to refer to a single integrated circuit (IC) chip or chip package that contains two or more independent processing units or cores (e.g., CPU cores, etc.) configured to read and execute program instructions. The term "multiprocessor" is used herein to refer to a system or device that includes two or more processing units configured to read and execute program instructions.

[0025] The term "system on chip" (SoC) is used herein to refer to a single integrated circuit (IC) chip that includes multiple resources and / or processors integrated on a single substrate. A single SoC may include circuits for digital, analog, mixed signal, and radio frequency functions. A single SoC may also include any number of general and / or special-purpose processors (digital signal processors (DSPs), modem processors, video processors, etc.), storage blocks (e.g., read-only memory (ROM), random access memory (RAM), flash memory, etc.), and resources (e.g., timers, voltage regulators, oscillators, etc.), any or all of which may be included in one or more cores.

[0026] The memory technologies described herein may be suitable for storing instructions, programs, control signals, and / or data for use in or by a computer or other digital electronic device. Any reference to terms and / or technical details related to individual memory types, interfaces, standards, or memory technologies is for illustrative purposes only and is not intended to limit the scope of the claims to a particular memory system or technology unless specifically stated in the claim language. The complexity of mobile computing device architectures has grown and now typically includes multiple processor cores, SoCs, coprocessors, functional modules including dedicated processors (e.g., communication modem chips, GPS receivers, etc.), complex memory systems, intricate electrical interconnects (e.g., buses and / or fabrics), and many other resources to execute complex and power-intensive software applications (e.g., video streaming applications, etc.).

[0027] Certain aspects of the present disclosure apply to input / output (I / O) circuits that provide an interface between core circuits and memory devices. Many mobile devices employ synchronous dynamic random access memory (SDRAM), including low-power double data rate SDRAM, which may be referred to as low-power DDR SDRAM (LPDDR SDRAM), or in some instances, LPDDRx, where x describes the technology formation of the LPDDR SDRAM. Later generations of LPDDR SDRAM designed to operate at higher operating frequencies may employ lower voltage levels in the core of the SoC or memory device to mitigate the power increase associated with the higher operating frequencies.

[0028] Process technologies used to manufacture semiconductor devices (including IC devices) are constantly improving. Process technologies include manufacturing methods used to manufacture IC devices and define transistor size, operating voltage, and switching speed. Features that are components of circuits in IC devices may be referred to as technology nodes and / or process nodes. The terms "technology node," "process node," and "process technology" may be used to characterize a particular semiconductor manufacturing process and corresponding design rules. Faster and more efficient technology nodes are constantly being developed by using smaller feature sizes to produce smaller transistors that enable the manufacture of higher density ICs.

[0029] Figure 1Example components and interconnects in a system on chip (SoC) 100 that may be suitable for implementing certain aspects of the present disclosure are illustrated. SoC 100 may include multiple heterogeneous processors, such as a central processing unit (CPU) 102, a modem processor 104, a graphics processor 106, and an application processor 108. Each processor 102, 104, 106, 108 may include one or more cores, and each processor / core may perform operations independently of the other processors / cores. Processors 102, 104, 106, 108 may be organized in close proximity to each other (e.g., on a single substrate, die, integrated chip, etc.) so that the processors may operate at much higher frequencies / clock rates than would be possible if signals were propagated off-chip. The proximity of the cores may also allow for sharing of on-chip memory and resources (e.g., voltage rails), as well as allowing for more coordinated collaboration between the cores.

[0030] SoC 100 may include system components and resources 110 for managing sensor data, analog-to-digital conversion, and / or wireless data transmission, as well as for performing other specialized operations (e.g., decoding high-definition video, video processing, etc.). System components and resources 110 may also include components such as voltage regulators, oscillators, phase-locked loops (PLLs), peripheral bridges, data controllers, system controllers, access ports, timers, and / or other similar components for supporting processors and software clients running on the computing device. System components and resources 110 may also include circuits for interfacing with peripheral devices such as cameras, electronic displays, wireless communication devices, external memory chips, etc.

[0031] SoC 100 may also include a universal serial bus (USB) or other serial bus controller 112, one or more memory controllers 114, and a centralized resource manager (CRM) 116. SoC 100 may also include an input / output module (not illustrated) for communicating with resources external to the SoC, each of which may be shared by two or more of the internal SoC components.

[0032] Processors 102, 104, 106, 108 may be interconnected to USB controller 112, memory controller 114, system components and resources 110, CRM 116, and / or other system components via interconnect / bus module 122, which may include a reconfigurable logic gate array and / or implement a bus architecture. Communications may also be provided by advanced interconnects such as a high-performance network-on-chip (NoC).

[0033] The interconnect / bus module 122 may include or provide a bus master system that is configured to grant the SoC component (e.g., processor, peripheral device, etc.) exclusive control of the bus (e.g., transfer data in burst mode, block transfer mode, etc.) to achieve a set duration, number of operations, number of bytes, etc. In some cases, the interconnect / bus module 122 may implement an arbitration scheme to prevent multiple master components from attempting to drive the bus at the same time. The memory controller 114 may be a dedicated hardware module configured to manage the flow of data to and from the memory 124 via the memory interface / bus 126.

[0034] The memory controller 114 may include one or more processors configured to perform read and write operations on the memory 124. Examples of processors include microprocessors, microcontrollers, digital signal processors (DSPs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic components, discrete hardware circuits, and other suitable hardware configured to perform various functionalities described throughout the present disclosure. In some aspects, the memory 124 may be part of the SoC 100.

[0035] Figure 2 An example of a system that uses a multi-channel data communication link 250 to couple a transmitting device 200 with a receiving device 220 is illustrated. The data communication link 250 includes data channels 2521-252 K , which data channels provide a transmission medium through which signals propagate from the first device to the second device. In the illustrated example, the transmitting device 200 may be configured to transmit signals on one or more data channels 2521-252 according to timing information provided by a clock signal transmitted on the clock channel 254. K The transmitting device 200 may include a device configured to convert parallel data into serial data for transmission on the data channels 2521-252. K The transmitting device 200 also includes data line drivers 2061-206 K The data line drivers are configured to transmit data on one or more data channels 2521-252 via the data communication link 250 based on the timing information provided by the clock signal forwarded by the clock line driver 204 on the clock channel 254. K A data signal is generated to the receiving device 220.

[0036] Clock forwarding is common in communication systems and provides the benefit of not requiring a phase locked loop (PLL) and other clock recovery circuitry in the receiving device 220. Long term jitter originating from the PLL 202 in the transmitting device 200 is transparent to the system. Typically, only one phase of the transmitter generated clock signal is forwarded to save power and space that would be occupied by an additional clock channel. In some examples, multiple phases of the transmitter generated clock signal are forwarded. In some examples, the transmitter generated clock signal is forwarded as a differential clock signal.

[0037] The receiving device 220 can be configured to receive and process the data signal. In some implementations, the receiving device 220 can generate an additional phase of the clock signal to obtain the phase interpolator 2281-228 K In-phase and quadrature (I / Q) versions of the clock signal are used. The phase of the quadrature signal is shifted 90° relative to the in-phase signal. Phase interpolator 2281-228 K The output may be provided as a phase adjusted or phase corrected I / Q version of the clock signal. In one example, the phase interpolators 2281-228 K The output of each phase interpolator is provided to sampling circuits 2241-224 K .

[0038] In some implementations, the receiving device 220 includes an injection locked oscillator (ILO) that receives a clock signal from a line receiver 222 coupled to a clock channel 254 and generates a phase shifted version 234 of the clock signal, including an I / Q version of the clock signal. Oscillators are a fundamental building block of modern electronics and are often implemented as ring oscillators (ROs), which can provide advantages over other types of oscillators, including reduced footprint, power efficiency, and scalability of technology processes.

[0039] In one example, the multi-channel data communication link 250 may correspond to Figure 1 The memory interface / bus 126 is shown and can be used to couple the memory controller 114 to a memory 124 implemented using SDRAM that can operate at multiple frequencies and voltages. Later generations of LPDDR SDRAM, including, for example, LPDDR6 (6th generation), are designed to operate at higher operating frequencies and lower voltage levels than previous generation memory devices. The wide range of possible operating frequencies to be supported in certain applications may result in increased complexity of the clock generation circuitry in the receiving device 220. Phase interpolators 2281-2282 may be required to generate the sampling clock signal. K To scale the delay circuit for operation over a wide range of frequencies. For example, phase interpolators 2281-228 KOperates reliably in the frequency range between 200Mhz and 6.4GHz.

[0040] For example, certain aspects of the present disclosure provide a phase interpolator that can be configured to operate at 200Mhz and 6.4GHz. Certain implementations of the presently disclosed phase interpolator can operate at higher and lower frequencies as needed to generate fine delays for use within a receiving device.

[0041] Figure 3 Certain aspects of a phase interpolator circuit configured in accordance with certain aspects of the present disclosure are illustrated. Figure 4 is a timing diagram 400 illustrating the operation of the phase interpolator circuit after the phase interpolator circuit has been calibrated for the frequency of a clock signal provided to the phase interpolator circuit. In some implementations, the phase interpolator circuit includes or is coupled to a circuit that provides an I / Q version of the clock signal. In some implementations, the oscillator circuit outputs the I / Q version of the clock signal.

[0042] The phase interpolator circuit includes two driver circuits 300 and 320 configured to drive a common output 310 with configurable weights. In the illustrated example, the driver circuits 300 and 320 can operate in the manner of binary inverters. The first driver circuit 300 receives an input signal 302 (In_I) as an in-phase version of a clock signal and contributes an output current through its output 308 at a current level that can be controlled using variable load transistors 304 and 306. The second driver circuit 320 receives an input signal 322 (In_Q) as a quadrature version of the clock signal and contributes an output current through its output 328 at a current level that can be controlled using variable load transistors 324 and 326. The driver circuits 300 and 320 can contribute to the common output 310 by supplying or absorbing their respective output currents. The contribution of the driver circuits 300 and 320 to the instantaneous amplitude of the current flowing through the common output 310 can be additive or subtractive depending on the phase of the clock signal provided to the phase interpolator circuit.

[0043] In the illustrated example, the clock signal has a 50% duty cycle and can be characterized as having equal duration half cycles such that the clock signal is nominally in a first signaling state during a first half cycle and in a second signaling state during a second half cycle. The driver circuits 300 and 320 are configured to follow their respective input signals 302, 322 while slowing down transitions in their respective outputs 308, 328.

[0044] In the illustrated example, the input signal 302 received by the first driver circuit 300 begins a transition from a low signaling state to a high signaling state at the beginning 410 of a half cycle 408 of the clock signal, and begins a transition back to the low signaling state at the end 412 of the half cycle 408 of the clock signal. The high signaling state may be represented by a first voltage level or a first current level, and the low signaling state may be represented by a second voltage level or a second current level. In one example, the first voltage level is more positive than the second voltage level. In another example, the first voltage level is more negative than the second voltage level. In another example, the first voltage level and the second voltage level have different signs. In another example, the first current has a greater amplitude than the second current. In another example, the first current has a lower amplitude than the second current. In another example, the first current and the second current flow in different directions. The output 308 of the first driver circuit 300 begins to rise at the beginning 410 of the half cycle 408, and nominally reaches a high signaling state at the end 412 of the half cycle 408. The output 308 of the first driver circuit 300 begins to fall at the end 412 of the half cycle 408 .

[0045] The input signal 322 received by the second driver circuit 320 begins transitioning from a low signaling state to a high signaling state at a time 414 occurring one quarter of the clock cycle after the start 410 of the half cycle 408 of the clock signal, and begins transitioning back to the low signaling state at a time 416 occurring one quarter of the clock cycle after the end 412 of the half cycle 408 of the clock signal. The output 328 of the second driver circuit 320 begins rising at time 414 and nominally reaches the high signaling state at time 416. The output 308 of the first driver circuit 300 begins falling at time 416.

[0046] According to certain aspects of the present disclosure, the output of the phase interpolator represents a weighted sum of the outputs 308, 328 of the two drive circuits 300 and 320. The weight applied to the output of the first drive circuit 300 is determined by the variable load transistors 304 and 306, and the weight applied to the output of the second drive circuit 320 is determined by the variable load transistors 324 and 326. The relative weighting of the outputs 308, 328 of the two drive circuits 300 determines the time at which a transition in the common output 310 causes the buffer circuit 312 to initiate a transition in the phase interpolator output 314. The buffer circuit 312 can be configured to adjust the phase interpolator output 314. For example, the buffer circuit 312 can be configured to square the edges in the phase interpolator output 314 so that the transitions in the phase interpolator output 314 represent a fraction of the duration of the half cycle 408 of the clock signal. In some implementations, each transition occupies less than 10% of the duration of the half cycle 408 of the clock signal. In some implementations, each transition occupies less than 5% of the duration of the half cycle 408 of the clock signal. In other implementations, the duration of the transition may be limited by tolerances and specifications specified during design.

[0047] In the illustrated example, each of the variable load transistors 304, 306, 324, and 326 may be configured to select a weight value ranging between zero and 30. Combinations or permutations of weights may be used to generate a signal having a phase angle within a range defined by the phases of the in-phase and quadrature versions of the clock signal.

[0048] In the first illustrated weighting example 420, variable load transistors 304 and 306 are configured to apply a maximum weight (30) to the current contributed by output 308 of the first driver circuit 300, and variable load transistors 324 and 326 are configured to apply a minimum weight (nominal zero weight) to the current contributed by output 328 of the second driver circuit 320. In this example, the second driver circuit 320 does not contribute to the common output 310, and the phase interpolator output 314 follows the input signal 302 received by the first driver circuit 300. In this example, the phase interpolator output 314 can be viewed as representing an in-phase version of a clock signal used to control the timing of the data receiving circuit.

[0049] In the second illustrated weighting example 430, variable load transistors 304 and 306 are configured to apply a minimum weight (nominal zero weight) to the current contributed by output 308 of the first driver circuit 300, and variable load transistors 324 and 326 are configured to apply a maximum weight (30) to the current contributed by output 328 of the second driver circuit 320. In this example, the first driver circuit 300 does not contribute to the common output 310, and the phase interpolator output 314 follows the input signal 322 received by the second driver circuit 300. In this example, the phase interpolator output 314 can be viewed as representing an orthogonal version of a clock signal used to control the timing of the data receiving circuit.

[0050] In the third illustrated weighting example 440, the drive circuits 300 and 320 are configured with equal weights. Current is contributed by the output 308 of the first drive circuit 300. The variable load transistors 304 and 306 are configured to apply a mid-range weight (15) to the current contributed by the output 308 of the first drive circuit 300, and the variable load transistors 324 and 326 are configured to apply a mid-range weight (15) to the current contributed by the output 328 of the second drive circuit 320. In this example, the first drive circuit 300 and the second drive circuit 320 contribute equally, so that the transition in the common output 310 lags the transition in the input signal 302 received by the first drive circuit 300 by 45° phase angle and leads the transition in the input signal 322 received by the second drive circuit 320 by 45° phase angle. In this example, the phase interpolator output 314 can be viewed as a bi-phase version of a clock signal representing the timing of the data receiving circuit.

[0051] Figure 4 Shown for Figure 3 The operating mode of the phase interpolator circuit shown is effective for clock signals operating at the calibration frequency or in a narrow frequency band around the calibration. As used herein, the calibration frequency corresponds to the frequency of the input clock signal when the phase interpolator circuit is calibrated. The frequency of the clock signal defines the duration of the half cycle 408 of the clock signal, and thus defines certain restrictions on the operation of the phase interpolator circuit. For example, the drive circuits 300 and 320 can be configured to select a phase defined by the phase of the in-phase and quadrature versions of the clock signal when the rise time of the transition in the output 308, 328 for the drive circuits 300 and 320 is calibrated to be substantially equal to the duration of the half cycle 408 of the clock signal.

[0052] The change in the duration of the half-cycle 408 of the clock signal may render the phase interpolator circuit ineffective in systems where the input clock signal is expected to vary over a wide frequency range. For example, when the expected clock frequency varies between 200 MHz and 6.4 GHz, the half-cycle 408 of the clock signal may vary between 2.5 ns and 0.78 ns. Furthermore, the variation in rise time in the driver circuits 300 and 320 may vary significantly due to process, voltage, and temperature (PVT) variations, and such PVT variations may limit the number and magnitude of phase angles that may be added by the phase interpolator circuit.

[0053] Phase interpolator circuits provided according to certain aspects of the present disclosure may be calibrated for use over a large operating frequency range and in accordance with PVT.In one aspect, the drive strength of driver circuits 300 and 320 may be controlled to configure the rise time in accordance with the input clock frequency.

[0054] Figure 5 An example of a phase interpolator circuit 500 that can be calibrated according to certain aspects of the present disclosure is illustrated. In the illustrated example, the phase interpolator circuit 500 is based on Figure 3 The phase interpolator shown in FIG. 5 and operates in a similar manner when calibrated for the frequency of the input clock signal. The phase interpolator circuit 500 also includes a calibration circuit 520 that can be used to set an operating point for the driver circuits 300 and 320. The operating point can be determined or limited by the drive strength of the driver circuits 300 and 320. In the illustrated example, the drive strength of the driver circuits 300 and 320 is selected by the bias voltages 534, 536 (Vbp and Vbn) of the bias control transistors 506a, 506b in the first driver circuit 300 and the bias control transistors 508a, 508b in the second driver circuit 320.

[0055] The illustrated phase interpolator circuit 500 includes two drive circuits 300 and 320 configured to drive a common output 510 with configurable weights. The first drive circuit 300 receives an input signal 502 (In_I) as an in-phase version of an input clock signal and contributes an output current to the common output 510 at a current level that can be controlled using variable load transistors 304 and 306. The second drive circuit 320 receives an input signal 504 (In_Q) as a quadrature version of the input clock signal and contributes an output current to the common output 510 at a current level that can be controlled using variable load transistors 324 and 326. The drive circuits 300 and 320 can contribute to the common output 510 by supplying or absorbing their respective output currents. The contribution of the drive circuits 300 and 320 to the instantaneous amplitude of the current flowing through the common output 510 can be additive or subtractive depending on the phase of the input clock signal. The buffer circuit 548 can be configured to adjust the output 550 of the phase interpolator 500. For example, the buffer circuit 548 may be configured to square the edges of the output 550 of the phase interpolator 500 so that transitions in the output 550 represent a fraction of the duration of a half-cycle of the input clock signal.

[0056] Also refer to Figure 6 600, the driver circuits 300 and 320 may be configured to select a phase defined by the phases of the in-phase and quadrature versions of the input clock signal when the rise time for a transition between signaling states in the outputs of the driver circuits 300 and 320 is substantially equal to the duration of a pulse 602 in the input clock signal. In a nominal case, the duration of the pulse 602 may correspond to the duration of a half cycle of the input clock signal. In some cases, the duration of the pulse may be greater or less than a half cycle of the input clock signal. The frequency of the input clock signal defines the duration of a half cycle of the input clock signal, and according to certain aspects of the present disclosure, the frequency of the input clock signal may be associated with an operating point of the phase interpolator circuit 500. When the bias voltages 534, 536 of the bias control transistors 506a, 506b, 508a, 508b are configured such that a transition in the outputs of the driver circuits 300 and 320 is completed after a duration corresponding to a half cycle of the input clock signal, the operating point of the phase interpolator circuit 500 may be selected.

[0057] According to certain aspects of the present disclosure, the bias voltages 534, 536 provided to the bias control transistors 506a, 506b, 508a, 508b may be calibrated for a given duration of the pulse 602 and / or the clock signal frequency. The bias voltages 534, 536 may be calibrated to accommodate timing variations caused by PVT conditions. The calibration process involves configuring the calibration circuit 520 to set the bias voltages 534, 536 at a level that provides the longest rise time for the transitions in the outputs of the driver circuits 300 and 320, and incrementally modifying the bias voltages until the rise time of the transitions in the outputs of the driver circuits 300 and 320 is optimized. In one example, the rise time of the transitions in the outputs of the driver circuits 300 and 320 is optimized when the transitions are completed after a duration substantially equal to the duration of the pulse 602. In another example, the rise time of the transitions in the outputs of the driver circuits 300 and 320 is optimized when the transitions are completed within the duration of the pulse 602. In another example, the rise time of the transition in the output of the driver circuits 300 and 320 is optimized when the transition is completed after a duration within a time range that includes the duration of the pulse 602. In the latter example, the size of the time range may be defined by tolerances during the design of the phase interpolator circuit 500.

[0058] In the illustrated example, the calibration circuit 520 in the phase interpolator circuit 500 includes a sampling circuit, a counter 528, and a digitally controlled voltage source 530. The sampling circuit can be implemented using a holding capacitor 524 and a P-type metal oxide semiconductor (PMOS) transistor 522 configured as a switch. The source of the PMOS transistor 522 is configured to couple the common output 510 of the driver circuits 300, 320 to a terminal of the holding capacitor 524 under the control of a sampling clock signal 518 coupled to the gate of the PMOS transistor 522.

[0059] The sampling clock signal 518 is generated from the input signal 502 which is an in-phase version of the clock signal input to the phase interpolator circuit 500. In the illustrated example, the sampling clock signal 518 is obtained from an inverting NAND gate 516 which gates the input signal 502 with a delayed version 514 of the input signal 502. The resulting sampling clock signal 518 output by the NAND gate 516 turns on the PMOS transistor 522 at a time point 604 occurring after the start of the pulse 602 based on the delay introduced by the delay element 512. When the PMOS transistor 522 is turned on, the voltage 608 across the holding capacitor 524 follows the voltage 606 of the common output 510. The PMOS transistor 522 is turned off at the end of the pulse 602. The sampling clock signal 518 is configured to enable charging of the holding capacitor 524 such that the voltage across the holding capacitor 524 represents the peak voltage of the common output 510 of the driver circuits 300 , 320 when the PMOS transistor 522 is turned off.

[0060] In the illustrated example, the calibration circuit 520 includes a comparator 526 that compares the sampled peak voltage 542 to a reference voltage level 544. The reference voltage level 544 represents a minimum voltage level 614 that will indicate an optimal rise time for the common output 510 of the driver circuits 300, 320. When the rise time of the common output 510 of the driver circuits 300, 320 is slower than required to accommodate the duration of the pulse 602, the sampled peak voltage 542 fails to reach the reference voltage level 544. The output 546 of the comparator 526 can be used to control the operation of the counter 528. In one example, the output 546 of the comparator 526 is in a first signaling state that enables the counter 528 to count when the sampled peak voltage 542 is less than the reference voltage level 544, and in a second signaling state that disables the counter 528 when the sampled peak voltage 542 equals or exceeds the reference voltage level 544. In some implementations, the delay element 512 is configured to generate a delay that prevents the PMOS transistor 522 from turning on until a time 612 at which the voltage of the common output 510 has reached or exceeded the previous peak voltage level 610. In these latter implementations, the calibration circuit 520 can ensure that the counter 528 is not immediately re-enabled due to early sampling of the common output 510 within the duration of the pulse 602.

[0061] In the illustrated example, the output of the counter provides a 5-bit count value 538, which is used to configure the digitally controlled voltage source 530. The 5-bit count value 538 is used to control the voltage drop across an N-type metal oxide semiconductor (NMOS) transistor 532, and the voltage on the drain of the NMOS transistor 532 defines the bias voltage 534 Vbp of the bias control transistors 506a, 508a. The calibration circuit 520 also defines the bias voltage 536 (Vbn) of the bias control transistors 506b, 508b. Other types of digitally controlled voltage sources 530 may be used.

[0062] In the illustrated example, when the counter 528 is enabled, the counter 528 is incremented by the counter clock signal 540. The counter 528 may ignore the counter clock signal 540 when it is disabled. The operation of the comparator 526 and the counter clock signal 540 can achieve automatic control of each cycle of the calibration process. In some specific implementations, the counter clock signal 540 may have a frequency less than half of the minimum frequency expected for the input signal 502 received by the first driver circuit 300. In some instances, the counter clock signal 540 has a frequency that is one order of magnitude slower than the minimum frequency expected for the input signal 502. In these specific implementations, calibration begins when the counter 528 is reset to zero, resulting in the slowest rise time and a low sampled peak voltage 542. The comparator 526 detects that the sampled peak voltage 542 is less than the reference voltage level 544 and enables the counter 528. Counter 528 then increments after each cycle of counter clock signal 540 until comparator 526 detects that sampled peak voltage 542 is equal to or greater than reference voltage level 544 and disables counter 528. The 5-bit count value 538 may be locked until a recalibration is performed.

[0063] In some implementations, a controller in a receiver may cause the phase interpolator circuit 500 to be calibrated for multiple possible input clock frequencies. The controller may cause a first frequency to be provided as an input to the phase interpolator circuit 500, reset the counter 528, and wait until the 5-bit count value 538 is locked. The controller may capture the 5-bit count value 538 and store it as a code associated with the first frequency. The controller may perform this calibration process for multiple clock frequencies, and may maintain multiple codes associated with different input clock frequencies. In some instances, when the receiving device is configured to operate at the selected clock frequency, the controller may directly load the counter 528.

[0064] Figure 7 is a flow chart illustrating an example of a method 700 for operating a phase interpolator circuit. In one example, the phase interpolator circuit corresponds to Figure 5Phase interpolator circuit 500 of the present invention. Method 700 may be implemented in a receiver coupled to a data communication link. At block 702, a sampling circuit may be used to capture a sample of an output of the phase interpolator circuit. A delay circuit may be configured to delay a sample performed by the sampling circuit. At block 704, a comparison signal may be provided or generated. In one example, the comparison signal indicates whether the voltage of the sample exceeds a reference voltage. At block 706, a control signal is generated. The control signal may be responsive to the comparison signal and may be configured to control an operating point of the phase interpolator circuit.

[0065] In some examples, the output signal generated by the phase interpolator circuit represents a weighted sum of a pair of input signals received by the phase interpolator circuit. The pair of input signals may be received by a pair of driver circuits. The driver circuits may be configured to concurrently drive the output of the phase interpolator circuit. In one example, the input signal is a phase-shifted version of a clock signal received by the phase interpolator circuit. The input signals may have the same frequency and may be phase-shifted relative to each other.

[0066] In various implementations, the comparison signal may be used to control the operation of the counter. For example, the counter may be enabled or otherwise enabled to count cycles of the clock signal until the comparison signal indicates that the voltage of the sample exceeds the reference voltage. The output of the counter may be used to configure one or more bias circuits in the pair of driver circuits. In some instances, the output of the counter is configured to configure one or more current sources of the pair of driver circuits. In some instances, the output of the counter configures a digitally controlled voltage source that controls an operating point for the pair of driver circuits.

[0067] The driver circuits in the pair of driver circuits may each have one or more load transistors configured to control a corresponding level of current contributing to the output signal. The operating point of the phase interpolator circuit may be one of a plurality of operating points associated with different frequencies of the input signal received by the phase interpolator circuit. The different frequencies may be defined by design or may be accommodated when encountered. The sampling circuit may be configured to capture a sample during a pulse in the input signal received by the phase interpolator circuit.

[0068] The devices and methods described herein and shown in the accompanying drawings may be implemented using various blocks, modules, components, circuits, steps, processes, algorithms, etc. (collectively referred to as "elements"). These elements may be implemented using electronic hardware, computer software, or any combination thereof. Whether such elements are implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system.

[0069] According to certain aspects of his disclosure, a device configured to operate as a phase interpolator circuit includes: a circuit or module configured to capture a sample of the output of the device, a circuit or module configured to provide a comparison signal indicating whether the voltage of the sample exceeds a reference voltage; and a circuit or module configured to generate a control signal responsive to the comparison signal and configured to control the operating point of the device. The circuit or module configured to capture the sample may include a delay circuit configured to delay the sampling performed by the sampling circuit. In some specific implementations, the sampling circuit is configured to capture the sample during a pulse in the input signal received by the device. The device may also include a circuit or module configured to generate an output signal representing a weighted sum of a pair of input signals received by the device. The circuit or module configured to generate the output signal may include a pair of drive circuits configured to concurrently drive the output of the device. The pair of input signals may have the same frequency and may be phase-shifted relative to each other.

[0070] In some examples, the circuit or module configured to generate an output signal includes a counter responsive to the comparison signal. The output of the counter can be used to configure one or more bias circuits in the pair of driver circuits. In one example, the output of the counter is configured to configure one or more current sources of the pair of driver circuits. In another example, the output of the counter configures a digitally controlled voltage source that controls an operating point for the pair of driver circuits. The counter can be configured to count the cycles of the clock signal until the comparison signal indicates that the voltage of the sample exceeds the reference voltage.

[0071] In some examples, each of the driver circuits includes one or more load transistors configured to control a corresponding level of current contributing to the output signal.

[0072] In some examples, the operating point of the device is configured for the frequency of the pair of input signals.The operating point of the device may be one of a plurality of operating points configured for different frequencies of the input signals received by the device.

[0073] According to at least one example described herein, a phase interpolator has: a sampling circuit configured to capture a sample of the output of the phase interpolator; a delay circuit configured to delay the sampling performed by the sampling circuit; a comparator configured to provide a comparison signal indicating whether the voltage of the sample exceeds a reference voltage; and a counter responsive to the comparison signal and configured to provide an output that controls an operating point of the phase interpolator. The phase interpolator may also have a pair of drive circuits configured to concurrently drive the output of the phase interpolator. The output of the counter can be used to configure one or more bias circuits in the pair of drive circuits. In some instances, the output of the counter is configured to configure one or more current sources of the pair of drive circuits. In some instances, the output of the counter configures a digitally controlled voltage source that controls an operating point for the pair of drive circuits.

[0074] In some instances, the pair of drive circuits is coupled to a pair of input signals having the same frequency and phase shifted relative to each other. The pair of drive circuits may be configured to generate a weighted sum of the pair of input signals. Each of the pair of drive circuits may include one or more load transistors configured to control the level of current contributed by the drive circuit to the output of the phase interpolator. The operating point of the phase interpolator may be configured for the frequency of the pair of input signals. The operating point of the phase interpolator may be one of a plurality of operating points configured for different frequencies of the input signal received by the phase interpolator. The sampling circuit may be configured to capture a sample during a pulse in the input signal received by the phase interpolator. The counter may be configured to count the cycles of the clock signal until the comparison signal indicates that the voltage of the sample exceeds the reference voltage.

[0075] Some specific implementation examples are described in the following numbered clauses:

[0076] 1. A phase interpolator comprising: a sampling circuit configured to capture a sample of an output of the phase interpolator; a delay circuit configured to delay a sample performed by the sampling circuit; a comparator configured to provide a comparison signal indicating whether a voltage of the sample exceeds a reference voltage; and a counter responsive to the comparison signal and configured to provide an output that controls an operating point of the phase interpolator.

[0077] 2. The phase interpolator of clause 1, further comprising: a pair of drive circuits configured to concurrently drive the outputs of the phase interpolator.

[0078] 3. A phase interpolator according to clause 2, wherein the output of the counter configures one or more bias circuits in the pair of drive circuits.

[0079] 4. A phase interpolator according to clause 2 or clause 3, wherein the output of the counter is configured to configure one or more current sources of the pair of drive circuits.

[0080] 5. A phase interpolator according to clause 2 or clause 3, wherein the output of the counter configures a digitally controlled voltage source that controls an operating point for the pair of drive circuits.

[0081] 6. A phase interpolator according to any one of clauses 2 to 5, wherein the pair of drive circuits are coupled to a pair of input signals having the same frequency and being phase shifted relative to each other, and wherein the pair of drive circuits are configured to generate a weighted sum of the pair of input signals.

[0082] 7. A phase interpolator according to clause 6, wherein each of the pair of drive circuits includes one or more load transistors, and the one or more load transistors are configured to control the level of current contributed by each drive circuit to the output of the phase interpolator.

[0083] 8. A phase interpolator according to clause 6 or clause 7, wherein the operating point of the phase interpolator is configured for the frequency of the pair of input signals.

[0084] 9. A phase interpolator according to any one of clauses 1 to 8, wherein the operating point of the phase interpolator is one of a plurality of operating points configured for different frequencies of an input signal received by the phase interpolator.

[0085] 10. A phase interpolator according to any of clauses 1 to 9, wherein the sampling circuit is configured to capture the sample during a pulse in an input signal received by the phase interpolator.

[0086] 11. A phase interpolator according to any of clauses 1 to 10, wherein the counter is configured to count cycles of a clock signal until the comparison signal indicates that the voltage of the sample exceeds the reference voltage.

[0087] 12. An apparatus comprising: means for capturing a sample of an output of the apparatus, the means comprising a delay circuit configured to delay a sample taken by a sampling circuit; means for providing a comparison signal indicating whether a voltage of the sample exceeds a reference voltage; and means for generating a control signal responsive to the comparison signal and configured to control an operating point of the apparatus.

[0088] 13. The device according to clause 12 further includes: a component for generating an output signal representing a weighted sum of a pair of input signals received by the device, the component comprising a pair of drive circuits configured to drive the output of the device concurrently, wherein the pair of input signals have the same frequency and are phase-shifted relative to each other.

[0089] 14. The apparatus of clause 13, wherein the means for generating the control signal comprises a counter responsive to the comparison signal, wherein an output of the counter configures one or more bias circuits in the pair of drive circuits.

[0090] 15. The apparatus of clause 14, wherein the output of the counter is configured to configure one or more current sources of the pair of drive circuits.

[0091] 16. The apparatus of clause 14, wherein the output of the counter configures a digitally controlled voltage source that controls an operating point for the pair of drive circuits.

[0092] 17. Apparatus according to any of clauses 14 to 16, wherein the counter is configured to count cycles of a clock signal until the comparison signal indicates that the voltage of the sample exceeds the reference voltage.

[0093] 18. An apparatus according to any of clauses 13 to 17, wherein each driver circuit of the pair of driver circuits comprises one or more load transistors configured to control a corresponding level of current contributing to the output signal.

[0094] 19. An apparatus as claimed in any of clauses 13 to 18, wherein the operating point of the apparatus is configured for the frequency of the pair of input signals.

[0095] 20. An apparatus as recited in any of clauses 12 to 19, wherein the operating point of the apparatus is one of a plurality of operating points configured for different frequencies of an input signal received by the apparatus.

[0096] 21. An apparatus according to any one of clauses 12 to 20, wherein the sampling circuit is configured

[0097] The sample is captured during a pulse in an input signal received by the device.

[0098] 22. A method for operating a phase interpolator circuit, the method comprising: capturing a sample of the output of the phase interpolator circuit using a sampling circuit and a delay circuit configured to delay the sampling performed by the sampling circuit; providing a comparison signal indicating whether the voltage of the sample exceeds a reference voltage; and generating a control signal responsive to the comparison signal and configured to control an operating point of the phase interpolator circuit.

[0099] 23. The method according to clause 22 further includes: using a pair of drive circuits to generate an output signal representing a weighted sum of a pair of input signals received by the phase interpolator circuit, wherein the pair of drive circuits are configured to concurrently drive the output of the phase interpolator circuit, wherein the pair of input signals have the same frequency and are phase-shifted relative to each other.

[0100] 24. The method of clause 23, wherein generating the control signal comprises using the comparison signal to control operation of a counter, wherein an output of the counter configures one or more bias circuits in the pair of driver circuits.

[0101] 25. The method of clause 24, wherein the output of the counter is configured to configure one or more current sources of the pair of drive circuits.

[0102] 26. The method of clause 24, wherein the output of the counter configures a digitally controlled voltage source that controls an operating point for the pair of drive circuits.

[0103] 27. The method of any of clauses 24 to 26, further comprising causing the counter to count cycles of a clock signal until the comparison signal indicates that the voltage of the sample exceeds the reference voltage.

[0104] 28. A method according to any of clauses 23 to 27, wherein each driver circuit of the pair of driver circuits comprises one or more load transistors configured to control a corresponding level of current contributing to the output signal.

[0105] 29. A method according to any of clauses 22 to 28, wherein the operating point of the phase interpolator circuit is one of a plurality of operating points associated with different frequencies of an input signal received by the phase interpolator circuit.

[0106] 30. A method according to any of clauses 22 to 29, wherein the sampling circuit is configured to capture the sample during a pulse in an input signal received by the phase interpolator circuit.

[0107] As used herein, a phrase referring to "at least one of" a list of items refers to any combination of those items (including single members). As an example, "at least one of a, b, or c" is intended to cover a, b, c, ab, ac, bc, and abc, as well as any combination with multiple identical elements (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc, or any other ordering of a, b, and c).

[0108] The present disclosure is provided to enable any person skilled in the art to make or use the various aspects of the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the examples and designs described herein, but to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A phase interpolator, comprising: a sampling circuit configured to capture samples of an output of the phase interpolator; a delay circuit configured to delay sampling by the sampling circuit; a comparator configured to provide a comparison signal indicating whether the voltage of the sample exceeds a reference voltage; and A counter is responsive to the comparison signal and configured to provide an output that controls an operating point of the phase interpolator.

2. The phase interpolator according to claim 1, further comprising: A pair of drive circuits are configured to concurrently drive the outputs of the phase interpolator.

3. The phase interpolator of claim 2, wherein the output of the counter configures one or more bias circuits in the pair of drive circuits.

4. The phase interpolator of claim 2, wherein the output of the counter is configured to configure one or more current sources of the pair of drive circuits.

5. The phase interpolator of claim 2, wherein the output of the counter configures a digitally controlled voltage source that controls an operating point for the pair of drive circuits.

6. The phase interpolator of claim 2, wherein the pair of drive circuits are coupled to a pair of input signals having the same frequency and being phase shifted relative to each other, and wherein the pair of drive circuits are configured to generate a weighted sum of the pair of input signals.

7. A phase interpolator according to claim 6, wherein each of the pair of drive circuits includes one or more load transistors, and the one or more load transistors are configured to control the level of current contributed by each drive circuit to the output of the phase interpolator.

8. The phase interpolator of claim 6, wherein the operating point of the phase interpolator is configured for the frequency of the pair of input signals.

9. The phase interpolator of claim 1, wherein the operating point of the phase interpolator is one of a plurality of operating points configured for different frequencies of an input signal received by the phase interpolator.

10. The phase interpolator of claim 1, wherein the sampling circuit is configured to capture the sample during a pulse in an input signal received by the phase interpolator.

11. The phase interpolator of claim 1, wherein the counter is configured to count cycles of a clock signal until the comparison signal indicates that the voltage of the sample exceeds the reference voltage.

12. An apparatus comprising: means for capturing a sample of an output of the apparatus, the means comprising a delay circuit configured to delay a sample taken by a sampling circuit; means for providing a comparison signal indicating whether the voltage of the sample exceeds a reference voltage; and Means for generating a control signal responsive to the comparison signal and configured to control an operating point of the apparatus.

13. The apparatus according to claim 12, further comprising: Means for generating an output signal representing a weighted sum of a pair of input signals received by the apparatus, the means comprising a pair of drive circuits configured to concurrently drive the output of the apparatus, wherein the pair of input signals have the same frequency and are phase shifted relative to each other.

14. The apparatus of claim 13, wherein the means for generating the control signal comprises a counter responsive to the comparison signal, wherein an output of the counter configures one or more bias circuits in the pair of drive circuits.

15. The apparatus of claim 14, wherein the output of the counter is configured to configure one or more current sources of the pair of drive circuits.

16. The apparatus of claim 14, wherein the output of the counter configures a digitally controlled voltage source that controls an operating point for the pair of drive circuits.

17. The apparatus of claim 14, wherein the counter is configured to count cycles of a clock signal until the comparison signal indicates that the voltage of the sample exceeds the reference voltage.

18. The apparatus of claim 13, wherein each of the pair of driver circuits comprises one or more load transistors configured to control a corresponding level of current contributing to the output signal.

19. The apparatus of claim 13, wherein the operating point of the apparatus is configured for the frequency of the pair of input signals.

20. The apparatus of claim 12, wherein the operating point of the apparatus is one of a plurality of operating points configured for different frequencies of an input signal received by the apparatus.

21. The apparatus of claim 12, wherein the sampling circuit is configured to capture the sample during a pulse in an input signal received by the apparatus.

22. A method for operating a phase interpolator circuit, comprising: capturing samples of an output of the phase interpolator circuit using a sampling circuit and a delay circuit configured to delay a sample taken by the sampling circuit; providing a comparison signal indicating whether the voltage of the sample exceeds a reference voltage; as well as A control signal is generated that is responsive to the comparison signal and configured to control an operating point of the phase interpolator circuit.

23. The method according to claim 22, further comprising: An output signal representing a weighted sum of a pair of input signals received by the phase interpolator circuit is generated using a pair of driver circuits configured to concurrently drive the output of the phase interpolator circuit, wherein the pair of input signals have the same frequency and are phase shifted relative to each other.

24. The method of claim 23, wherein generating the control signal comprises: The comparison signal is used to control the operation of a counter, wherein an output of the counter configures one or more bias circuits in the pair of drive circuits.

25. The method of claim 24, wherein the output of the counter is configured to configure one or more current sources of the pair of drive circuits.

26. The method of claim 24, wherein the output of the counter configures a digitally controlled voltage source that controls an operating point for the pair of drive circuits.

27. The method of claim 24, further comprising: The counter is caused to count cycles of a clock signal until the comparison signal indicates that the voltage of the sample exceeds the reference voltage.

28. The method of claim 23, wherein each driver circuit of the pair of driver circuits comprises one or more load transistors configured to control a corresponding level of current contributing to the output signal.

29. The method of claim 22, wherein the operating point of the phase interpolator circuit is one of a plurality of operating points associated with different frequencies of an input signal received by the phase interpolator circuit.

30. The method of claim 22, wherein the sampling circuit is configured to capture the sample during a pulse in an input signal received by the phase interpolator circuit.

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