Register and preparation method thereof

Abstract

The invention discloses a register and a preparation method thereof, and belongs to the technical field of semiconductors. The register comprises a signal input end, a signal output end and a clock control signal end, and further comprises a first transistor, a second transistor, a first phase inverter, a second phase inverter and a third phase inverter. In the first transistor and the second transistor, a grid electrode of one transistor is electrically connected with a clock control signal end through a first phase inverter, a grid electrode of the other transistor is directly and electrically connected with the clock control signal end, in addition, a source electrode of the first transistor is electrically connected with a signal input end, and a source electrode of the second transistor is electrically connected with a signal output end. The drain electrode of the first transistor is electrically connected with the source electrode of the second transistor through the second inverter, and the drain electrode of the second transistor is electrically connected with the signal output end through the third inverter. The register based on the circuit structure is complete in function, relatively simple in structure and relatively low in resource consumption, and the area of the register is favorably reduced.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular, relates to a register and a preparation method thereof. Background Art

[0002] A register is a circuit unit used to latch data in a computing system. Currently, a register contains a large number of transistors, which consumes a lot of resources and occupies a large area. In addition, traditional registers are based on silicon transistors, and the channel layer material of silicon transistors includes single crystal silicon. Although single crystal silicon has a high mobility, its high growth temperature limits its application in the back-end process. Summary of the invention

[0003] The present application provides a register and a method for preparing the same, wherein the register is based on a back-end transistor, aiming to reduce the resource consumption of the register and reduce the area size. In addition, the channel layer material of the back-end transistor is a non-single-crystal silicon material, which eliminates the dependence on silicon materials and can avoid high temperatures, protecting other film layer structures that have been manufactured, thereby allowing the manufacturing method to have a relatively free manufacturing sequence.

[0004] In a first aspect, the present application provides a register, including a signal input terminal, a signal output terminal and a clock control signal terminal, and the register also includes a first transistor, a second transistor, a first inverter, a second inverter and a third inverter. In the first transistor and the second transistor, the gate of one is electrically connected to the clock control signal terminal through the first inverter, and the gate of the other is directly electrically connected to the clock control signal terminal. In addition, the source of the first transistor is electrically connected to the signal input terminal, the drain of the first transistor is electrically connected to the source of the second transistor through the second inverter, and the drain of the second transistor is electrically connected to the signal output terminal through the third inverter.

[0005] In some embodiments, the first inverter includes a third transistor and a fourth transistor, the gate of the third transistor is electrically connected to the gate of the fourth transistor, the source of the third transistor is electrically connected to the first voltage terminal, the source of the fourth transistor is electrically connected to the second voltage terminal, and the drain of the third transistor is electrically connected to the drain of the fourth transistor. The second inverter includes a fifth transistor and a sixth transistor, the gate of the fifth transistor is electrically connected to the gate of the sixth transistor, the source of the fifth transistor is electrically connected to the first voltage terminal, the source of the sixth transistor is electrically connected to the second voltage terminal, and the drain of the fifth transistor is electrically connected to the drain of the sixth transistor. The third inverter includes a seventh transistor and an eighth transistor, the gate of the seventh transistor is electrically connected to the gate of the eighth transistor, the source of the seventh transistor is electrically connected to the first voltage terminal, the source of the eighth transistor is electrically connected to the second voltage terminal, and the drain of the seventh transistor is electrically connected to the drain of the eighth transistor.

[0006] In some embodiments, the register further includes a substrate, and the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are discretely arranged on a surface of the substrate.

[0007] In some embodiments, the register further includes a substrate, and the first transistor, the second transistor, the first inverter, the second inverter, and the third inverter are arranged on the substrate. The first inverter, the second inverter, and the third inverter each include two transistors, and along a direction perpendicular to the substrate, at least one of the first inverter, the second inverter, and the third inverter is an inverter with a stacked structure, and the two transistors in the inverter with a stacked structure are stacked.

[0008] In some embodiments, the first transistor, the second transistor, the first inverter, the second inverter, and the third inverter are discretely arranged on a surface of the substrate.

[0009] In some embodiments, the first inverter, the second inverter, and the third inverter are all inverters having a stacked structure.

[0010] In some embodiments, the first transistor and the second transistor are both N-type transistors.

[0011] On the other hand, the present application also provides a method for preparing a register, the register comprising a signal input terminal, a signal output terminal and a clock control signal terminal, the preparation method comprising:

[0012] A first transistor, a second transistor, a first inverter, a second inverter, and a third inverter are formed on a substrate.

[0013] Among them, in the first transistor and the second transistor, the gate of one is electrically connected to the clock control signal end through the first inverter, and the gate of the other is directly electrically connected to the clock control signal end. In addition, the source of the first transistor is electrically connected to the signal input end, the drain of the first transistor is electrically connected to the source of the second transistor through the second inverter, and the drain of the second transistor is electrically connected to the signal output end through the third inverter.

[0014] In some embodiments, the first inverter includes a third transistor and a fourth transistor, the second inverter includes a fifth transistor and a sixth transistor, and the third inverter includes a seventh transistor and an eighth transistor.

[0015] A first transistor, a second transistor, a first inverter, a second inverter and a third inverter are formed on a substrate, including:

[0016] forming gates of eight transistors, namely, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor;

[0017] forming an active layer of eight transistors, namely, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor;

[0018] Sources and drains of eight transistors, namely, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor, are formed.

[0019] In some embodiments, along a direction perpendicular to the substrate, at least one of the first inverter, the second inverter, and the third inverter is an inverter with a stacked structure, and the inverter with the stacked structure includes a lower transistor and an upper transistor.

[0020] The inverter having the stacked structure is formed, comprising:

[0021] forming the source and drain of the transistor below;

[0022] forming a first active layer of a lower transistor;

[0023] forming a common gate of the lower transistor and the upper transistor;

[0024] forming a second active layer of the upper transistor, wherein the second active layer is located on a side of the common gate away from the substrate;

[0025] The source and drain of the upper transistor are formed.

[0026] In an embodiment of the present application, the register includes a first transistor, a second transistor, a first inverter, a second inverter, and a third inverter. In the first transistor and the second transistor, the gate of one is electrically connected to the clock control signal terminal through the first inverter, and the gate of the other is directly electrically connected to the clock control signal terminal, thereby controlling one of the two transistors to turn on and the other to turn off through the clock control signal. In addition, the source of the first transistor is electrically connected to the signal input terminal, the drain of the first transistor is electrically connected to the source of the second transistor through the second inverter, and the drain of the second transistor is electrically connected to the signal output terminal through the third inverter.

[0027] In a clock scan cycle, when the first transistor switches from the open state to the closed state, the second transistor switches from the closed state to the open state. At this time, the gate capacitor of the second inverter latches the signal collected by the signal input terminal, and the signal output terminal outputs the signal collected by the signal input terminal at this time. When the first transistor switches from the closed state to the open state, the second transistor switches from the open state to the closed state. At this time, the gate capacitor of the third inverter latches the signal before the state of the second transistor is switched, that is, the signal output terminal continues to maintain the signal output before the state of the second transistor is switched. Until the next clock scan cycle arrives, the above process is repeated again, thereby realizing the function of the register. The structure of the register provided in the embodiment of the present application is relatively simple, and the resource consumption is small, which is conducive to reducing the area of ​​the register.

[0028] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0030] Figure 1 A schematic diagram of a circuit structure of a register provided in an embodiment of the present application;

[0031] Figure 2 A schematic diagram of the circuit structure of another register provided in an embodiment of the present application;

[0032] Figure 3 Based on the embodiments of the present application Figure 1 Waveform diagram of the register shown;

[0033] Figure 4 A schematic diagram of the circuit structure of an inverter provided in an embodiment of the present application;

[0034] Figure 5 A partial cross-sectional schematic diagram of a register provided in an embodiment of the present application;

[0035] Figure 6 A partial cross-sectional schematic diagram of another register provided in an embodiment of the present application;

[0036] Figure 7 A flowchart of a method for preparing a register provided in an embodiment of the present application;

[0037] Figure 8 to Figure 11 for Figure 7 The steps of the preparation method shown;

[0038] Fig.12A flowchart of another method for preparing a register provided in an embodiment of the present application;

[0039] Figures 13 to 20 for Fig.12 Diagram of each step of the preparation method shown. DETAILED DESCRIPTION

[0040] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0041] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, ie, meaning "including, but not limited to."

[0042] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

[0043] When describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. For example, when describing some embodiments, the term "connection" may be used to indicate that two or more components are in direct physical or electrical contact with each other.

[0044] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0045] It will be understood that when a layer or an element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0046] Exemplary embodiments are described herein with reference to cross-sectional views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include deviations in shape due to, for example, manufacturing. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0047] Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0048] At present, a register contains a large number of transistors, which consumes a lot of resources and causes the register to occupy a large area. For example, a typical register is implemented based on a latch. A typical D latch includes 4 NAND gate circuits, each of which includes 4 transistors, and a typical register consists of 2 D latches and 1 inverter, where the inverter includes 2 transistors, that is, a typical register includes 34 transistors. This results in a large consumption of register resources and a large area overhead. In addition, traditional registers are based on silicon transistors, and the channel layer material of silicon transistors includes single crystal silicon. Although single crystal silicon has a high mobility, its excessively high growth temperature limits its application in back-end processes.

[0049] In order to reduce resource consumption and area size of a register, the present application provides a register based on a back-end transistor, and a preparation method thereof has a relatively free manufacturing sequence.

[0050] like Figure 1-2 As shown, Figure 1 A circuit structure diagram of a register provided in an embodiment of the present application is shown in FIG. Figure 2 A schematic diagram of the circuit structure of another register provided in an embodiment of the present application.

[0051] like Figure 1 and Figure 2 As shown, the register 10 includes a signal input terminal IN, a signal output terminal OUT and a clock control signal terminal CLK. The signal input terminal IN is used to receive the signal to be collected, the signal output terminal OUT is used to output the signal collected by the register 10, and the clock control signal terminal CLK is used to receive the clock scanning signal and control the period of the register 10 collecting the signal.

[0052] The register 10 further includes a first transistor 11, a second transistor 12, a first inverter 21, a second inverter 22 and a third inverter 23. Among them, in the first transistor 11 and the second transistor 12, the gate G of one is electrically connected to the clock control signal terminal CLK through the first inverter 21, and the gate G of the other is directly electrically connected to the clock control signal terminal CLK.

[0053] For example, Figure 1 As shown, the gate G of the first transistor 11 is electrically connected to the clock control signal terminal CLK through the first inverter 21, and the gate G of the second transistor 12 is directly electrically connected to the clock control signal terminal CLK. Figure 2 As shown, the gate G of the second transistor 12 is electrically connected to the clock control signal terminal CLK through the first inverter 21, and the gate G of the first transistor 11 is directly electrically connected to the clock control signal terminal CLK.

[0054] In addition, the source S of the first transistor 11 is electrically connected to the signal input terminal IN, the drain D of the first transistor 11 is electrically connected to the source S of the second transistor 12 through the second inverter 22, and the drain D of the second transistor 12 is electrically connected to the signal output terminal OUT through the third inverter 23.

[0055] by Figure 1 Taking the circuit structure of the register 10 shown as an example, within a scanning cycle of the clock scanning signal received by the clock control signal terminal CLK, when the clock scanning signal is at a low level, under the action of the first inverter 21, the signal received by the gate G of the first transistor 11 is at a high level, the first transistor 11 is turned on, and the signal D collected by the signal input terminal IN is transmitted to the node M through the first transistor 11, at which time the signal of the node M is D, and then transmitted to the node N through the second inverter 22, at which time the signal of the node N is D negative. At this time, since the signal received by the gate G of the second transistor 12 is at a low level, the second transistor 12 is in a closed state, and under the action of the gate capacitance (parasitic capacitance) of the third inverter 23, the node P will latch and maintain the signal before the second transistor 12 is turned off, and the corresponding node Q will also maintain the previous signal. That is, at this time, the signal output by the signal output terminal OUT has nothing to do with the signal collected by the signal input terminal IN, and the signal output by the signal output terminal OUT still maintains the signal of the node Q before the second transistor 12 is turned off.

[0056] When the clock scan signal becomes a high level, under the action of the first inverter 21, the signal received by the gate G of the first transistor 11 is a low level, the first transistor 11 is turned off, and the signal collected by the signal input terminal IN cannot be transmitted to the node M, and under the action of the gate capacitance (parasitic capacitance) of the first inverter 11, the node M will latch and maintain the signal before the first transistor 11 is turned off, that is, the signal of the node M is still D. The corresponding node N will also maintain the previous signal, that is, the signal of the node N is still D non. At this time, since the signal received by the gate G of the second transistor 12 is a high level, the second transistor 12 is turned on, and the signal D non of the node N will be transmitted to the node P through the second transistor 12, and the signal of the node P is D non, and the signal of the node P is transmitted to the node Q through the third inverter 23, and the signal of the node Q is D, and the signal of the node Q is output through the signal output terminal OUT, that is, the signal output terminal OUT outputs the signal D.

[0057] In other words, when the clock scan signal changes from a low level to a high level, the node M latches the signal collected by the signal input terminal IN, and the signal output by the signal output terminal OUT is the signal collected by the signal input terminal IN at this time. When the clock scan signal changes from a high level to a low level, regardless of whether the signal collected by the signal input terminal IN changes at this time, the second transistor 12 is turned off, and the signal output by the signal output terminal OUT is still the output signal before the second transistor 12 is turned off. That is, at the rising edge of the clock scan signal, the register 10 collects and outputs the signal, and at the falling edge of the clock scan signal, the signal output by the register 10 is consistent with the signal collected by the signal input terminal IN at the rising edge of the clock scan signal.

[0058] For example, Figure 3 As shown, Figure 3 Provide a method based on the embodiment of the present application Figure 1 The waveform of the register shown in the figure, where the wave line CLK represents the clock scanning signal, and one scanning cycle is 1ms. The wave line D represents the signal collected by the signal input terminal IN, and the wave line Q represents the signal output by the signal output terminal OUT. The 0 marked on each wave line represents a low level, and the 1 marked on each wave line represents a high level. According to the working principle described above, Figure 3 As shown, at the rising edge of the clock scanning signal, i.e., the wave line CLK, the register 10 performs signal acquisition, and the signal output by the signal output terminal OUT is the signal D acquired by the signal input terminal IN at this time. At the falling edge, the register 10 latches and holds the signal acquired at the rising edge. Until the rising edge of the next clock scanning cycle arrives, the above process is repeated, thereby realizing the function of the register.

[0059] Similarly, if Figure 2The register 10 shown collects signals at the falling edge of the clock scan signal, and at the rising edge, it still keeps the signals collected and latched at the falling edge until the falling edge of the next scan cycle arrives, and then repeats the above process. No further description is given here.

[0060] The register 10 provided in the embodiment of the present application has complete functions and a simpler structure compared with the related art, which saves resource consumption, reduces costs, and is conducive to reducing the area of ​​the register.

[0061] In some embodiments, taking the first inverter 21 as an example, Figure 4 As shown, Figure 4 The circuit structure diagram of the inverter provided in the embodiment of the present application, the first inverter 21 includes a third transistor 13 and a fourth transistor 14, the gate G of the third transistor 13 is electrically connected to the gate G of the fourth transistor 14, and the two are connected to serve as the input terminal of the first inverter 21. The source S of the third transistor 13 is electrically connected to the first voltage terminal, and the source S of the fourth transistor 14 is electrically connected to the second voltage terminal. The drain D of the third transistor 13 is electrically connected to the drain D of the fourth transistor 14, and the two are connected to serve as the output terminal of the first inverter 21. Among them, one of the first voltage terminal and the second voltage terminal is the power supply voltage VDD, and the other is the ground voltage GND, and the two need to match the conductivity type of the third transistor 13 and the fourth transistor 14. For example, Figure 4 The third transistor 13 is a P-type transistor, the fourth transistor 14 is an N-type transistor, the first voltage terminal is a power supply voltage VDD, and the second voltage terminal is a ground voltage GND.

[0062] Similarly, the second inverter 22 includes a fifth transistor 15 and a sixth transistor 16, wherein the gate G of the fifth transistor 15 is electrically connected to the gate G of the sixth transistor 16, and the two are connected to serve as the input terminal of the second inverter 22. The source S of the fifth transistor 15 is electrically connected to the first voltage terminal, and the source S of the sixth transistor 16 is electrically connected to the second voltage terminal. The drain D of the fifth transistor 15 is electrically connected to the drain D of the sixth transistor 16, and the two are connected to serve as the output terminal of the second inverter 22.

[0063] The third inverter 23 includes a seventh transistor 17 and an eighth transistor 18, wherein the gate G of the seventh transistor 17 is electrically connected to the gate G of the eighth transistor 18, and the two are connected to serve as an input terminal of the third inverter 23. The source S of the seventh transistor 17 is electrically connected to the first voltage terminal, and the source S of the eighth transistor 18 is electrically connected to the second voltage terminal. The drain S of the seventh transistor 17 is electrically connected to the drain D of the eighth transistor 18, and the two are connected to serve as an output terminal of the third inverter 23.

[0064] In the embodiment of the present application, the first inverter 21, the second inverter 22 and the third inverter 23 each include two transistors. Based on this, the register 10 includes 8 transistors, which greatly saves resource consumption, reduces costs, and is conducive to reducing the area of ​​the register 10 compared with 34 transistors in the related art.

[0065] The register 10 further includes a substrate 101, and the first transistor 11, the second transistor 12, the first inverter 21, the second inverter 22 and the third inverter 23 of the register 10 are all disposed on the substrate 101. In addition, in some embodiments, the first transistor 11, the second transistor 12, the first inverter 21, the second inverter 22 and the third inverter 23 are discretely arranged on the surface of the substrate 101.

[0066] For example, in some embodiments, Figure 5 As shown, Figure 5 A partial cross-sectional schematic diagram of a register provided in an embodiment of the present application, wherein a first transistor 11 , a second transistor 12 , a third transistor 13 , a fourth transistor 14 , a fifth transistor 15 , a sixth transistor 16 , a seventh transistor 17 , and an eighth transistor 18 are all discretely arranged on the surface of the substrate 101 . Figure 5 Only partial film layer structures of the third transistor 13 and the fourth transistor 14 are shown.

[0067] That is, in the embodiment of the present application, the first inverter 21, the second inverter 22 and the third inverter 23 all adopt a planar structure, the two transistors included in each inverter are flattened on the substrate 101, and the eight transistors included in the register 10 are flattened on the substrate 101. Based on this, in the embodiment of the present application, the area overhead of the register 10 is equivalent to the area occupied by the eight transistors flattened on the substrate 101.

[0068] For example, in some embodiments, Figure 6 As shown, Figure 6 A partial cross-sectional schematic diagram of another register provided in an embodiment of the present application, wherein at least one of the first inverter 21, the second inverter 22 and the third inverter 23 is an inverter with a stacked structure, and an inverter with a stacked structure refers to an inverter in which two transistors are stacked.

[0069] The stacking structure is as follows Figure 6 As shown, taking the third transistor 13 and the fourth transistor 14 of the first inverter 21 as an example, in the direction perpendicular to the substrate 101, the fourth transistor 14 is located above the third transistor 13, that is, on the substrate 101, the area overhead of the first inverter 21 is equivalent to the area occupied by one transistor flat on the substrate 101.

[0070] Exemplarily, in some embodiments, the first inverter 21, the second inverter 22, and the third inverter 23 are all inverters with a stacked structure. That is, the area overhead of the first inverter 21, the second inverter 22, and the third inverter 23 on the substrate 101 is equivalent to the area occupied by one transistor laid flat on the substrate 101. Based on this, in the embodiment of the present application, the area overhead of the register 10 is equivalent to the area occupied by five transistors laid flat on the substrate 101.

[0071] Under the premise of ensuring that the functions of the register 10 are perfect, the embodiment of the present application further reduces the area overhead and the area size of the register 10, which is conducive to the miniaturization of the device.

[0072] In some embodiments, the first transistor 11 and the second transistor 12 are both N-type transistors. The materials of the N-type transistor include, but are not limited to, wide bandgap semiconductor materials such as indium gallium zinc oxide. The off-state leakage current of the N-type transistor is lower, which prevents the signal latched at the node M under the gate capacitance of the second inverter 22 from being affected by the signal collected by the signal input terminal IN. Similarly, the signal latched at the node P under the gate capacitance of the third inverter 23 can be prevented from being affected by the signal of the node N, thereby ensuring a normal latching function.

[0073] On the other hand, the present application also provides a method for preparing a register.

[0074] Based on the back-end process, the register 10 prepared by the preparation method provided in the embodiment of the present application includes a signal input terminal IN, a signal output terminal OUT and a clock control signal terminal CLK. The register 10 also includes a substrate 101. The preparation method includes:

[0075] A first transistor 11, a second transistor 12, a first inverter 21, a second inverter 22 and a third inverter 23 are formed on a substrate 101. Exemplarily, the first transistor 11 and the second transistor 12 are both N-type transistors.

[0076] Among them, in the first transistor 11 and the second transistor 12, the gate G of one is electrically connected to the clock control signal terminal CLK through the first inverter 21, and the gate G of the other is directly electrically connected to the clock control signal terminal CLK. In addition, the source S of the first transistor 11 is electrically connected to the signal input terminal IN, the drain D of the first transistor 11 is electrically connected to the source S of the second transistor 12 through the second inverter 22, and the drain D of the second transistor 12 is electrically connected to the signal output terminal OUT through the third inverter 23.

[0077] Exemplarily, in some embodiments, the first inverter 21 includes a third transistor 13 and a fourth transistor 14, one of which is an N-type transistor and the other is a P-type transistor. The second inverter 22 includes a fifth transistor 15 and a sixth transistor 16, one of which is an N-type transistor and the other is a P-type transistor. The third inverter 23 includes a seventh transistor 17 and an eighth transistor 18, one of which is an N-type transistor and the other is a P-type transistor.

[0078] Illustratively, in some embodiments, the first transistor 11 , the second transistor 12 , the third transistor 13 , the fourth transistor 14 , the fifth transistor 15 , the sixth transistor 16 , the seventh transistor 17 , and the eighth transistor 18 are discretely arranged on the surface of the substrate 101 .

[0079] Based on this, Figure 7 As shown, Figure 7 A preparation method flow chart is provided for the embodiment of the present application. Figure 8 to Figure 11 for Figure 7 Each step diagram of the manufacturing method is shown. Here, each step diagram is explained by taking the formation of the third transistor 13 and the fourth transistor 14 related structural film layers as an example.

[0080] like Figure 7 As shown, the preparation method includes the following steps S11 to S13:

[0081] Step S11: Figure 8 As shown, gates G of eight transistors, namely, a first transistor 11 , a second transistor 12 , a third transistor 13 , a fourth transistor 14 , a fifth transistor 15 , a sixth transistor 16 , a seventh transistor 17 and an eighth transistor 18 , are formed on a substrate 101 .

[0082] Afterwards, if Fig. 9 As shown, a dielectric layer 102 is formed, and the dielectric layer 102 covers the gates G of the eight transistors and is used to isolate and protect the gate G of each transistor.

[0083] Step S12: Fig.10 As shown, an active layer ACT of eight transistors, namely, a first transistor 11 , a second transistor 12 , a third transistor 13 , a fourth transistor 14 , a fifth transistor 15 , a sixth transistor 16 , a seventh transistor 17 and an eighth transistor 18 , is formed.

[0084] The active layer ACT includes a first portion ACT11, a second portion ACT12, a third portion ACT13, a fourth portion ACT14, a fifth portion ACT15, a sixth portion ACT16, a seventh portion ACT17 and an eighth portion ACT18, which respectively form eight transistors.

[0085] In each inverter, the conductivity types of the two transistors are different, that is, the corresponding active layer ACT conductivity types are different. Taking the third transistor 13 and the fourth transistor 14 of the first inverter 21 as an example, when the third transistor 13 is a P-type transistor and the fourth transistor 14 is an N-type transistor, the third part ACT13 of the active layer ACT is a P-type conductivity type, and the fourth part ACT14 of the active layer ACT is an N-type conductivity type. That is, the material of the third part ACT13 includes at least one of a P-type oxide semiconductor, P-doped polysilicon, P-doped amorphous silicon, or a two-dimensional material exhibiting P-type semiconductor characteristics. The material of the fourth part ACT14 includes at least one of an N-type oxide semiconductor, N-doped polysilicon, N-doped amorphous silicon, or a two-dimensional material exhibiting N-type semiconductor characteristics.

[0086] Step S13: Fig.11 As shown, the source S and the drain D of a total of eight transistors, namely, a first transistor 11, a second transistor 12, a third transistor 13, a fourth transistor 14, a fifth transistor 15, a sixth transistor 16, a seventh transistor 17 and an eighth transistor 18, are formed.

[0087] The source S and drain D of the above eight transistors can be formed in the same process, and the following can be achieved through reasonable patterning: Figure 1 or Figure 2 The circuit connection relationship is shown.

[0088] In the register 10 prepared by the above preparation method, each inverter is a planar structure, that is, the two transistors of each inverter are laid flat on the substrate 101. Based on this, the area overhead of the register 10 is equivalent to the area of ​​8 transistors laid flat on the substrate 101.

[0089] Since the preparation method provided in the embodiment of the present application is based on a back-end process, a stacking solution can be adopted in the process of preparing the inverter.

[0090] Illustratively, in some embodiments, along a direction perpendicular to the substrate 101 , at least one of the first inverter 21 , the second inverter 22 , and the third inverter 23 is an inverter with a stacked structure, and the inverter with the stacked structure includes a lower transistor T1 and an upper transistor T2 .

[0091] For example, Figure 6 As shown, when the first inverter 21 has a stacked structure, and the stacked structure is such that the third transistor 13 is located below the fourth transistor 14 , the lower transistor T1 is the third transistor 13 , and the upper transistor T2 is the fourth transistor 14 .

[0092] Based on this, Fig.12 As shown, Fig.12Another preparation method flow chart is provided for the embodiment of the present application. Figures 13 to 20 for Fig.12 Diagram of each step of the preparation method shown.

[0093] like Fig.12 As shown, the preparation method includes the following steps S21 to S25:

[0094] Step S21: Fig.13 As shown, the source S and the drain D of the lower transistor T1 are formed.

[0095] In the process of forming the source S and the drain D of the lower transistor T1 , the source S and the drain D of the first transistor 11 and the source S and the drain D of the second transistor 12 may also be formed in the same process.

[0096] Step S22: Fig.14 As shown, a first active layer ACT11 of the lower transistor T1 is formed.

[0097] The first active layer ACT11 includes a first portion ACT111 for forming the first transistor 11, a second portion ACT112 for forming the second transistor 12, and a lower transistor T1 (ie, a lower portion ACT122) for forming the first inverter 21. Figure 6 The third part ACT113 of the third transistor 13) is shown.

[0098] Afterwards, if Fig.15 As shown, a first dielectric layer 102 is formed. The first dielectric layer 102 is used to provide a flat surface to facilitate subsequent processes, and the first dielectric layer 102 plays a role of protection and isolation to prevent leakage.

[0099] In order to realize the electrical connection between the two transistors inside the inverter, such as Fig.16 As shown, a via hole V1 is formed through the first dielectric layer 102, and the via hole V1 exposes the drain D of the transistor T1 below, so as to facilitate the subsequent electrical connection between the drains D of the two transistors in the inverter. After the drains D of the two transistors are electrically connected, they serve as the output end of the inverter and are electrically connected to other devices to form Figure 1 or Figure 2 The circuit structure shown.

[0100] Step S23: Fig.17 As shown, a common gate G0 of the lower transistor T1 and the upper transistor T2 is formed.

[0101] In the process of forming the common gate G0 of the inverter with a stacked structure, the gate G of the first transistor 11 and the gate G of the second transistor 12 may also be formed by the same process.

[0102] Afterwards, if Fig.18 As shown, a second dielectric layer 103 is formed, and the second dielectric layer 103 covers the common gate G0 to play a role of protection and isolation.

[0103] Step S24: Fig.19 As shown, a second active layer ACT21 of the upper transistor T2 is formed, and the second active layer ACT21 is located on a side of the common gate G0 away from the substrate 101 .

[0104] Illustratively, the second active layer ACT21 includes a fourth portion ACT214 for forming the fourth transistor 14 .

[0105] Step S25: Fig. 20 As shown, the source S and the drain D of the upper transistor T2 are formed.

[0106] The above preparation method is only illustrated by taking the first inverter 21 having a stacked structure as an example. It can be understood that when the second inverter 22 and / or the third inverter 23 also have a stacked structure, their preparation methods can refer to the above preparation methods.

[0107] When the first inverter 21, the second inverter 22 and the third inverter 23 all have a stacked structure, based on the above-mentioned preparation method, the area overhead of each inverter is equivalent to the area of ​​1 transistor on the substrate 101. Based on this, the area overhead of the register 10 is equivalent to the area of ​​5 transistors on the substrate 101, further reducing the area overhead of the register 10.

[0108] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can think of within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A register, characterized in that: It includes a signal input terminal, a signal output terminal and a clock control signal terminal; The register further includes a first transistor, a second transistor, a first inverter, a second inverter, and a third inverter; Among the first transistor and the second transistor, the gate of one is electrically connected to the clock control signal terminal through the first inverter, and the gate of the other is directly electrically connected to the clock control signal terminal; the source of the first transistor is electrically connected to the signal input terminal, and the drain of the first transistor is electrically connected to the source of the second transistor through the second inverter; the drain of the second transistor is electrically connected to the signal output terminal through the third inverter.

2. The register according to claim 1, characterized in that: The first inverter includes a third transistor and a fourth transistor, the gate of the third transistor is electrically connected to the gate of the fourth transistor, the source of the third transistor is electrically connected to the first voltage terminal, the source of the fourth transistor is electrically connected to the second voltage terminal, and the drain of the third transistor is electrically connected to the drain of the fourth transistor; The second inverter includes a fifth transistor and a sixth transistor, the gate of the fifth transistor is electrically connected to the gate of the sixth transistor, the source of the fifth transistor is electrically connected to the first voltage terminal, the source of the sixth transistor is electrically connected to the second voltage terminal, and the drain of the fifth transistor is electrically connected to the drain of the sixth transistor; The third inverter includes a seventh transistor and an eighth transistor, the gate of the seventh transistor is electrically connected to the gate of the eighth transistor, the source of the seventh transistor is electrically connected to the first voltage terminal, the source of the eighth transistor is electrically connected to the second voltage terminal, and the drain of the seventh transistor is electrically connected to the drain of the eighth transistor.

3. The register according to claim 2, characterized in that: The register further includes a substrate, and the first to eighth transistors are discretely arranged on a surface of the substrate.

4. The register according to claim 1, characterized in that: The register further includes a substrate, and the first transistor, the second transistor, the first inverter, the second inverter and the third inverter are arranged on the substrate; The first inverter, the second inverter and the third inverter each include two transistors, and along a direction perpendicular to the substrate, at least one of the first inverter, the second inverter and the third inverter is an inverter with a stacked structure; The two transistors in the inverter with the stack structure are stacked.

5. The register according to claim 4, characterized in that: The first transistor, the second transistor, the first inverter, the second inverter and the third inverter are discretely arranged on the surface of the substrate.

6. The register according to claim 4 or 5, characterized in that: The first inverter, the second inverter and the third inverter are all inverters with a stacked structure.

7. The register according to claim 1, characterized in that: The first transistor and the second transistor are both N-type transistors.

8. A method for preparing a register, characterized in that: The register includes a signal input terminal, a signal output terminal and a clock control signal terminal; The preparation method comprises: forming a first transistor, a second transistor, a first inverter, a second inverter, and a third inverter on a substrate; Among them, among the first transistor and the second transistor, the gate of one is electrically connected to the clock control signal end through the first inverter, and the gate of the other is directly electrically connected to the clock control signal end; the source of the first transistor is electrically connected to the signal input end, and the drain of the first transistor is electrically connected to the source of the second transistor through the second inverter; the drain of the second transistor is electrically connected to the signal output end through the third inverter.

9. The preparation method according to claim 8, characterized in that: The first inverter includes a third transistor and a fourth transistor, the second inverter includes a fifth transistor and a sixth transistor, and the third inverter includes a seventh transistor and an eighth transistor; A first transistor, a second transistor, a first inverter, a second inverter and a third inverter are formed on a substrate, including: forming gates of the first to eighth transistors; forming active layers of the first to eighth transistors; The source and drain of the first to eighth transistors are formed.

10. The preparation method according to claim 8, characterized in that: Along a direction perpendicular to the substrate, at least one of the first inverter, the second inverter and the third inverter is an inverter with a stacked structure, and the inverter with a stacked structure includes a lower transistor and an upper transistor; The inverter with the stacked structure is formed, comprising: forming a source and a drain of the lower transistor; forming a first active layer of the lower transistor; forming a common gate of the lower transistor and the upper transistor; forming a second active layer of the upper transistor, wherein the second active layer is located on a side of the common gate away from the substrate; A source and a drain of the upper transistor are formed.

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