Calculation circuit and calculation device

Abstract

The invention relates to an operational circuit and a computing device. The operational circuit comprises multiple stages of addition modules, and the input end of the next stage of addition module is in communication connection with the output end of the previous stage of addition module adjacent to the next stage of addition module. The latter-level addition module is configured to calculate at least a sum of a first operand output by the former-level addition module and a product obtained by multiplying at least one set of first coefficients and a second operand, where the first coefficients are generated from at least one element in a first vector and the second coefficients are generated from at least one element in a second vector. And the second operand is generated according to at least one element in the second vector.

Description

Technical Field

[0001] The present disclosure relates to the technical field of electronic circuits, and more specifically, to an operation circuit and a computing device. Background Art

[0002] In the process of data processing, dot product operations between vectors are often involved. In some cases, multiple items to be accumulated in the dot product operation (for example, the product obtained by multiplying an element in a vector by the corresponding element in another vector) may not be obtained at the same time, so it is generally necessary to wait until all items to be accumulated are obtained before performing accumulation calculations to obtain the dot product operation results. However, this processing method will lead to a greater risk of timing violations in related circuits and may also lead to a decrease in circuit performance, so it needs to be improved. Summary of the invention

[0003] One of the objectives of the present disclosure is to provide an operation circuit and a computing device.

[0004] According to a first aspect of the present disclosure, a computing circuit is provided, the computing circuit being at least used to calculate a dot product of a first vector and a second vector, wherein the first vector is a pre-known coefficient vector, and the computing circuit comprises: A multi-stage addition module, wherein an input end of a subsequent stage addition module is communicatively connected to an output end of a previous stage addition module adjacent to the stage addition module, and the subsequent stage addition module is configured to at least calculate the sum of a first operand output by the previous stage addition module and a product obtained by multiplying at least one set of first coefficients and second operands, wherein the first coefficient is generated based on at least one element in a first vector, and the second operand is generated based on at least one element in a second vector.

[0005] In some embodiments, when the dimensions of the first vector and the second vector are N respectively, the operation circuit has an N-1-stage addition module, wherein: The 0th level addition module is configured to calculate A 0 *B 0 +A 1 *B 1 , where A 0 It is based on the 0th element a in the first vector 0 The first coefficient generated, A 1 It is based on the first element a in the first vector 1 The first coefficient generated, B 0 is based on the 0th element b in the second vector 0 The second operand generated, and B 1 is based on the first element b in the second vector 1 The second operand generated; and, The i-th stage addition module is configured to calculate S i +A i+1 *B i+1 , where S i is the first operand output by the i-1th level addition module, A i+1 It is based on the i+1th element a in the first vector i+1 The first coefficient generated, and B i+1 is based on the i+1th element b in the second vector i+1 The second operand generated, where i is an integer and 0 <i<N-1。

[0006] In some embodiments, the operation circuit further includes: One or more data transmission lines, each of the one or more data transmission lines is communicatively connected to at least one stage of the addition module, and the data transmission line is configured to transmit the element in the second vector or the second operand to the corresponding addition module.

[0007] In some embodiments, at least one level of the multi-level addition module is configured to obtain a third operand, and is configured to determine a corresponding set of products obtained by multiplying the first coefficient and the second operand based on the product obtained by multiplying the second coefficient and the third operand, wherein the third operand is a preset multiple of the corresponding fourth operand, the fourth operand is generated based on at least one target element in the second vector, and in the dot product calculation, the absolute value of the element in the first vector multiplied by the target element in the second vector is greater than or equal to the absolute value of the preset multiple, the preset multiple is greater than 1, and for each fourth operand and the corresponding third operand, the product of the second coefficient and the preset multiple is less than or equal to the first coefficient.

[0008] In some embodiments, the at least one stage of addition module is further configured to determine a corresponding set of products obtained by multiplying the first coefficient and the second operand according to the product obtained by multiplying the third coefficient and the fourth operand corresponding to the third operand, wherein, for each fourth operand and the corresponding third operand, the sum of the product of the second coefficient and the preset multiple plus the third coefficient is equal to the first coefficient; and / or, The at least one stage addition module is also configured to determine a corresponding set of products obtained by multiplying the first coefficient and the second operand based on the product obtained by multiplying the first coefficient and the fifth operand, wherein the fifth operand is generated based on at least one element in the second vector except the element used to generate the third operand.

[0009] In some embodiments, the operation circuit further includes: A multiple operation module is configured to calculate a preset multiple of a fourth operand to generate a corresponding third operand.

[0010] In some embodiments, the preset multiple is determined according to the first vector; or, The preset multiple includes at least one of 3 times, 5 times and 7 times.

[0011] In some embodiments, the multiple calculation module includes one or more multiple calculation units, and the multiple calculation unit includes: A first shifter is configured to shift the sixth operand to the left by p bits to generate a seventh operand, wherein the seventh operand is 2 p times the sixth operand, the sixth operand is a positive integer multiple of the second operand, and p is a positive integer; or, A first adding unit is configured to add an eighth operand and a ninth operand to generate a tenth operand, wherein the eighth operand is a positive integer multiple of the second operand, and the ninth operand is a positive integer multiple of the second operand.

[0012] In some embodiments, the addition module includes at least one of the following: A second shifter configured to shift the eleventh operand to the left by q bits to generate a twelfth operand, wherein the twelfth operand is 2 q times an eleventh operand, the eleventh operand being generated based on the second operand, and q is a positive integer; and, A second adding unit, wherein the second adding unit is configured to calculate the sum of at least two operands, wherein the at least two operands include a first operand output by a previous stage adding module, one or more operands output by a corresponding second shifter, or a preset constant.

[0013] In some embodiments, the operation circuit further includes: One or more register modules, wherein the register modules are communicatively connected to the input end or output end of the corresponding first-stage adding module in the multi-stage adding module.

[0014] In some embodiments, when the operation circuit has M-level addition modules, the operation circuit includes at least M register modules, wherein the output end of the m-th level addition module is communicatively connected to the input end of the m-th register module, and the m-th register module is configured to register the first operand output by the m-th level addition module, wherein m is an integer and 0≤m <M。

[0015] In some embodiments, the one or more register modules include a primary register module, the primary register module is communicatively connected to the input terminal of the 0th stage addition module, and the primary register module is configured to register A 0 *B 0, where A 0 It is based on the 0th element a in the first vector 0 The first coefficient generated, and B 0 is based on the 0th element b in the second vector 0 The generated second operand.

[0016] In some embodiments, the operation circuit further includes: The bitwise inversion module is configured to, when an element in the first vector is a negative number, bitwise invert at least one operand generated according to an element in the second vector multiplied by the element in the first vector.

[0017] In some embodiments, the operation circuit is configured to perform an image interpolation operation, the first vector is a coefficient vector for image interpolation, and at least two elements of the second vector are not provided to the operation circuit at the same time.

[0018] According to a second aspect of the present disclosure, a computing device is provided, comprising one or more computing circuits as described above.

[0019] In some embodiments, when the computing device includes a plurality of computing circuits, at least two computing circuits operate in parallel.

[0020] Other features and advantages of the present disclosure will become more apparent from the following detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings, which constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0022] The present disclosure may be more clearly understood from the following detailed description with reference to the accompanying drawings, in which: Figure 1 A schematic diagram showing a computing device performing image interpolation; Figure 2 Shows Figure 1 A schematic diagram of a computing circuit in a computing device; Figure 3 A block diagram of a computing device according to an exemplary embodiment of the present disclosure is shown; Figure 4 A block diagram of an operation circuit according to an exemplary embodiment of the present disclosure is shown; Figure 5 A block diagram of an operation circuit according to another exemplary embodiment of the present disclosure is shown; Figure 6 A block diagram of a multiple operation module in an operation circuit according to a specific embodiment of the present disclosure is shown; Figure 7 A block diagram of a multiple operation module in an operation circuit according to another specific embodiment of the present disclosure is shown; Figure 8 A block diagram of a multiple operation module in an operation circuit according to another specific embodiment of the present disclosure is shown; Fig. 9 A block diagram of an addition module in a computing circuit according to a specific embodiment of the present disclosure is shown; Fig.10 A block diagram of an operation circuit according to yet another exemplary embodiment of the present disclosure is shown.

[0023] Note that in the embodiments described below, the same reference numerals are sometimes used in common between different drawings to represent the same parts or parts with the same functions, and their repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to represent similar items, so once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0024] For ease of understanding, the positions, sizes, and ranges of various structures shown in the drawings and the like sometimes do not represent actual positions, sizes, and ranges, etc. Therefore, the disclosed invention is not limited to the positions, sizes, and ranges, etc. disclosed in the drawings and the like. In addition, the drawings are not necessarily drawn to scale, and some features may be exaggerated to show details of specific components. DETAILED DESCRIPTION

[0025] Various exemplary embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that unless otherwise specifically stated, the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure.

[0026] The following description of at least one exemplary embodiment is in fact merely illustrative and is in no way intended to limit the present disclosure and its application or use. That is, the structures and methods herein are shown in an exemplary manner to illustrate different embodiments of the structures and methods in the present disclosure. However, those skilled in the art will appreciate that they merely illustrate exemplary ways of the present disclosure that can be implemented, rather than exhaustive ways. In addition, the drawings need not be drawn to scale, and some features may be enlarged to illustrate the details of specific components.

[0027] In addition, technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0028] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0029] In various data processing processes, vector dot product operations are a common form of operation. For example, the dot product P between a first vector A and a second vector B, each with dimensions N, is d It can be expressed as: (1) in, represents the i-th component of the first vector A, represents the i-th component of the second vector B, where i is an integer and (Those skilled in the art will appreciate that the value of i may also be an integer greater than or equal to 1, which does not affect the essence of the operation. Therefore, in this article, the value of i starting from zero will be used as an example for detailed explanation).

[0030] In some examples, dot product operations of vectors can be used in image interpolation. Specifically, image interpolation is the process of inferring the values ​​of new pixels from the values ​​of known pixels. The new pixels may not be at the integer coordinates of the original image. In this case, the values ​​of these new pixels can be obtained through image interpolation algorithms. When the size, shape or position of the image changes, or in the process of video processing, in order to fill in missing frames or generate smooth slow motion effects, etc., image interpolation related to images or video frames may be required.

[0031] Depending on the image interpolation algorithm used, a corresponding coefficient vector may be determined, which may be used as the first vector in the vector dot product operation process. In a specific example, in Advanced Video Coding (AVC, H.264), a pixel value at a half-pixel position may be generated based on a coefficient vector (0, 1, -5, 20, 20, -5, 1, 0). In another specific example, in High Efficiency Video Coding (HEVC, H.265), a pixel value at a half-pixel position may be generated based on a coefficient vector (-1, 4, -11, 40, 40, -11,4, -1), a pixel value at a quarter-pixel position may be generated based on a coefficient vector (-1, 4, -10, 58, 17, -5, 1, 0), or a pixel value at a three-quarter-pixel position may be generated based on a coefficient vector (0, 1, -5, 17, 58, -10, 4, -1). In some specific embodiments below, the coefficient vector (-1, 4, -11, 40, 40, -11, 4, -1) in H.265 is taken as the first vector, and the second vector formed by the pixel values ​​of eight pixels to be processed in the image is taken as an example to explain the technical solution of the present disclosure in detail. However, it can be understood that the operation circuit and the computing device of the present disclosure can also be used to calculate the dot product between other types of vectors, or used in application scenarios other than image interpolation, which is not limited here.

[0032] like Figure 1 and Figure 2 As shown, a computing device 200' may include a plurality of computing circuits 100', and the plurality of computing circuits 100' may operate in parallel to process image interpolation operations associated with a plurality of groups of pixel points 910 in an image 900 in parallel. Figure 1 In the image 900 shown, taking the multiple pixel points 910 in the first row above the image 900 as an example, the pixel points 910 in this row can be divided into multiple pixel groups, each pixel group can include eight consecutive pixel points 910, and for each pixel group, the pixel values ​​of the pixel points 910 therein can be sequentially input into the corresponding operation circuit 100' in the computing device 200' in order from right to left to perform image interpolation operation; after completing the image interpolation operation associated with the first row of pixel points 910, the image interpolation operation associated with the next row of pixel points 910 can be continued until the interpolation of the entire image 900 is completed. For example, Figure 1 The various operation circuits 100′ shown in the figure can be used to execute the operations related to the pixel point p 0 ~p 7 A pixel group, including pixel point p 1 ~p 8 The pixel group, until it includes pixel point p n ~pn+7 For each operation circuit 100', the operation circuit 100' can sequentially receive the pixel values ​​of the pixel points 910 in the corresponding pixel group in different clock cycles. Figure 1 As shown, each operation circuit 100' may include an input terminal (din) to receive the pixel value of the pixel point 910, and may also include an output terminal (dout) to output the dot product of the first vector and the second vector or the result of the image interpolation operation. It is understandable that in other specific examples, the pixel values ​​of the corresponding pixel points may also be input into the corresponding operation circuit 100' in the computing device 200' according to the pixel columns in the image, or according to the diagonal lines in the image, etc., to achieve the desired image interpolation operation, which is not limited here. For example, each operation circuit 100' may be responsible for image interpolation operations associated with the pixel points 910 in a row or a column in the image 900, etc.

[0033] According to the above formula (1), a large number of multiplication and addition operations are usually involved in vector dot product or image interpolation operations. In order to simplify the operation circuit, the multiplication and addition operations in the above formula (1) can be converted into shift and addition operations. Take the first vector A=(-1, 4, -11, 40, 40, -11, 4, -1) and the second vector B=(p 0 , p 1 , p 2 , p 3 ,p 4 , p 5 , p 6 , p 7 ) as an example, each element in the first vector can be converted into the sum of integer powers of 2, that is: A=(-1, 4, -8-2-1, 32+8, 32+8, -8-2-1, 4, -1). Furthermore, the dot product of the first vector A and the second vector B can be expressed as: (2) In some examples, the following may be used: Figure 2 The operation circuit 100' shown is used to perform the operation in the above formula (2). Specifically, the operation circuit 100' may include a plurality of registers 110' and an addition module 120'. The plurality of registers 110' may be connected in series to respectively store the corresponding elements in the second vector that are sequentially input into the operation circuit 100', or the register 110' may be used for beating to ensure the correct timing in the operation circuit 100'. After obtaining all the elements in the second vector from the corresponding register 110', the addition module 120' may perform shift and addition operations to obtain the dot product of the first vector and the second vector. Figure 2 In the example, the inputs d0 to d7 received by the adding module 120' from the register 110' may be equal to the pixel points p 0 ~p 7 '. It can be seen that the pixel value input to the operation circuit 100' earlier will be stored in more registers 110', which allows the pixel values ​​of multiple pixels to be transmitted to the addition module 120' within the same clock cycle to participate in the shift and addition operations. However, this setting will result in the existence of multiple registers 110' directly connected inside the operation circuit 100', which will lead to a greater risk of hold time violations, and solving these hold time violation problems often requires a great price. In addition, a large number of shift and addition operations may need to be performed in the addition module 120', which results in a generally large delay, thereby reducing the performance of the operation circuit 100' and increasing the area and power consumption of the operation circuit 100'.

[0034] In order to solve the above problems, the present disclosure provides an operation circuit and a computing device including the same. In an exemplary embodiment of the present disclosure, Figure 3 As shown, the computing device 200 may include one or more computing circuits 100, wherein the computing circuit 100 may be used to calculate the dot product of the first vector and the second vector. In an embodiment of the present disclosure, the first vector may be a pre-known coefficient vector, so that the specific setting mode of various components in the computing circuit 100 is determined according to the pre-known coefficients in the first vector. Compared with the case where both the first vector and the second vector are uncertain, the computing circuit 100 of the present disclosure only needs to consider the uncertain second vector, which helps to simplify the circuit structure of the computing circuit 100 and the computing device 200. Further, in the case where the computing device 200 includes multiple computing circuits 100, at least two computing circuits 100 can run in parallel to improve the computing efficiency.

[0035] In some embodiments, the operation circuit 100 and the computing device 200 including the same may be configured to perform image interpolation operations, and the operation thereof may refer to the above description of the operation circuit 100 and the computing device 200 including the same. Figure 1 As described above, for example, the pixel values ​​of the corresponding pixel points can be input into the corresponding operation circuit 100 in the computing device 200 according to the pixel rows, pixel columns or diagonals in the image to achieve the desired image interpolation operation, which will not be described in detail here. It can be understood that in other embodiments, the computing device 200 and the operation circuit 100 of the present disclosure can also be used for vector dot product operations involved in other application scenarios, which are not limited here.

[0036] In the present disclosure, examples of computing device 200 may include, but are not limited to, video encoders, consumer electronics, components of consumer electronics, electronic testing equipment, image processing equipment, cellular communication infrastructure such as base stations, etc. Examples of computing device 200 may include, but are not limited to, mobile phones such as smart phones, wearable computing devices such as smart watches or headphones, phones, televisions, computer monitors, computers, modems, handheld computers, laptop computers, tablet computers, personal digital assistants (PDAs), in-vehicle electronic systems such as automotive electronic systems, stereo systems, DVD players, portable cameras, cameras such as digital cameras, portable memory chips, peripheral devices, clocks, etc. In addition, computing device 200 may include incomplete products.

[0037] In an exemplary embodiment of the present disclosure, Figure 4 As shown, the operation circuit 100 may include a multi-stage addition module 120. Among them, the input end of the subsequent stage addition module 120 can be communicatively connected to the output end of the previous stage addition module 120 adjacent to the stage addition module 120. In some embodiments, two adjacent stages of addition modules 120 can be directly connected. Alternatively, in other embodiments, in order to improve the performance of the operation circuit 100, other components such as a register module 110 may be provided between two adjacent stages of addition modules 120, as will be described in detail later. The subsequent stage addition module 120 may be configured to at least calculate the sum of the first operand output by the previous stage addition module 120 and the product obtained by multiplying at least one set of first coefficients and second operands, wherein the first coefficient may be generated based on at least one element in the first vector, and the second operand may be generated based on at least one element in the second vector. By providing the multi-stage addition module 120, the output of the previous stage addition module 120 may be directly connected to the output of the previous stage addition module 120. Figure 2 All the multiplication-accumulation-addition operations or shift-and-addition operations to be performed by the single addition module 120' shown in the figure are converted into partial multiplication-accumulation-addition operations or shift-and-addition operations respectively performed by multiple stages of addition modules 120. On the one hand, this can help reduce or even eliminate the situation where multiple registers are directly connected, thereby reducing or even eliminating the cost of repairing hold time violations. On the other hand, it can reduce the amount of operations of each stage of the addition module 120, thereby helping to reduce delays, improve the performance of the operation circuit 100, and also reduce the area and power consumption of the operation circuit 100.

[0038] In some embodiments, the single-stage addition module 120 may be configured to perform calculations associated with one or more accumulated items in the above formula (1) or formula (2). For example, when the dimensions of the first vector and the second vector are 8 respectively, the dot product operation of the first vector and the second vector generally involves the accumulation of a total of 8 product items, wherein each product item is obtained by multiplying the elements in the first vector and the second vector at the same position. In a specific example, the operation circuit 100 may include a two-stage addition module 120, wherein the first-stage addition module 120 may be configured to calculate , and the subsequent stage addition module 120 may be configured to calculate. Alternatively, in another specific example, the previous stage addition module 120 may be configured to calculate , and the subsequent adding module 120 can be configured to calculate That is, the number of items accumulated by each level of the adding module 120 is not limited here. In addition, more levels of adding modules 120 can be provided in the operation circuit 100 to further reduce the amount of operations that each level of the adding module 120 may need to perform, which is also not limited here.

[0039] In some embodiments, a corresponding element in the first vector may be directly used as the first coefficient, and a corresponding element in the second vector may be used as the second operand, so that each stage of the addition module 120 performs corresponding calculations. Alternatively, in other embodiments, the elements in the first vector and / or the second vector may be appropriately processed in advance to generate the corresponding first coefficient and / or second operand, so as to simplify the calculations.

[0040] For example, there may be negative elements in the first vector. Although the negative coefficients can be directly reflected by subtraction calculation, this may cause the structure of the operation circuit 100 to become complicated. In another processing method, the subtraction calculation can be converted into addition calculation by bit-by-bit inversion of the elements in the second vector that will be multiplied by the negative coefficients. In this case, the first coefficient can be the absolute value of a corresponding element in the first vector. It is understandable that, according to specific operation requirements, other methods can also be used to generate the corresponding first coefficient according to at least one element in the first vector, which is not limited here.

[0041] For another example, in the dot product operation, if the elements in the first vector that are multiplied by two or more elements in the second vector have equal absolute values, the sum or difference of the two or more elements in the second vector may be calculated first, and then the product of the sum or difference and the coefficient may be calculated. For example, when the first vector is A=(-1, 4, -11,40, 40, -11, 4, -1) and the second vector is B=(p 0 , p 1 , p2 , p 3 , p 4 , p 5 , p 6 , p 7 ), we can first calculate p 0 +p 7 、p 1 +p 6 、p 2 +p 5 or p 3 +p 4 The value of, and then calculate their product with the corresponding coefficient. In this case, the second operand can be the sum or difference of two or more elements in the second vector, or can also be equal to the bitwise inversion of the above sum or difference, etc. Alternatively, as will be described in detail later, the second operand may also be a preset multiple of an element in the second vector, or a preset multiple of the sum or difference of multiple elements, etc., to help reduce the number of shifts and / or addition calculations required to be performed in the corresponding addition module 120. It is understandable that, according to specific operation needs, other methods can also be used to generate the corresponding second operand according to at least one element in the second vector, which is not limited here.

[0042] In a specific embodiment, when the dimensions of the first vector and the second vector are N, the operation circuit 100 may have N-1 stages of adding modules 120, and each stage of adding modules 120 may be configured to perform a calculation associated with a corresponding item to be accumulated in the above formula (1). Specifically, the 0th stage adding module (i.e., the first stage adding module) 120 may be configured to calculate A 0 *B 0 +A 1 *B 1 , where A 0 It can be based on the 0th element a in the first vector A 0 The first coefficient generated, A 1 It can be based on the first element a in the first vector A 1 The first coefficient generated, B 0 It can be based on the 0th element b in the second vector B 0 The second operand generated, and B 1 It can be based on the first element b in the second vector B 1 The second operand generated; and the i-th level addition module can be configured to calculate S i +A i+1 *B i+1 , where S i It can be the first operand output by the i-1th level addition module, A i+1It can be the first coefficient generated according to the (i + 1)-th element a in the first vector A i+1 and B i+1 It can be the second operand generated according to the (i + 1)-th element b in the second vector B i+1 where i is an integer and 0 < i < N - 1. Especially when each element in the second vector or the second operand generated according to the element is provided to the arithmetic circuit 100 in a respective one clock cycle, this setting method can eliminate the direct connection of the registers in the arithmetic circuit 100, thereby improving the performance of the arithmetic circuit.

[0043] In some embodiments, as Figure 4 and Figure 5 shown, the arithmetic circuit 100 may further include one or more data transmission lines 130. Each data transmission line 130 may be formed by, for example, a data bus. Each data transmission line 130 may be communicatively connected to at least one stage of the addition module 120, and the data transmission line 130 may be configured to transmit the elements in the second vector or the second operand to the corresponding addition module. Which addition modules 120 each data transmission line 130 is specifically communicatively connected to may be determined according to the coefficients in the first vector, and this is not limited herein. In a specific example, as Figure 4 shown, each stage of the multi-stage addition module 120 may be respectively communicatively connected to the same data transmission line 130, so that the data transmission line 130 can sequentially transmit the elements in the second vector or the second operand to the corresponding addition module 120. In another specific example, as Figure 5 shown, the same addition module 120 may be communicatively connected to multiple data transmission lines 130 at the same time to obtain all the data required for the addition module 120 to perform the operation. For example, in the case where multiple product terms in formula (1) are to be accumulated in the addition module 120 (the addition module 120 may need to respectively obtain different elements in the second vector or different second operands from different data transmission lines 130), or as described later in the case of performing a multiply-accumulate operation based on a preset multiple of the corresponding element in the second vector (the addition module 120 may need to respectively obtain the element in the second vector and the preset multiple of the element from different data transmission lines 130).

[0044] In some embodiments, as mentioned above, in order to simplify the operation, at least one level of the multi-level addition module 120 in the multi-level addition module 120 may be configured to obtain a third operand, and may be configured to determine a corresponding set of products obtained by multiplying the first coefficient and the second operand according to the product obtained by multiplying the second coefficient and the third operand (it can be understood that in some cases, the third operand may be equal to the second operand). The third operand may be a preset multiple of the corresponding fourth operand, and the fourth operand may be generated according to at least one target element in the second vector. In the dot product calculation, the absolute value of the element in the first vector multiplied by the target element in the second vector is greater than or equal to the absolute value of the preset multiple, and the preset multiple is greater than 1. In this way, by calculating the preset multiples of at least part of the target elements in the second vector in advance, the number of shifts and / or addition and subtraction calculations required to be performed by the corresponding addition module 120 can be reduced, thereby simplifying the structure of the operation circuit 100.

[0045] Further, in order to generate the third operand, in a specific example, as Figure 5 As shown, the operation circuit 100 may further include a multiple operation module 140, and the multiple operation module 140 may be configured to calculate a preset multiple of the fourth operand to generate a third operand, that is, the third operand is equal to the product of the fourth operand and the preset multiple. Alternatively, in some other specific examples, other methods may be used to obtain the third operand without setting the multiple operation module 140 in the operation circuit 100, which is not limited here.

[0046] In some specific examples, the fourth operand may be generated based on a single target element in the second vector. For example, the fourth operand may be a target element in the second vector itself. Alternatively, the fourth operand may be equal to the bitwise inversion of a target element in the second vector, especially when the element corresponding to the target element in the first vector is a negative number, the subtraction calculation in the dot product operation may be converted into an addition calculation by the bitwise inversion operation, thereby further simplifying the structure of the operation circuit 100.

[0047] In some other specific examples, the fourth operand may be generated based on at least two target elements in the second vector. For example, during the dot product operation, if the elements in the first vector that are multiplied by two or more target elements in the second vector have equal absolute values, then the sum or difference of the two or more target elements in the second vector may be calculated first, and then the product of the sum or difference and the coefficient may be calculated. For example, when the first vector is A=(-1, 4, -11,40, 40, -11, 4, -1) and the second vector is B=(p 0 , p 1 , p 2 , p3 , p 4 , p 5 , p 6 , p 7 ), we can first calculate p 0 +p 7 、p 1 +p 6 、p 2 +p 5 or p 3 +p 4 The fourth operand may be the sum or difference of two or more target elements, or may be equal to the bitwise inversion of the above-mentioned sum or difference, as required. It is to be understood that the fourth operand may also be obtained by calculating one or more target elements in the second vector in other ways as required, which is not limited here.

[0048] In addition, it should be noted that, in the second vector, there may be multiple target elements that meet the above conditions, but in some embodiments of the present disclosure, it is not necessarily necessary to convert all target elements into the form of the third operand. For example, if an element in the first vector is 6 and the preset multiple is 5, then for the element b in the second vector multiplied by the coefficient 6, the multiple operation module 140 can be used to calculate 5b, so that 6b is expressed in the form of 5b+b for further calculation, or 5 times of this element can be not calculated, but 6b can be expressed in the form of 4b+2b for further calculation, and the number of addition operations brought about by these two methods is the same. In general, it is possible to reduce the number of required shifts and / or addition calculations by only generating the corresponding third operand based on a part of the target elements, thereby simplifying the operation circuit 100 to a certain extent.

[0049] In some embodiments, the operation circuit 100 may include one or more multiple operation modules 140 to convert the corresponding fourth operand into the third operand. In addition, when there are multiple multiple operation modules 140, these multiple operation modules 140 can be used to calculate the product of the corresponding fourth operand and the same preset multiple. Alternatively, multiple different preset multiples can also be set as needed. In this case, these multiple operation modules 140 can also be used to calculate multiple preset multiples of the same fourth operand, which is not limited here.

[0050] In some embodiments, the preset multiple can be determined according to the first vector. Generally speaking, the larger the preset multiple is, the more likely it is to convert the multiplication calculation related to the coefficient with a larger absolute value in the first vector into less shift and / or addition calculation, but at the same time, for the coefficient with a smaller absolute value in the first vector, it generally cannot be rewritten into a form related to the preset multiple, but can only use the original shift and addition calculation method. Therefore, the specific value of the preset multiple can be weighed according to the specific first vector. In order to simplify the operation, the preset multiple can be an integer. Further, in some embodiments, considering that the multiples of integer powers of 2 can be realized by shift operations, the preset multiple can be set to an odd number or a prime number to simplify the operation as much as possible. For example, the preset multiple can include at least one of 3 times, 5 times and 7 times. In some specific examples below, the technical solution of the present disclosure will be described in detail by taking the preset multiple of 5 times as an example.

[0051] In some embodiments, Figures 6 to 8 As shown, the multiple operation module 140 may include one or more multiple calculation units, wherein the multiple calculation unit may include a first shifter 141 or a first adding unit 142 .

[0052] exist Figure 6 In the specific example shown, the multiple calculation unit may include a first shifter 141, which may be configured to shift the sixth operand to the left by p bits to generate a seventh operand, that is, the seventh operand is 2 p The sixth operand may be a positive integer multiple of the second operand, wherein the sixth operand may be a positive integer multiple of the second operand, and p is a positive integer. For example, the value of m may be 1, and depending on the specific value of the sixth operand, the first shifter 141 may be configured to generate various even multiples of the second operand.

[0053] exist Figure 7 In the specific example shown, the multiple calculation unit may include a first addition unit 142, and the first addition unit 142 may be configured to add the eighth operand and the ninth operand to generate the tenth operand, that is, the tenth operand is the sum of the eighth operand and the ninth operand, wherein the eighth operand may be a positive integer multiple of the second operand, and the ninth operand may be a positive integer multiple of the second operand. It can be seen that, depending on the specific values ​​of the eighth operand and the ninth operand, the first addition unit 142 may be configured to generate various integer multiples of the second operand. In some specific examples, the first addition unit 142 may include an adder to perform the addition of two operands.

[0054] In addition, various multiple calculation units can also be used in combination, which is not limited here. Figure 8In the specific example shown, the first adding unit 142 may be connected to the output end of the first shifter 141 to conveniently generate the required third operand.

[0055] Furthermore, in some embodiments, Figures 6 to 8 As shown, the multiple operation module 140 may further include a first register 143, the first register 143 may be communicatively connected to at least one multiple calculation unit, and the first register 143 may be configured to register the seventh operand or the tenth operand from the multiple calculation unit. Figures 6 to 8 In the specific example shown, the first register 143 can be connected to the output end of the last stage of the multiple calculation unit in the multiple operation module 140, so as to reduce the burrs in the signal, help control the timing in the operation circuit 100, and ensure the correct operation. However, in some other embodiments, especially when the addition module 120 of the operation circuit 100 is communicatively connected to the register module 110, the first register 143 in the multiple operation module 140 can also be omitted, and the register module 110 can realize the desired register function, so as to simplify the structure of the operation circuit 100 and reduce the area of ​​the operation circuit 100.

[0056] In some embodiments, Figure 5 As shown, one end of at least one data transmission line 130 in the operation circuit 100 can be communicatively connected to the multiple operation module 140, and the other end can be communicatively connected to the corresponding addition module 120, so as to transmit the third operand from the multiple operation module 140 to the corresponding addition module 120.

[0057] As described above, the addition module 120 can be configured to determine a corresponding set of products obtained by multiplying the first coefficient and the second operand according to the product obtained by multiplying the second coefficient and the third operand. Wherein, for each fourth operand and the corresponding third operand, the product of the second coefficient and the preset multiple can be less than or equal to the first coefficient. It should be noted that in this specific example, the fourth operand that has not been multiplied by the preset multiple is used as the second operand. For example, if the first vector A=(5, 15, -10, 5, 5, -10, 15, 5), the second vector B=(p 0 , p 1 , p 2 , p 3 , p 4 , p 5 ,p 6 , p 7), the preset multiple is 5, the operation circuit 100 has 7 levels of adding modules 120, and each level of adding module 120 is configured to perform a calculation associated with a corresponding term to be accumulated in the above formula (1), then for each level of adding module 120, the product of the second coefficient and the preset multiple is equal to the first coefficient, that is, the product obtained by multiplying the second coefficient and the third operand is equal to the product obtained by multiplying the corresponding set of first coefficients and the second operand. Taking the first level adding module 120 in the operation circuit 100 as an example, it can be configured to calculate , the third operand 5p 1 It can be pre-calculated by the multiple operation module 140 and the third operand 5p 1 The corresponding second coefficient is 3.

[0058] In some embodiments, depending on the specific value of the first coefficient in the first vector, a target element in the second vector may be converted into the form of the sum of the third operand and the product of the target element and an integer power of 2. In this case, in order to correctly calculate the dot product of the first vector and the second vector, the corresponding addition module 120 can also be configured to determine a corresponding set of first coefficients and products obtained by multiplying the second operand based on the product obtained by multiplying the third coefficient and the fourth operand corresponding to the third operand, wherein, for each fourth operand and the corresponding third operand, the product of the second coefficient and a preset multiple plus the sum of the third coefficient is equal to the first coefficient. It should be noted that in this specific example, the fourth operand that has not yet been multiplied by the preset multiple is also used as the second operand. For example, if the first vector A=(5, 16,-10, 5, 5, -10, 15, 5) and the second vector B=(p 0 , p 1 , p 2 , p 3 , p 4 , p 5 , p 6 , p 7 ), the preset multiple is 5, the operation circuit 100 has 7 levels of adding modules 120, and each level of adding module 120 is configured to perform a calculation associated with a corresponding item to be accumulated in the above formula (1), then for the first level adding module 120, the sum of the product of the second coefficient and the preset multiple plus the third coefficient is equal to the first coefficient. That is, the first level adding module in the operation circuit 100 can be configured to calculate , where the third operand is 5p 1 It can be pre-calculated by the multiple operation module 140. 1 For the relevant terms, the second coefficient is 3 and the third coefficient is 1, that is, 16p 1 =3*5p 1 +1*p1 .

[0059] In some embodiments, depending on the specific value of the first coefficient in the first vector, a certain element in the second vector may not be converted into a form containing the third operand. In this case, in order to correctly calculate the dot product of the first vector and the second vector, the corresponding addition module 120 can also be configured to determine the product obtained by multiplying a corresponding set of first coefficients and the second operand according to the product obtained by multiplying the first coefficient and the fifth operand. Among them, the fifth operand can be generated according to at least one element in the second vector except for the element used to generate the fourth operand. In some specific examples, the fifth operand can be generated according to a single element in the second vector. For example, the fifth operand can be an element in the second vector itself. Alternatively, the fifth operand can be equal to the bitwise inversion of a certain element in the second vector, especially when the coefficient corresponding to this element in the first vector is a negative number, the subtraction calculation in the dot product operation can be converted into an addition calculation by the bitwise inversion operation, thereby further simplifying the structure of the operation circuit 100. In other specific examples, the fifth operand can be generated according to at least two elements in the second vector. For example, during the dot product operation, if the coefficients of the first vector multiplied by two or more elements in the second vector have equal absolute values, then the sum or difference of the two or more elements in the second vector can be calculated first, and then the product of the obtained sum or difference and the coefficient can be calculated, similar to the explanation above about the fourth operand. As needed, the fifth operand can be the sum or difference of two or more elements in the second vector, or it can be equal to the bit-by-bit inversion of the above sum or difference. It can be understood that, as needed, the fifth operand can also be obtained by calculating one or more elements in the second vector in other ways, which is not limited here. For example, if the first vector A=(-1, 4, -11, 40,40, -11, 4, -1), the second vector B=(p 0 , p 1 , p 2 , p 3 , p 4 , p 5 , p 6 , p 7 ), the preset multiple is 5, the operation circuit 100 has 7 levels of adding modules 120, and each level of adding module 120 is configured to perform a calculation associated with a corresponding item to be accumulated in the above formula (1), then for the first level adding module 120, it can be configured to calculate , and the fifth operand p 1 The corresponding first coefficient is 4.

[0060] In some embodiments, Fig. 9 As shown, the adding module 120 may include at least one of a second shifter 121 and a second adding unit 122 .

[0061] The second shifter 121 may be configured to shift the eleventh operand to the left by q bits to generate a twelfth operand, that is, the twelfth operand is 2 q The eleventh operand is a multiple of the first vector A and the second vector B, wherein the eleventh operand may be generated according to the second operand, for example, may be the third operand, the fourth operand or the fifth operand (depending on the specific dot product operation), and q is a positive integer. In a special case, if the dot product of the first vector A and the second vector B can be written in the form of a product of a single operand and an integer power of 2, then the addition module 120 may only include the second shifter 121.

[0062] The second addition unit 122 may be configured to calculate the sum of at least two operands, wherein the at least two operands may include a first operand output by a previous addition module 120, one or more operands output by a corresponding second shifter 121, or a preset constant. Specifically, in the case where the addition module 120 is not the first-stage addition module, it may be configured to perform addition related to the first operand output by the previous-stage addition module 120. In addition, the second addition unit 122 may be configured to calculate the sum of at least a portion of the products of the third operand and the second coefficient, the fourth operand and the third coefficient, and the fifth operand and the first coefficient involved in the addition module 120 in which it is located (depending on the specific dot product operation). In addition, in the case of bitwise inversion of the elements in the first vector or the second vector to convert the subtraction calculation into the addition calculation, the second addition unit 122 in at least part of the addition modules 120 may also be configured to perform addition with a preset constant caused by the bitwise inversion operation, so as to obtain a correct dot product operation result, as will be described in detail later.

[0063] In some specific examples, the second addition unit 122 can be implemented by a compression tree. The compression tree can efficiently compress multiple data into the form of the sum of two or three data. In addition, as needed, the shift operation of related data can be implemented inside the compression tree, thereby realizing the shift and addition operations involved in the dot product operation, and shifting and compressing multiple numbers into the sum of two or three numbers. Common compression trees may include 4:2 compression trees, 3:2 compression trees, and other compression trees with two output ends, and may also include 5:3 compression trees, 6:3 compression trees, 7:3 compression trees, and other compression trees with three output ends. The compression tree here can be a compression tree with any number of input ends and output ends that is currently available or developed in the future, or it can be a compression tree module with any number of input ends and output ends that is implemented by a combination of multiple existing compression trees.

[0064] In some other specific examples, the second adder unit 122 may also be alternatively implemented as a full adder or a combination of a full adder and a half adder, etc. In this case, it may be necessary to use the second shifter 121 and the second adder unit 122 in combination to implement the shift and addition calculations in the dot product operation.

[0065] In still other specific examples, the second adder unit 122 may include a compression tree and a full adder or a combination of a full adder and a half adder. For example, for simplicity, in the embodiments of the present disclosure, a compression tree with two output terminals may be adopted, and then the two output data of the compression tree are added by an adder to obtain the final dot product operation result.

[0066] In some embodiments, as Figure 4 and Figure 5 shown, the arithmetic circuit 100 may further include one or more register modules 110, and the register modules 110 may be communicatively connected to the input end or the output end of the corresponding first-level adder module 120 in the multi-level adder module 120, so as to register the data from the adder module 120 as needed. In a specific example, the register module 110 may be formed by a register or the like.

[0067] In some embodiments, as Figure 4 and Figure 5 shown, in the case where the arithmetic circuit 100 has M levels of adder modules 120, the arithmetic circuit may include at least M register modules 110. Among them, the output end of the m-th level adder module 120 may be communicatively connected to the input end of the m-th register module 110, and the m-th register module 110 may be configured to register the first operand output by the m-th level adder module 120, where m is an integer and 0 ≤ m < M. By setting a corresponding register module 110 for each level of adder module 120, the glitches in the signal can be effectively reduced or even eliminated, which helps to control the correct timing in the arithmetic circuit 100, thereby improving the performance of the arithmetic circuit 100.

[0068] Further, in some embodiments, as Figure 4 and Figure 5 shown, one or more register modules 110 may include a primary register module 110, and the primary register module 110 may be communicatively connected to the input end of the 0-th level adder module 120, and the primary register module 110 may be configured to register A 0 *B 0 , where A 0 may be the first coefficient generated according to the 0-th element a 0 in the first vector, and B 0 may be the first coefficient generated according to the 0-th element b in the second vector.0 The second operand generated. Figure 4 and Figure 5 In the specific example shown, the primary register module 110 may also be communicatively connected to at least one data transmission line 130 to obtain the 0th element in the second vector or the corresponding second operand.

[0069] As mentioned above, when the first vector includes negative coefficients, in order to simplify the operation, the subtraction in the dot product operation can be converted into addition by a bit-by-bit inversion operation. For example, when a negative number is represented by a two's complement code, (-1)*b=~b+1, where ~b is the bit-by-bit inversion of b. It can be seen that the product of a negative coefficient and an element in the second vector can be expressed as the sum of the product of the absolute value of the coefficient and the element and a constant term, where the constant term is determined according to the specific value of the coefficient, and the constant term can be extracted for subsequent processing. Accordingly, in some embodiments, such as Fig.10 As shown, the operation circuit 100 may also include a bitwise inversion module 150, which may be configured to, when the first coefficient in the first vector is a negative number, invert at least one operand generated according to the element in the second vector multiplied by the element in the first vector bit by bit. As required, the bitwise inversion module 150 may be arranged outside the addition modules 120 at each level, or the bitwise inversion module 150 may also be included in at least one level of the addition module 120, without limitation here. According to the constant term extracted during the bitwise inversion process, the preset constant as described above may be determined, and the preset constant may be added to the dot product operation result at an appropriate position, without limitation here. In some embodiments, the bitwise inversion module 150 may be formed by a plurality of inverters. Alternatively, the bitwise inversion module 150 may also be formed in other ways, without limitation here.

[0070] In a specific embodiment of the present disclosure, the first vector A=(-1, 4, -11, 40, 40, -11, 4, -1) and the second vector B=(p 0 , p 1 , p 2 , p 3 , p 4 , p 5 , p 6 , p 7 ) as an example, the operation circuit has Figure 4 The eight register modules 110 and the seven-stage adding modules 120 are arranged in a manner such that the data transmission lines in the operation circuit 100 can sequentially transmit pixel values ​​p 0 、p 1 、p 2 、p 3 、p 4 、p5 、p 6 and p 7 , then its operation process can be described as follows: First, the primary register module 110 obtains din=p 0 , and store S 0 =-p 0 ; Then, the 0th stage addition module 120 calculates S 1 =S 0 +4din, and S 1 Registered in the 0th register module 110 connected to the output terminal of the 0th stage addition module 120, where din=p 1 ; Then, the first stage addition module 120 calculates S 2 =S 1 -8din-2din-din, and S 2 Registered in the first register module 110 connected to the output terminal of the first stage addition module 120, where din=p 2 ; Then, the second stage addition module 120 calculates S 3 =S 2 +32din+8din, and S 3 The second register module 110 connected to the output terminal of the second stage addition module 120 is stored in the second register module 110, wherein din=p 3 ; Then, the third-stage addition module 120 calculates S 4 =S 3 +32din+8din, and S 4 Registered in the third register module 110 connected to the output terminal of the third stage addition module 120, where din=p 4 ; Then, the 4th stage addition module 120 calculates S 5 =S 4 -8din-2din-din, and S 5 Registered in the fourth register module 110 connected to the output terminal of the fourth stage addition module 120, where din=p 5 ; Then, the fifth-stage addition module 120 calculates S 6 =S 5 +4din, and S 6 Registered in the fifth register module 110 connected to the output terminal of the fifth stage addition module 120, where din=p 6 ; Finally, the sixth-stage addition module 120 calculates S7 =S 6 -din, and S 7 The dot product operation result of the first vector and the second vector is stored in the sixth register module 110 connected to the output terminal of the sixth-stage addition module 120 .

[0071] In another specific example of the present disclosure, the first vector A=(-1, 4, -11, 40, 40, -11, 4, -1), the second vector B=(p 0 , p 1 , p 2 , p 3 , p 4 , p 5 , p 6 , p 7 ) as an example, the operation circuit 100 has Figure 5 The eight register modules 110 and the seven-stage adding modules 120 are arranged in a manner, and the operation circuit 100 has two data transmission lines 130 to transmit din and 5din respectively, wherein the data transmission line 130 for transmitting din can be connected to the primary register module 110 and the 0th, 1st, 4th, 5th, and 6th-stage adding modules 120, and the data transmission line 130 for transmitting 5din can be connected to the 1st, 2nd, 3rd, and 4th-stage adding modules 120. The operation process of the operation circuit 100 can be described as follows: First, the primary register module 110 obtains din=p 0 , and store S 0 =-p 0 ; Then, the 0th stage addition module 120 calculates S 1 =S 0 +4din, and S 1 Registered in the 0th register module 110 connected to the output terminal of the 0th stage addition module 120, where din=p 1 ; Then, the first stage addition module 120 calculates S 2 =S 1 -2*5din-din, and S 2 Registered in the first register module 110 connected to the output terminal of the first stage addition module 120, where din=p 2 ; Then, the second stage addition module 120 calculates S 3 =S 2 +8*5din, and S 3 The second register module 110 connected to the output terminal of the second stage addition module 120 is stored in the second register module 110, wherein din=p 3; Then, the third-stage addition module 120 calculates S 4 =S 3 +8*5din, and S 4 Registered in the third register module 110 connected to the output terminal of the third stage addition module 120, where din=p 4 ; Then, the 4th stage addition module 120 calculates S 5 =S 4 -2*5din-din, and S 5 Registered in the fourth register module 110 connected to the output terminal of the fourth stage addition module 120, where din=p 5 ; Then, the fifth-stage addition module 120 calculates S 6 =S 5 +4din, and S 6 Registered in the fifth register module 110 connected to the output terminal of the fifth stage addition module 120, where din=p 6 ; Finally, the sixth-stage addition module 120 calculates S 7 =S 6 -din, and S 7 The dot product operation result of the first vector and the second vector is stored in the sixth register module 110 connected to the output terminal of the sixth-stage addition module 120 .

[0072] In the technical solution disclosed in the present invention, by converting a multiplication-accumulation operation of more groups of data performed by a single addition module in a dot product operation into a hierarchical multiplication-accumulation operation performed by multiple addition modules, each addition module can be used to perform multiplication-accumulation operations between fewer groups of data, which can reduce or even eliminate the logic of direct connection of registers in the operation circuit for performing dot product operations, thereby effectively reducing or even eliminating the risk of hold time violations in the operation circuit. Further, since fewer multiplication-accumulation operations or shift and addition operations are performed in each addition module, it can be formed by relatively simple addition units (for example, a small number of adders, etc.), thereby reducing operation delays, improving the performance of the operation circuit and the computing device containing it, and reducing the area and power consumption of the operation circuit and the computing device containing it. In addition, since the number of stages of combinational logic is reduced, the burrs in the signal can be well controlled, and the power consumption of the operation circuit and the computing device can be further optimized. In some embodiments, the preset multiples of certain elements involved in the vector dot product operation can also be pre-calculated, effectively reducing the number of shifts and / or addition calculations required in subsequent calculations, thereby reducing the number of shifters and / or addition units required in the addition module, making the structure of the operation circuit simpler, reducing the circuit area, shortening the critical path, making the timing easier to converge, reducing the delay in the circuit, and reducing the circuit power consumption. In some examples, the operation circuit and computing device disclosed in the present invention can be used in the field of image interpolation, thereby effectively improving the efficiency and effect of image processing.

[0073] The words "left", "right", "front", "back", "top", "bottom", "up", "down", "high", "low", etc., in the specification and claims, if present, are used for descriptive purposes and are not necessarily used to describe an unchanging relative position. It should be understood that the words so used are interchangeable under appropriate circumstances, so that the embodiments of the present disclosure described herein, for example, can operate in other orientations than those shown or otherwise described herein. For example, when the device in the drawings is turned over, features originally described as "above" other features may now be described as "below" the other features. The device may also be oriented in other ways (rotated 90 degrees or in other orientations), and the relative spatial relationships will be interpreted accordingly.

[0074] In the specification and claims, when an element is referred to as being "on", "attached", "connected", "coupled", or "contacting" another element, the element may be directly on, directly attached, directly connected, directly coupled, or directly contacting another element, or one or more intermediate elements may be present. In contrast, when an element is referred to as being "directly" "on", "directly attached", "directly connected", "directly coupled", or "directly contacting" another element, there will be no intermediate elements. In the specification and claims, a feature being arranged "adjacent" to another feature may refer to a feature having a portion that overlaps with an adjacent feature or a portion that is located above or below an adjacent feature.

[0075] As used herein, the word "exemplary" means "serving as an example, instance, or illustration" rather than as a "model" to be exactly copied. Any implementation described as an example herein is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, the present disclosure is not to be limited by any expressed or implied theory given in the technical field, background, summary, or detailed description.

[0076] As used herein, the term "substantially" is intended to include any minor variations due to design or manufacturing imperfections, device or component tolerances, environmental influences, and / or other factors. The term "substantially" also allows for deviations from a perfect or ideal situation due to parasitic effects, noise, and other practical considerations that may exist in actual implementations.

[0077] In addition, the terms "first", "second" and the like may also be used herein for reference purposes only and are not intended to be limiting. For example, the terms "first", "second" and other such numerical terms referring to structures or elements do not imply a sequence or order unless the context clearly indicates otherwise.

[0078] It should also be understood that when the term “include / comprises” is used in this document, it indicates the presence of the specified features, integers, steps, operations, units and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, units and / or components and / or their combinations.

[0079] In addition, when used in this application, the words "herein", "above", "below", "hereunder", "above" and words of similar meaning shall refer to the entirety of this application rather than any particular portion of this application. In addition, unless otherwise expressly stated or understood in the context of use, conditional language used herein, such as "may", "might", "for example", "such as", etc., is generally intended to express that certain embodiments include, while other embodiments do not include certain features, elements and / or states. Therefore, such conditional language is generally not intended to imply that one or more embodiments require features, elements and / or states in any way, or whether these features, elements and / or states are included or performed in any particular embodiment.

[0080] In the present disclosure, the term "providing" is used in a broad sense to cover all ways of obtaining an object, so "providing an object" includes but is not limited to "purchasing", "preparing / manufacturing", "arranging / setting", "installing / assembling", and / or "ordering" an object, etc. In addition, in the present disclosure, the terms "circuit", "unit" and "module" can be used interchangeably.

[0081] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. The terms used herein are for the purpose of describing specific embodiments only and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0082] Those skilled in the art will appreciate that the boundaries between the above operations are merely illustrative. Multiple operations may be combined into a single operation, a single operation may be distributed in additional operations, and operations may be performed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be changed in various other embodiments. However, other modifications, changes, and substitutions are also possible. The aspects and elements of all embodiments disclosed above may be combined in any manner and / or in combination with aspects or elements of other embodiments to provide multiple additional embodiments. Therefore, this specification and the accompanying drawings should be regarded as illustrative, not restrictive. In fact, the novel devices, methods, and systems described herein may be embodied in various other forms. In addition, various omissions, substitutions, and changes may be made to the forms of the methods and systems described herein without departing from the spirit of the present disclosure. For example, although blocks are presented in a given arrangement, alternative embodiments may perform similar functions with different components and / or circuit topologies, and may delete, move, add, subdivide, combine, and / or modify some blocks. Each of these blocks may be implemented in various different ways.

[0083] The various embodiments of the present disclosure may be described in a progressive manner, and the same or similar parts between the various embodiments may be referred to each other, and each embodiment focuses on the differences from other embodiments. In the present disclosure, the descriptions with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In the present disclosure, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in a suitable manner in any one or more embodiments or examples.

[0084] Although some specific embodiments of the present disclosure have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present disclosure. The various embodiments disclosed herein may be combined in any manner without departing from the spirit and scope of the present disclosure. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A computing circuit, characterized in that: The operation circuit is at least used to calculate the dot product of a first vector and a second vector, wherein the first vector is a coefficient vector known in advance, and the operation circuit includes: A multi-stage addition module, wherein an input end of a subsequent stage addition module is communicatively connected to an output end of a previous stage addition module adjacent to the stage addition module, and the subsequent stage addition module is configured to at least calculate the sum of a first operand output by the previous stage addition module and a product obtained by multiplying at least one set of first coefficients and second operands, wherein the first coefficient is generated based on at least one element in a first vector, and the second operand is generated based on at least one element in a second vector.

2. The operation circuit according to claim 1, characterized in that When the dimensions of the first vector and the second vector are N respectively, the operation circuit has an N-1-stage addition module, wherein: The 0th stage addition module is configured to calculate A0*B0+A1*B1, where A0 is a first coefficient generated based on the 0th element a0 in the first vector, A1 is a first coefficient generated based on the 1st element a1 in the first vector, B0 is a second operand generated based on the 0th element b0 in the second vector, and B1 is a second operand generated based on the 1st element b1 in the second vector; and The i-th stage addition module is configured to calculate S i +A i+1 *B i+1 , where S i is the first operand output by the i-1th level addition module, A i+1 It is based on the i+1th element a in the first vector i+1 The first coefficient generated, and B i+1 is based on the i+1th element b in the second vector i+1 The second operand generated, where i is an integer and 0 <i<N-1。 3. The operation circuit according to claim 1, characterized in that: The operation circuit also includes: One or more data transmission lines, each of the one or more data transmission lines is communicatively connected to at least one stage of the addition module, and the data transmission line is configured to transmit the element in the second vector or the second operand to the corresponding addition module.

4. The operation circuit according to claim 1, characterized in that: At least one level of the multi-level addition module is configured to obtain a third operand, and is configured to determine a corresponding set of products obtained by multiplying the first coefficient and the second operand based on the product obtained by multiplying the second coefficient and the third operand, wherein the third operand is a preset multiple of the corresponding fourth operand, the fourth operand is generated based on at least one target element in the second vector, and in the dot product calculation, the absolute value of the element in the first vector multiplied by the target element in the second vector is greater than or equal to the absolute value of the preset multiple, the preset multiple is greater than 1, and for each fourth operand and the corresponding third operand, the product of the second coefficient and the preset multiple is less than or equal to the first coefficient.

5. The operation circuit according to claim 4, characterized in that: The at least one level of addition module is further configured to determine a corresponding set of products obtained by multiplying the first coefficient and the second operand according to the product obtained by multiplying the third coefficient and the fourth operand corresponding to the third operand, wherein, for each fourth operand and the corresponding third operand, the sum of the product of the second coefficient and the preset multiple plus the third coefficient is equal to the first coefficient; and / or The at least one stage addition module is also configured to determine a corresponding set of products obtained by multiplying the first coefficient and the second operand based on the product obtained by multiplying the first coefficient and the fifth operand, wherein the fifth operand is generated based on at least one element in the second vector except the element used to generate the third operand.

6. The operation circuit according to claim 4, characterized in that: The operation circuit also includes: A multiple operation module is configured to calculate a preset multiple of a fourth operand to generate a corresponding third operand.

7. The operation circuit according to claim 6, characterized in that: The preset multiple is determined according to the first vector; or The preset multiple includes at least one of 3 times, 5 times and 7 times.

8. The operation circuit according to claim 6, characterized in that: The multiple operation module includes one or more multiple calculation units, and the multiple calculation unit includes: A first shifter is configured to shift the sixth operand to the left by p bits to generate a seventh operand, wherein the seventh operand is 2 p times the sixth operand, the sixth operand is a positive integer multiple of the second operand, and p is a positive integer; or A first adding unit is configured to add an eighth operand and a ninth operand to generate a tenth operand, wherein the eighth operand is a positive integer multiple of the second operand, and the ninth operand is a positive integer multiple of the second operand.

9. The operation circuit according to claim 1, characterized in that: The addition module includes at least one of the following: A second shifter configured to shift the eleventh operand to the left by q bits to generate a twelfth operand, wherein the twelfth operand is 2 q times an eleventh operand, the eleventh operand being generated based on the second operand, and q is a positive integer; and A second adding unit, wherein the second adding unit is configured to calculate the sum of at least two operands, wherein the at least two operands include a first operand output by a previous stage adding module, one or more operands output by a corresponding second shifter, or a preset constant.

10. The operation circuit according to claim 1, characterized in that: The operation circuit also includes: One or more register modules, wherein the register modules are communicatively connected to the input end or output end of the corresponding first-stage adding module in the multi-stage adding module.

11. The operation circuit according to claim 10, characterized in that: In the case where the operation circuit has M-level addition modules, the operation circuit includes at least M register modules, wherein the output end of the m-th level addition module is communicatively connected to the input end of the m-th register module, and the m-th register module is configured to register the first operand output by the m-th level addition module, wherein m is an integer and 0≤m <M。 12. The operation circuit according to claim 10, characterized in that: The one or more register modules include a primary register module, which is communicatively connected to the input end of the 0th stage addition module, and the primary register module is configured to store A0*B0, wherein A0 is a first coefficient generated based on the 0th element a0 in the first vector, and B0 is a second operand generated based on the 0th element b0 in the second vector.

13. The operation circuit according to claim 1, characterized in that: The operation circuit also includes: The bitwise inversion module is configured to, when an element in the first vector is a negative number, bitwise invert at least one operand generated according to an element in the second vector multiplied by the element in the first vector.

14. The operation circuit according to claim 1, characterized in that: The operation circuit is configured to perform an image interpolation operation, the first vector is a coefficient vector for image interpolation, and at least two elements of the second vector are not provided to the operation circuit at the same time.

15. A computing device, characterized in that: The computing device comprises one or more computing circuits, wherein the computing circuit is a computing circuit according to any one of claims 1 to 14.

16. The computing device according to claim 15, characterized in that In the case where the computing device includes a plurality of operation circuits, at least two operation circuits operate in parallel.

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