Self-reference PUF device, read-write circuit and read-write circuit array

Abstract

The invention provides a self-reference PUF device, a read-write circuit and a read-write circuit array. The PUF device comprises a middle magnetic tunnel junction (MTJ), and a first MTJ and a second MTJ which are respectively positioned on two sides of the middle MTJ, a gap exists between the first MTJ and the middle MTJ, a gap exists between the second MTJ and the middle MTJ, the first MTJ, the middle MTJ and the second MTJ use the same free layer, and the width of the free layer is gradually reduced from the part located in the middle MTJ to the parts of the first MTJ and the second MTJ so as to form a magnetic anisotropic gradient; a voltage control layer is arranged on the free layer and located in the area of the middle MTJ. The MTJs at the two ends can serve as reading devices, the magnetic domain wall can be fixed in the area of the middle MTJ in the initial state, then the magnetic domain wall is driven to randomly relax towards the two sides based on anisotropy, after the magnetic domain wall is stabilized on the MTJ on one side, the MTJ forms a low-resistance state, the MTJ on the corresponding other side is in a high-resistance state, and therefore the self-reference structure of the device is formed, and the self-reference performance of the device is improved. And the mode can improve the reading margin of the device.

Description

Technical Field

[0001] The present disclosure belongs to the field of semiconductor technology, and in particular relates to a self-referenced physical unclonable function (PUF) device, a read-write circuit, and a read-write circuit array. Background Art

[0002] As people's requirements for electronic device integration, high computing power and data security gradually increase, the storage devices of electronic devices can be designed as storage-computing integrated circuits, and PUF devices are used as encryption devices in storage-computing integrated circuits to generate keys for data.

[0003] The principle of PUF device to generate keys is to construct a physical unclonable function based on ferromagnetic properties and non-ideal properties of the device to serve as the key of the data. Accordingly, the formation of PUF devices requires the cooperation of magnetic domain wall devices and circuits. The storage and computing circuit determines the storage state based on the resistance size, and then reads and writes data. Based on this, the storage reliability of the storage and computing circuit depends on the read margin (Sense Margin, SM) of the resistance.

[0004] However, the magnetic domain wall device included in the conventional PUF device has a low tunnel magnetoresistance ratio (TMR), which can easily lead to misreading under disturbance, resulting in low storage reliability of the storage-computing integrated circuit. Summary of the invention

[0005] The present disclosure proposes a self-referenced PUF device, a read-write circuit, and a read-write circuit array. A PUF device formed by three magnetic tunnel junctions (MTJs) is designed. By triggering the magnetic domain wall to fluctuate to one side of the MTJ, complementary high and low resistance states are generated inside the PUF device, thereby improving the read margin of the device.

[0006] The first aspect of the present disclosure provides a self-referenced PUF device, the PUF device comprising: an intermediate magnetic tunnel junction MTJ, and a first MTJ and a second MTJ respectively located on both sides of the intermediate MTJ;

[0007] There are gaps between the first MTJ and the second MTJ and the middle MTJ respectively, the first MTJ, the middle MTJ and the second MTJ use the same free layer, and the width of the free layer is gradually reduced from a portion located in the middle MTJ to portions of the first MTJ and the second MTJ respectively, so as to form a magnetic anisotropy gradient;

[0008] A voltage control layer is disposed on the free layer and in a region located at the middle MTJ.

[0009] In the embodiment of the present disclosure, in an initial state, the first MTJ receives an input current, and a single magnetic domain wall is formed in the first MTJ.

[0010] In the disclosed embodiment, when the voltage control layer applies a voltage to the intermediate MTJ, the magnetic domain wall is pinned to a pinning region in the intermediate MTJ corresponding to the voltage control layer, so that the PUF device enters a state capable of generating a key.

[0011] In the embodiment of the present disclosure, after the voltage-controlled layer stops applying voltage to the intermediate MTJ, the magnetic domain wall relaxes to the first MTJ or the second MTJ under the drive of the magnetic anisotropy gradient, and stabilizes in the region with the smallest width in the first MTJ or the region with the smallest width in the second MTJ.

[0012] In the embodiment of the present disclosure, in the initial state, the magnetic moment directions of the region of the free layer corresponding to the first MTJ and the region corresponding to the second MTJ are both spin-down;

[0013] If the magnetic domain wall is stable in the region where the width of the first MTJ is the smallest, the magnetic moment direction of the free layer in the region where the magnetic domain wall of the first MTJ is stable rotates to spin-up, so that the resistance of the first MTJ is smaller than the resistance of the second MTJ;

[0014] If the magnetic domain wall is stable in the area where the width of the second MTJ is the smallest, the magnetic moment direction of the free layer in the area where the magnetic domain wall of the second MTJ is stable rotates to spin-up, so that the resistance of the second MTJ is smaller than the resistance of the first MTJ.

[0015] In the embodiment of the present disclosure, the material of the pressure control layer is a composite oxide.

[0016] An embodiment of the second aspect of the present disclosure provides a read-write circuit, the read-write circuit comprising a first drive circuit, a second drive circuit, a third drive circuit and a self-reference PUF device, the self-reference PUF device being as described in the first aspect;

[0017] The first driving circuit is connected to the first MTJ and is used to input a level signal to the first MTJ;

[0018] The second driving circuit is connected to the second MTJ and is used to input a level signal to the second MTJ;

[0019] The third driving circuit is connected to the middle MTJ and is used to input a level signal to the middle MTJ.

[0020] In the disclosed embodiment, a state control circuit is further included, wherein the state control circuit is connected to the voltage control layer of the intermediate MTJ;

[0021] The first driving circuit includes a first bit line and a first switch device; the second driving circuit includes a second bit line and a second switch device; the third driving circuit includes a read-write control circuit and a third switch device;

[0022] The source of the first switch device is connected to the first bit line, the gate of the first switch device is connected in parallel with the state control line, and the drain of the first switch device is connected to the bottom electrode of the first MTJ;

[0023] A source of the second switch device is connected to the second bit line, a gate of the second switch device is connected to the state control line, and a drain of the second switch device is connected to the bottom electrode of the second MTJ;

[0024] The drain of the third switch device is connected to the bottom electrode of the middle MTJ, and the gate of the third switch device is connected to the read-write control line.

[0025] In the embodiment of the present disclosure, when a high level signal is input to the voltage control layer of the intermediate MTJ through the state control line,

[0026] The first switch device is driven by the first bit line to input a high level signal to the first MTJ, the second switch device is driven by the second bit line to input a low level signal to the second MTJ, and the third switch device is driven by the read-write control line to input a low level signal to the intermediate MTJ, the self-reference PUF device generates a key, and the read-write circuit is in a data writing state;

[0027] The first switching device is driven by the first bit line to input a high level signal to the first MTJ, the second switching device is driven by the second bit line to input a high level signal to the second MTJ, and the third switching device is driven by the read-write control line to input a high level signal to the intermediate MTJ, and the read-write circuit is in a data reading state.

[0028] An embodiment of a third aspect of the present disclosure provides a read / write circuit array, comprising a preset number of read / write circuits, a control circuit, and a precharge amplifier, wherein any read / write circuit is as described in the second aspect;

[0029] The control circuit includes clamp circuits connected in parallel with the preset number of read-write circuits, respectively, so as to control the working state of the corresponding read-write circuits through the output voltage of the clamp circuits;

[0030] The precharge amplifier includes an amplifier circuit, and a first voltage detection circuit and a second voltage detection circuit connected in parallel with the amplifier circuit; the first voltage detection circuit is connected in parallel with the first MTJ of the preset number of read-write circuits; the second voltage detection circuit is connected in parallel with the second MTJ of the preset number of read-write circuits;

[0031] For the read-write circuit controlled by the control circuit to enter the data reading state, the voltage of the first MTJ in the read-write circuit is read by the first voltage detection circuit, the voltage of the second MTJ in the read-write circuit is read by the second voltage detection circuit, the difference between the voltage read by the first voltage detection circuit and the voltage read by the second voltage detection circuit is amplified, and the read data is output according to the amplified difference.

[0032] The technical solution provided in the embodiments of the present disclosure has at least the following technical effects or advantages:

[0033] The PUF device proposed in the embodiment of the present disclosure includes: an intermediate magnetic tunnel junction MTJ, and a first MTJ and a second MTJ located on both sides of the intermediate MTJ, respectively. The first MTJ, the intermediate MTJ and the second MTJ use the same free layer, and the width of the free layer gradually decreases from the part located in the intermediate MTJ to the parts of the first MTJ and the second MTJ, respectively. In this way, a magnetic shape anisotropy gradient can be formed. A voltage-controlled layer is provided in the area above the free layer and located in the intermediate MTJ. Thus, the MTJs at both ends can be used as reading devices, and the magnetic domain wall can be fixed in the area of ​​the intermediate MTJ in the initial state. Then, by driving the magnetic domain wall to relax randomly to both sides based on anisotropy, after the magnetic domain wall is stabilized on one side of the MTJ, the MTJ forms a low-resistance state, and the corresponding MTJ on the other side is in a high-resistance state, thereby forming a self-reference structure of the device, and this mode can improve the reading margin of the device.

[0034] Additional aspects and advantages of the present disclosure will be given in part in the following description and in part will become apparent from the following description or be learned through practice of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] By reading the detailed description of the preferred embodiment below, various other advantages and benefits will become clear to those of ordinary skill in the art. The accompanying drawings are only used for the purpose of illustrating the preferred embodiment and are not considered to be limitations of the present disclosure. In addition, the same reference symbols are used to represent the same components throughout the accompanying drawings.

[0036] In the attached picture:

[0037] Figure 1 A schematic diagram of the structure of a self-reference PUF device provided by an embodiment of the present disclosure is shown;

[0038] Figure 2 Shows Figure 1 An exemplary partition diagram of the free layer of the self-referenced PUF device;

[0039] Figure 3 A schematic diagram showing an exemplary scenario of magnetic domain wall relaxation provided by an embodiment of the present disclosure is shown;

[0040] Figure 4 A schematic diagram showing the structure of a read-write circuit provided by an embodiment of the present disclosure is shown;

[0041] Figure 5 A schematic diagram showing the structure of a read / write circuit array provided by an embodiment of the present disclosure is shown;

[0042] Figure 6 A schematic diagram of the encryption and decryption process provided by an embodiment of the present disclosure is shown;

[0043] Figure 7 A schematic diagram showing comparison of simulation results of a reading feature provided by an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0044] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0045] The terms used in the following embodiments of the present disclosure are for the purpose of describing specific embodiments and are not intended to be limiting of the technical solutions of the present disclosure. As used in the specification and appended claims of the present disclosure, the singular expressions "one", "a kind", "said", "above", "the" and "this" are intended to also include plural expressions, unless the context clearly indicates otherwise. It should also be understood that although the terms first, second, etc. may be used to describe a certain class of objects in the following embodiments, the objects should not be limited to these terms. These terms are used to distinguish the specific implementation objects of this class of objects. For example, the terms first, second, etc. are used to describe MTJs in the following embodiments, but MTJs are not limited to these terms. These terms are only used to distinguish different MTJs. The same is true for other classes of objects that may be described by the terms first, second, etc. in the following embodiments, which will not be repeated here.

[0046] It should be noted that, unless otherwise specified, the technical terms or scientific terms used in the present disclosure should have the common meanings understood by those skilled in the art to which the present disclosure belongs.

[0047] The following introduces the implementation scenarios and related technologies involved in the embodiments of the present disclosure.

[0048] The disclosed embodiments relate to the in-memory computing technology scenario. The integrated computing circuit for implementing in-memory computing is an integrated circuit. By integrating data computing and data storage on the same chip or the same circuit unit, the data transmission between the processor and the memory is significantly reduced, thereby reducing power consumption, improving data processing speed and efficiency, and is widely used in various electronic devices. In order to improve data security while ensuring integration, PUF devices are usually integrated as part of the integrated computing circuit, so that in the integrated computing circuit, the PUF device is used as a part of key generation and storage. In the process of writing data, the key generated by the PUF is used to encrypt data, and in the process of reading data, the key generated by the PUF is used to decrypt.

[0049] PUF devices are hardware security technologies that use the physical property of ferromagnetic materials to form random magnetic domain wall structures during the manufacturing process to generate unique and non-copyable authentication keys. That is, the function of PUF devices depends on ferromagnetic properties. Accordingly, PUF devices can usually be semiconductor devices with ferromagnetic properties, such as MTJ devices.

[0050] The storage and computing circuit uses a reference resistor R in the process of reading and writing data. ref Characterizes the state of the stored data. Specifically, according to R ref The reference voltage V ref , if the read voltage V read Greater than the reference voltage V ref , the output is high level, and the read data is, for example, "1"; if the read voltage V read Less than the reference voltage V ref , the output is low level, and the read data is, for example, "0". Accordingly, the read margin is usually used to characterize the reliability of the storage-computing integrated circuit. The read margin refers to the ability to accurately distinguish different storage states (such as "0" and "1") when reading data in a storage unit (which can be understood as a storage-computing integrated circuit). The read margin can be expressed as: |V read -V ref | / V ref ×100%.

[0051] Taking the commonly used 1T1M spin transfer torque (STT) effect memory composed of a transistor (Transistor, T) and a magnetic tunnel junction (MTJ), or the 2T1M spin-orbit torque (SOT) magnetic random access memory composed of two transistors (Transistor, T) and a magnetic tunnel junction (MTJ) as an example, the reference resistor R ref Both can be characterized as R ref =1 / 2(R p +R ap ), where R p is the resistance of the MTJ when the reference layer and the free layer are magnetized in parallel, R ap is the resistance of the MTJ when the magnetizations of the reference layer and the free layer are antiparallel.

[0052] Since the tunnel magnetoresistance TMR of the same MTJ is low, the reading margin of the conventional storage-computing integrated circuit is low, and the fluctuation of the MTJ spin process can easily cause misreading of the MTJ state, thereby reducing the read and write reliability of the storage-computing integrated circuit.

[0053] In view of this, the technical solution proposed in the embodiment of the present disclosure designs a PUF device formed by three magnetic tunnel junctions (MTJs), and triggers the magnetic domain wall to fluctuate to one side of the MTJ, so that complementary self-referenced high and low resistance states are generated inside the PUF device, thereby improving the reading margin of the device and further improving the reading and writing reliability of the storage and computing integrated circuit.

[0054] A self-reference PUF device, a read / write circuit, and a read / write circuit array proposed according to an embodiment of the present disclosure are described below in conjunction with the accompanying drawings.

[0055] like Figure 1 As shown, the embodiment of the present disclosure provides a self-reference PUF device, the PUF device includes: an intermediate MTJ 10, and a first MTJ 20 and a second MTJ 30 respectively located on both sides of the intermediate MTJ 10. There are gaps between the first MTJ 20 and the second MTJ 30 and the intermediate MTJ 10, respectively. The first MTJ 20, the intermediate MTJ 10 and the second MTJ 30 use the same free layer 100, and the width of the free layer 100 is gradually reduced from the portion located in the intermediate MTJ 10 to the portion of the first MTJ 20 and the second MTJ 30, respectively, to form a magnetic anisotropy gradient. A voltage control layer 40 is provided on the free layer 100 and in the region located in the intermediate MTJ 10.

[0056] Exemplarily, the maximum width of the free layer 100 is, for example, 50 nanometers (nm), and the free layer 100 gradually decreases from the portion located at the middle MTJ 10 to the first MTJ 20 and the second MTJ 30, for example, to form a diamond shape.

[0057] It should be understood that the width of the free layer 100 is gradually reduced from the middle MTJ 10 to the first MTJ 20 and the second MTJ 30, respectively, in order to form a magnetic shape anisotropy gradient to support the relaxation of the magnetic domain wall between the MTJs under the action of anisotropy. Based on this, Figure 1 The rhombus shape of the free layer 100 is only a schematic description and does not limit the structure of the self-reference PUF device of the present disclosure. In some other implementations, the free layer 100 may also be an ellipse, which is not limited by the present disclosure.

[0058] In order to conveniently explain the relaxation process of the magnetic domain wall between the middle MTJ 10, the first MTJ 20 and the second MTJ 30, and the rotation of the magnetic moment direction of each region of the free layer 100, the embodiment of the present disclosure will be Figure 1 The free layer 100 in is divided into several regions.

[0059] Figure 1 An exemplary partition of the free layer 100 is as follows Figure 2 As shown, five regions are included, among which region 1 may correspond to the first MTJ 20; region 2 may correspond to the gap between the first MTJ 20 and the middle MTJ 10, that is, the barrier region between the first MTJ 20 and the middle MTJ 10; region 3 may correspond to the middle MTJ 10; region 4 may correspond to the gap between the middle MTJ 10 and the second MTJ 30, that is, the barrier region between the second MTJ 30 and the middle MTJ 10; and region 5 may correspond to the second MTJ 30.

[0060] For example, the lengths of region 1 and region 5 may be 31 nm, that is, the lengths of the first MTJ 20 and the second MTJ 30 are both 31 nm. The lengths of region 2 and region 4 may be 45 nm, and the length of region 3 may be 20 nm, that is, the length of the middle MTJ 10 is 20 nm.

[0061] Among them, any MTJ in the middle MTJ 10, the first MTJ 20 and the second MTJ 30 includes a free layer (Free Layer, FL) (also called the top ferromagnetic layer), a barrier layer (Barrier Layer, BL), a reference layer (Reference Layer, RL), a bottom electrode (Bottom Electrode, BE) and other material layers from top to bottom, which are not described in detail here. In the initial state, that is, when no current or voltage is input, the magnetic moment direction of the free layer 100 spins down, and the magnetic moment directions of the reference layer in the middle MTJ 10, the reference layer in the first MTJ 20 and the reference layer in the second MTJ 30 all spin down, then, the magnetic moment direction of the reference layer in the first MTJ 20 is parallel to the magnetic moment direction of the free layer 100 region 1 part, at this time, the first MTJ 20 is in a high resistance state, and the magnetic moment direction of the reference layer in the second MTJ 30 is parallel to the magnetic moment direction of the free layer 100 region 5 part, and the second MTJ 30 is in a high resistance state.

[0062] For example, the first MTJ 20 receives an input current, a single magnetic domain wall is formed in the first MTJ 20, and then, if the voltage control layer 40 applies a voltage to the middle MTJ, the magnetic domain wall can be pinned at Figure 2 The region 3 shown in FIG. 1 , i.e., the pinning region in the middle MTJ 10 corresponding to the voltage control layer 40, enables the PUF device to enter a state where a key can be generated. At this time, the magnetic domain wall can oscillate with the assistance of thermal disturbance.

[0063] It should be understood that the above description is only based on the example of the first MTJ 20 receiving the input current. In another implementation, the second MTJ 30 receives the input current. If the voltage control layer 40 applies a voltage to the middle MTJ, the magnetic domain wall can also be pinned. Figure 2 The area 3 shown in FIG. will not be repeated here.

[0064] Furthermore, after the voltage-controlled layer 40 stops applying voltage to the intermediate MTJ 10, the magnetic domain wall relaxes to the first MTJ 20 or the second MTJ 30 under the drive of the magnetic anisotropy gradient, and stabilizes in the region with the smallest width in the first MTJ 20 or the region with the smallest width in the second MTJ 30.

[0065] refer to Figure 3 , Figure 3FIG. 2 shows an exemplary scenario schematic diagram of magnetic domain wall relaxation provided by an embodiment of the present disclosure. For example, within 0 to 2 nanoseconds (ns), a current is passed through the first MTJ 20 to form a single magnetic domain wall and drive the magnetic domain wall to move to region 3. At the same time, a pinning voltage is applied to the voltage control layer 40 to form a potential well pinning region with low magnetocrystalline anisotropy in region 3. At this time, Figure 3 As shown in the figure from 2ns to 20ns, the domain wall is pinned in region 3 and oscillates randomly around the geometric center at room temperature. During the key creation process, the domain wall is in a metastable state after the voltage control voltage of the voltage control layer 40 is removed, and under the influence of thermal disturbance and shape anisotropy, it randomly relaxes from region 3 to region 2 or region 4, and stabilizes in the region with the smallest width in region 1 after oscillation.

[0066] The phenomenon that the magnetic domain wall is stable in any MTJ can be called "nucleation". If the magnetic domain wall is stable in the area where the width of the first MTJ 20 is the smallest, the free layer 100 is in the area where the magnetic domain wall of the first MTJ 20 is stable (i.e. Figure 2 The magnetic moment direction of the region 1 in the first MTJ 20 is rotated to spin upward, so that the resistance of the first MTJ 20 is smaller than the resistance of the second MTJ 30. Similarly, if the magnetic domain wall is stable in the region with the smallest width of the second MTJ 30, the free layer is in the region where the magnetic domain wall of the second MTJ 30 is stable (i.e. Figure 2 The magnetic moment direction of region 5) in the second MTJ is rotated to spin upward, so that the resistance value of the second MTJ 30 is smaller than the resistance value of the first MTJ 20.

[0067] It should be noted that during the random relaxation of the magnetic domain wall, the pinned magnetic domain wall continues to remain in the region 3, and the relaxation part fluctuates differently based on the degree of influence of thermal disturbance, and the nucleation area range is also different. Correspondingly, the size of the region where the magnetic moment direction of the free layer 100 rotates to spin-up is relatively random.

[0068] It can be seen that if the MTJs at both ends are used as reading devices, the magnetic domain walls can be driven to relax randomly to both sides based on anisotropy. After the magnetic domain walls are stabilized on one side of the MTJ, the MTJ forms a low-resistance state, while the corresponding MTJ on the other side is in a high-resistance state, thereby forming a self-reference structure of the device. This mode can improve the reading margin of the device.

[0069] In the process of digital storage and in-memory encryption, the first MTJ 20 and the second MTJ 30 can be used as reading devices. After the self-reference PUF device is nucleated, the normalized perpendicular magnetization (M z ) is used to embody. For example, if the magnetization directions of the reference layer in the first MTJ 20 and the free layer 100 region 1 are parallel, it is considered that the magnetic domain wall precesses to the Mz =-1, during the reading process, the first MTJ 20 exhibits a low resistance, and at this time, the data stored in the first MTJ 20 is "0". If the magnetization directions of the reference layer in the first MTJ 20 and the free layer 100 region 1 are antiparallel, it is considered that the magnetic domain wall precesses to the M z =1, during the reading process, the first MTJ 20 exhibits a high resistance, and at this time, the data stored in the first MTJ 20 is "1". At the same time, the magnetization direction of the free layer 100 in region 5 (corresponding to the second MTJ 30) is opposite to the magnetization direction of region 1 (corresponding to the first MTJ 20), thereby determining the key information generated by the self-reference PUF device.

[0070] It can be seen that the embodiment of the present disclosure uses the first MTJ as the storage terminal of the key unit and uses the second MTJ as the reference resistor to replace the traditional reference resistor. Therefore, the read margin can be expressed as: |V 第一MTJ -V 第二MTJ | / V 第二MTJ ×100%, and the improved reading margin is greater than the traditional reading margin.

[0071] In some implementations, Figure 1 The material of the pressure control layer 40 in the embodiment can be a composite oxide, such as barium titanate (BaTiO 3 ), bismuth ferrite (BiFeO 3 ) or hafnium zirconium oxide (HfZrO 2 ) etc. Since the composite oxide has a spontaneous polarization that can be tuned by an external electric field, its saturation polarization can be achieved in a bipolar manner, where the ferroelectricity originates from the non-centrosymmetric displacement of atoms in the lattice below the Curie temperature, and this displacement can affect the ferromagnetic / ferroelectric (multiferroic) interface. Based on this, the use of composite oxide materials as voltage-controlled layers has the advantages of fast writing / reading, good durability and high energy efficiency.

[0072] In summary, the present invention designs a PUF device formed by three MTJs, and triggers the magnetic domain wall to fluctuate to the MTJ on one side, so that complementary high and low resistance states are generated inside the PUF device, thereby forming a self-reference structure on the same device, which can not only improve the reading margin of the device, but also help to reduce the size of the device and improve the degree of integration.

[0073] See also Figure 4 , Figure 4 A schematic diagram of the structure of a read-write circuit provided by an embodiment of the present disclosure is shown. Figure 4 The illustrated read / write circuit includes a first drive circuit 41, a second drive circuit 42, a third drive circuit 43 and a self-reference PUF device, wherein the self-reference PUF device is as follows: Figure 1 The exemplary embodiments are described in detail and will not be described in detail here.

[0074] The first driving circuit 41 is connected to the first MTJ for inputting a level signal to the first MTJ; the second driving circuit 42 is connected to the second MTJ for inputting a level signal to the second MTJ; the third driving circuit 43 is connected to the intermediate MTJ for inputting a level signal to the intermediate MTJ. The first driving circuit 41, the second driving circuit 42 and the third driving circuit 43 can be used to collaboratively drive the self-reference PUF device to generate a key and read data.

[0075] For example, refer again to Figure 4 The read / write circuit further includes a state control line 44, and the state control line (wordline, WL) 44 is connected to the voltage control layer of the middle MTJ.

[0076] The first driving circuit 41 includes a first bit line 411 and a first switch device 412, wherein the source of the first switch device 412 is connected to the first bit line 411, the gate of the first switch device 412 is connected in parallel to the state control line 44, and the drain of the first switch device 412 is connected to the bottom electrode of the first MTJ. In this way, a current can be output to the source of the first switch device 412 through the first bit line 411, so as to output a level signal to the bottom electrode of the first MTJ through the drain of the first switch device 412, thereby driving the working state of the first MTJ.

[0077] The second driving circuit 42 includes a second bit line 421 and a second switch device 422, wherein the source of the second switch device 422 is connected to the second bit line 42, the gate of the second switch device 422 is connected to the state control line 44, and the drain of the second switch device 422 is connected to the bottom electrode of the second MTJ. In this way, a current can be output to the source of the second switch device 422 through the second bit line 421, so as to output a level signal to the bottom electrode of the second MTJ through the drain of the second switch device 422, thereby driving the working state of the second MTJ.

[0078] The third driving circuit 43 includes a read / write control circuit 431 and a third switch device 432, wherein the drain of the third switch device 432 is connected to the bottom electrode of the middle MTJ, and the gate of the third switch device 432 is connected to the read / write control circuit 431. The read / write control circuit 431 can output a current to the source of the third switch device 432 to output a level signal to the bottom electrode of the middle MTJ through the drain of the third switch device 432, thereby driving the working state of the middle MTJ.

[0079] In some implementations, the state control circuit 44 may be a circuit for controlling the working state of the first switch device 412, the second switch device 422, and the third switch device 432, and the self-reference PUF device. The read-write control circuit 431 may be a circuit for controlling the write data state or the read data state of the read-write circuit.

[0080] Combined with the above description of the working process of the self-reference PUF device, it can be known that after power-on, the read-write circuit can enter the preparatory state of work. At this time, the state of the self-reference PUF device can be a state of pinning the magnetic domain wall to the pinning area. Accordingly, the first bit line 411 can be used to drive the first switch device 412 to input a low-level signal to the first MTJ, and the second bit line 421 can be used to drive the second switch device 422 to output a high-level signal to the bottom electrode of the second MTJ, and the state control line 44 can be used to input a high-level signal to the voltage control layer of the intermediate MTJ. Since this is the preparatory state of work, rather than the process of generating a key or reading data, the third switch device 432 can be driven by the read-write control line 431 to input a low level to the intermediate MTJ.

[0081] It should be understood that the above is only an illustrative description of the example of inputting a high level signal to the first MTJ terminal and inputting a low level signal to the second MTJ terminal. In another implementation, it can also be implemented as inputting a high level signal to the second MTJ terminal and inputting a low level signal to the first MTJ terminal. This will not be repeated here.

[0082] Furthermore, in the preparation state, the first bit line 411 , the second bit line 421 and the read / write control line 431 can be coordinated to control the read / write circuit to generate a key or read data.

[0083] In some embodiments, if the first switch device 412 is driven by the first bit line 411 to input a high level signal to the first MTJ, the second switch device 422 is driven by the second bit line 421 to input a low level signal to the second MTJ, and the third switch device 432 is driven by the read-write control line 431 to input a low level signal to the intermediate MTJ, then the self-reference PUF device can be driven to generate a key, and at this time, the read-write circuit can be in a data writing state. The implementation process of the self-reference PUF device generating a key, and the magnetic domain wall relaxation process involved in the key generation process, refer to the description of the above embodiment, and will not be repeated here.

[0084] In other embodiments, if the first switching device 412 is driven by the first bit line 411 to input a high level signal to the first MTJ, the second switching device 422 is driven by the second bit line 421 to input a high level signal to the second MTJ, and the third switching device 432 is driven by the read-write control line 431 to input a high level signal to the middle MTJ, the read-write circuit is in a data reading state.

[0085] The drive levels of the read / write circuits entering various working states may be shown in Table 1, for example:

[0086] Table 1

[0087] line Ready state Key generation level Reading level First line 411 0 1 1 The second bit line 421 1 0 1 Status control circuit 44 1 1 1 Read and write control circuit 431 0 0 1

[0088] Exemplarily, the first switch device 412, the second switch device 422 and the third switch device 432 may be implemented as transistors. Since the two-terminal MTJs of the self-referenced PUF device are used as read and write terminals, the read and write circuit described in the embodiment of the present disclosure may be called a 3T2M memristor unit.

[0089] It can be seen that due to the use of the 3T2M structure, the memristor unit of the embodiment of the present disclosure has a higher read margin, which is beneficial to reducing the misreading caused by the fluctuation of the spin process, thereby improving the reliability of reading and writing.

[0090] Figure 4 The read / write circuit shown can be a 3T2M memristor unit in a storage-computing integrated circuit. A 3T2M memristor unit stores 1 bit of data. If the data read and written by the storage-computing integrated circuit includes multiple bits, the storage-computing integrated circuit can be implemented as a read / write circuit array.

[0091] See also Figure 5 , Figure 5 FIG. 1 shows a schematic diagram of the structure of a read / write circuit array provided by an embodiment of the present disclosure. The read / write circuit array provided by the embodiment of the present disclosure may include a preset number of read / write circuits 50, a control circuit 51 and a pre-charge sense amplifier (PCSA) 52. Any read / write circuit may be as follows: Figure 4 The exemplary embodiments are described.

[0092] The specific value of the preset number can be determined according to the number of bits of data processed by the read / write circuit array. For example, if the data processed by the read / write circuit array is 64 bits, then the preset number can be 64, that is, the read / write circuit array can include 64 3T2M memristor units. The embodiments of the present disclosure are not limited to this.

[0093] The control circuit 51 includes clamping circuits connected in parallel with the preset number of read-write circuits 50 , respectively, so as to control the working state of the corresponding read-write circuits through the output voltage of the clamping circuits.

[0094] Exemplarily, the control circuit 51 can be connected to the read-write control circuit through the state control circuit of the read-write circuit, and the clamp circuit of the control circuit 51 can be connected to the first bit line and the second bit line of the read-write circuit. access) selects a read / write circuit from a preset number of read / write circuits 50, and then outputs a clamping voltage (V clamp ) to output pulses to the read / write circuit to drive the read / write circuit to generate a key or read data.

[0095] See also Figure 5 The enlarged view of the pre-charge amplifier 52 in FIG. 5 , the pre-charge amplifier 52 may include an amplifier circuit, and a first voltage detection circuit and a second voltage detection circuit connected in parallel with the amplifier circuit; the first voltage detection circuit is connected in parallel with the first MTJ of the preset number of read-write circuits; the second voltage detection circuit is connected in parallel with the second MTJ of the preset number of read-write circuits. The control circuit controls the read-write circuit to enter the data reading state, reads the voltage of the first MTJ in the read-write circuit through the first voltage detection circuit, reads the voltage of the second MTJ in the read-write circuit through the second voltage detection circuit, amplifies the difference between the voltage read by the first voltage detection circuit and the voltage read by the second voltage detection circuit, and outputs the read data according to the amplified difference.

[0096] The first voltage detection circuit and the second voltage detection circuit can be implemented as transistors, for example. Figure 5 The transistor T x and transistor T y .

[0097] It should be noted that the precharge amplifier 52 is used to amplify the data read from the read / write circuit when the read / write circuit is in the data reading state. Exemplarily, for any read / write circuit, the precharge amplifier 52 can charge to the V dd When the read / write circuit is driven to the data read state, the precharge amplifier 52 receives the read enable signal (i.e., the CLK signal) of the read / write circuit and increases the voltage V on the first MTJ side of the read / write circuit to L Set to the gate voltage of transistor Tx, and set the voltage V on the second MTJ side of the read / write circuit to R Set to transistor T y The gate voltage controls the discharge speed of the amplifier branch, which has an impact on V L and V R Differential amplification produces complementary output results. out Output high voltage level, so that the first MTJ can store data bit "1"; V out Outputting a low voltage level facilitates the first MTJ to store a data bit "0", thereby realizing a key reading operation of the memristor unit in the circuit.

[0098] refer to Figure 6 , in use Figure 5In the process of the read-write circuit array, in the data writing stage, the difference between the initial data and the key binary strings of equal length can be obtained by XOR Boolean logic operation to calculate the Hamming distance (HD) between the two, thereby generating the encrypted data bit of the data bit, thereby obtaining the encrypted data of the initial data. In the decryption stage, the key can be generated by driving each read-write circuit in the read-write circuit array, and then the encrypted data and the key are decrypted by inverse operation to obtain the initial data.

[0099] In order to verify the performance of the 3T2M device of the embodiment of the present disclosure, the 2T1M device is used as a comparison. In a simulation example, reference Figure 7 As shown in (a) and (b) in the figure, for example, at 300ps in the circuit, a level signal is input to the state control line WL of the two circuits, and the V L and V R The output read voltage is as follows Figure 7 As shown in (a), the V L and V R The output read voltage is as follows Figure 7 For example, when the enable pulse is turned on at 500ps on PCSA, the V L and V R The differential is amplified and the data stored in the device is output.

[0100] according to Figure 7 From the comparison between (a) and (b), it can be seen that when the circuit reaches a steady state, the reading margins of the 2T1M device are 26% and 29.8% respectively, while the margins of the 3T2M device are 132.6% and 67.2% respectively. The reading margin of the 3T2M device is much higher than that of the 2T1M device. It can be seen that the 3T2M device has a higher reading accuracy when facing process fluctuations or external interference.

[0101] To further verify the tolerance of the 3T2M device and the reference generator circuit in handling fluctuations, in the above simulation of the present disclosure, a change of σ = 5% was added to the transistor to obtain the V L and V R The corresponding output results are as follows Figure 7 As shown in (c), the V L and V R The corresponding output results are as follows Figure 7 As shown in (d) in the figure, it can be seen that whether it is reading "1" or reading "0", under the higher reading margin of the 3T2M device, V L and V RThe voltage values ​​of the voltages do not overlap in the process fluctuations. It can be seen that the technical solution disclosed in the present invention can effectively avoid misreading during reading.

[0102] In summary, the PUF device proposed in the embodiment of the present disclosure includes: an intermediate magnetic tunnel junction MTJ, and a first MTJ and a second MTJ located on both sides of the intermediate MTJ, respectively. Among them, the first MTJ, the intermediate MTJ and the second MTJ use the same free layer, and the width of the free layer gradually decreases from the part located in the intermediate MTJ to the parts of the first MTJ and the second MTJ, respectively. In this way, a magnetic shape anisotropy gradient can be formed. A voltage-controlled layer is provided in the area above the free layer and located in the intermediate MTJ. Thus, the MTJs at both ends can be used as reading devices, and the magnetic domain wall can be fixed in the area of ​​the intermediate MTJ in the initial state. Then, by driving the magnetic domain wall to randomly relax to both sides based on anisotropy, after the magnetic domain wall is stabilized on one side of the MTJ, the MTJ forms a low-resistance state, and the corresponding MTJ on the other side is in a high-resistance state, thereby forming a self-reference structure of the device, and this mode can improve the reading margin of the device.

[0103] Although the optional embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0104] The specific implementation methods described above further illustrate the purpose, technical solutions and beneficial effects of the present disclosure. It should be understood that the above description is only the specific implementation method of the present disclosure and is not intended to limit the protection scope of the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made on the basis of the technical solutions of the present disclosure should be included in the protection scope of the present invention.

Claims

1. A self-referenced physical unclonable function PUF device, characterized in that: The PUF device comprises: an intermediate magnetic tunnel junction MTJ, and a first MTJ and a second MTJ respectively located on both sides of the intermediate MTJ; There are gaps between the first MTJ and the second MTJ and the middle MTJ respectively, the first MTJ, the middle MTJ and the second MTJ use the same free layer, and the width of the free layer is gradually reduced from a portion located in the middle MTJ to portions of the first MTJ and the second MTJ respectively, so as to form a magnetic anisotropy gradient; A voltage control layer is disposed on the free layer and in a region located at the middle MTJ.

2. The self-reference PUF device according to claim 1, characterized in that: In an initial state, the first MTJ receives an input current, and a single magnetic domain wall is formed in the first MTJ.

3. The self-reference PUF device according to claim 2, characterized in that: When the voltage control layer applies a voltage to the middle MTJ, the magnetic domain wall is pinned to a pinning region in the middle MTJ corresponding to the voltage control layer, so that the PUF device enters a state where a key can be generated.

4. The self-reference PUF device according to claim 3, characterized in that After the voltage-controlled layer stops applying voltage to the middle MTJ, the magnetic domain wall relaxes to the first MTJ or the second MTJ driven by the magnetic anisotropy gradient, and stabilizes in the region with the smallest width in the first MTJ or the region with the smallest width in the second MTJ.

5. The self-reference PUF device according to claim 4, characterized in that: In the initial state, the magnetic moment directions of the region of the free layer corresponding to the first MTJ and the region corresponding to the second MTJ are both spin-down; If the magnetic domain wall is stable in the region where the width of the first MTJ is the smallest, the magnetic moment direction of the free layer in the region where the magnetic domain wall of the first MTJ is stable rotates to spin-up, so that the resistance of the first MTJ is smaller than the resistance of the second MTJ; If the magnetic domain wall is stable in the area where the width of the second MTJ is the smallest, the magnetic moment direction of the free layer in the area where the magnetic domain wall of the second MTJ is stable rotates to spin-up, so that the resistance of the second MTJ is smaller than the resistance of the first MTJ.

6. The self-referencing PUF device according to any one of claims 1 to 5, characterized in that: The material of the pressure control layer is a composite oxide.

7. A read-write circuit, characterized in that: The read / write circuit comprises a first drive circuit, a second drive circuit, a third drive circuit and a self-reference PUF device, wherein the self-reference PUF device is as described in any one of claims 1 to 6; The first driving circuit is connected to the first MTJ and is used to input a level signal to the first MTJ; The second driving circuit is connected to the second MTJ and is used to input a level signal to the second MTJ; The third driving circuit is connected to the middle MTJ and is used to input a level signal to the middle MTJ.

8. The read-write circuit according to claim 7, characterized in that: Also included is a state control circuit, the state control circuit being connected to the voltage control layer of the intermediate MTJ; The first driving circuit includes a first bit line and a first switch device; the second driving circuit includes a second bit line and a second switch device; the third driving circuit includes a read-write control circuit and a third switch device; The source of the first switch device is connected to the first bit line, the gate of the first switch device is connected in parallel with the state control line, and the drain of the first switch device is connected to the bottom electrode of the first MTJ; A source of the second switch device is connected to the second bit line, a gate of the second switch device is connected to the state control line, and a drain of the second switch device is connected to the bottom electrode of the second MTJ; The drain of the third switch device is connected to the bottom electrode of the middle MTJ, and the gate of the third switch device is connected to the read-write control line.

9. The read-write circuit according to claim 8, characterized in that: In a state where a high level signal is input to the voltage control layer of the intermediate MTJ through the state control line, The first switch device is driven by the first bit line to input a high level signal to the first MTJ, the second switch device is driven by the second bit line to input a low level signal to the second MTJ, and the third switch device is driven by the read-write control line to input a low level signal to the intermediate MTJ, the self-reference PUF device generates a key, and the read-write circuit is in a data writing state; The first switching device is driven by the first bit line to input a high level signal to the first MTJ, the second switching device is driven by the second bit line to input a high level signal to the second MTJ, and the third switching device is driven by the read-write control line to input a high level signal to the intermediate MTJ, and the read-write circuit is in a data reading state.

10. A read-write circuit array, characterized in that: The read / write circuit array includes a preset number of read / write circuits, control circuits and pre-charge amplifiers, any read / write circuit being as described in any one of claims 7 to 9; The control circuit includes clamp circuits connected in parallel with the preset number of read-write circuits, respectively, so as to control the working state of the corresponding read-write circuits through the output voltage of the clamp circuits; The precharge amplifier includes an amplifier circuit, and a first voltage detection circuit and a second voltage detection circuit connected in parallel with the amplifier circuit; the first voltage detection circuit is connected in parallel with the first MTJ of the preset number of read-write circuits; the second voltage detection circuit is connected in parallel with the second MTJ of the preset number of read-write circuits; For the read-write circuit controlled by the control circuit to enter the data reading state, the voltage of the first MTJ in the read-write circuit is read by the first voltage detection circuit, the voltage of the second MTJ in the read-write circuit is read by the second voltage detection circuit, the difference between the voltage read by the first voltage detection circuit and the voltage read by the second voltage detection circuit is amplified, and the read data is output according to the amplified difference.

Images