Negative PSPI pattern manufacturing method adopting partition exposure

Abstract

The invention belongs to the technical field of semiconductor packaging, and particularly relates to a negative PSPI pattern manufacturing method adopting partition exposure, which comprises the following steps of: 1, pasting a chip on a metal carrier plate according to a drawing, and re-casting into a wafer with larger chip spacing; step 2, coating the surface of the reconstructed wafer with uniform negative PSPI; 3, aligning a chip area on the surface of the reconstructed wafer coated with the PSPI, and performing small-line-width pattern exposure; 4, aligning the surface of the reconstructed wafer coated with the PSPI with an EMC area, and performing high-energy exposure to meet the requirement of enhancing the adhesive force of the PSPI and the EMC; step 5, developing the reconstructed wafer to enable the exposed part of the negative PSPI to be reserved so as to obtain a required pattern; and step 6, oxygen-free and high-temperature treatment is carried out on the reconstructed wafer, so that the PSPI is solidified into PI with stable properties, a dielectric layer consistent with a design pattern is obtained, a pattern close to a negative PSPI limit line width can be manufactured in the use process, and the adhesive force of the PSPI and EMC in an EMC area in a packaging unit is not affected.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor packaging, in particular to a method for manufacturing a negative PSPI pattern by using partitioned exposure. Background Art

[0002] The multifunctionality and miniaturization of semiconductor chips have become a major trend, and the types and number of chips that need to be integrated and packaged together are also increasing. For example, applications such as PA / PMU / IoT often require chips with different functions (bare wafers or passive components) to be assembled together to achieve a single package with certain functions, thereby forming a package module or sub-module.

[0003] The widely used fan-out packaging is to rewire the plastic package composed of chips (including passive components and bare chips) that have been plastic-sealed together to achieve interconnection packaging between components. When multiple chips are interconnected in a packaging unit (such as system-level packaging, memory packaging, etc.), the contradiction between more interconnected circuits and limited chip area requires a smaller feature pattern size. At this time, the PSPI pattern production is required to have higher resolution and smaller line width under the premise of unchanged reliability.

[0004] Based on the above problems, we propose a new negative PSPI patterning method using partitioned exposure. Summary of the invention

[0005] The purpose of this section is to summarize some aspects of the embodiments of the present invention and briefly introduce some preferred embodiments. Some simplifications or omissions may be made in this section and the specification abstract and the invention title of this application to avoid blurring the purpose of this section, the specification abstract and the invention title, and such simplifications or omissions cannot be used to limit the scope of the present invention.

[0006] In view of the problems existing in the prior art, the present invention is proposed.

[0007] Therefore, the purpose of the present invention is to provide a method for producing a negative PSPI pattern using partitioned exposure, which can achieve the production of a pattern close to the negative PSPI limit line width during use without affecting the adhesion between the PSPI and the EMC in the EMC area within the packaging unit.

[0008] To solve the above technical problems, according to one aspect of the present invention, the present invention provides the following technical solutions:

[0009] A method for producing a negative PSPI pattern using partition exposure comprises the following steps:

[0010] Step 1: Stick the chip on the metal carrier according to the drawing and recast it into a wafer with a larger chip spacing;

[0011] Step 2: uniformly coating negative PSPI on the surface of the reconstructed wafer;

[0012] Step 3: Align the chip area on the surface of the reconstructed wafer coated with PSPI and perform small line width pattern exposure;

[0013] Step 4: Align the EMC area on the surface of the reconstructed wafer coated with PSPI and perform high-energy exposure to meet the requirement of enhancing the adhesion between PSPI and EMC;

[0014] Step 5: developing the reconstructed wafer so that the exposed portion of the negative PSPI is retained, thereby obtaining the desired pattern;

[0015] Step 6: The reconstructed wafer is subjected to oxygen-free and high-temperature treatment to solidify the PSPI into PI with stable properties, thereby obtaining a dielectric layer consistent with the designed pattern.

[0016] As a preferred solution of the method for making a negative PSPI pattern by partition exposure described in the present invention, one packaging unit is composed of one chip or multiple chips interconnected to form a system and package.

[0017] As a preferred solution of the negative PSPI pattern production method using partitioned exposure described in the present invention, the passive component includes one or more optional dummy tube cores, and the dummy tube core is composed of a material with an appropriate thermal expansion coefficient and volume size, which is used to adjust and improve the warpage of the package body caused by the mismatch of thermal expansion coefficients between the packaged components and the plastic packaging material.

[0018] Compared with the prior art, the present invention has the beneficial effects of being able to produce a pattern close to the negative PSPI limit line width without affecting the adhesion between the PSPI and the EMC in the EMC region within the packaging unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the present invention will be described in detail below in combination with the accompanying drawings and detailed embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor. Among them:

[0020] Figure 1 This is a schematic diagram of step 1 of the present invention;

[0021] Figure 2 This is a schematic diagram of step 2 of the present invention;

[0022] Figure 3 This is a schematic diagram of step three of the present invention;

[0023] Figure 4 This is a schematic diagram of step 4 of the present invention;

[0024] Figure 5 This is a schematic diagram of step five of the present invention;

[0025] Figure 6 This is a schematic diagram of step six of the present invention. DETAILED DESCRIPTION

[0026] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0027] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0028] Secondly, the present invention is described in detail with reference to schematic diagrams. When describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0029] In order to make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0030] The present invention provides the following technical solutions: a method for producing a negative PSPI pattern using partitioned exposure, which can produce a pattern close to the negative PSPI limit line width during use, and does not affect the adhesion between the PSPI and the EMC in the EMC area of ​​the packaging unit;

[0031] Example 1

[0032] A method for producing a negative PSPI pattern using partition exposure comprises the following steps:

[0033] Step 1: According to the drawing, attach the chip to the metal carrier and recast it into a wafer with a larger chip spacing. Figure 1 shown.

[0034] Step 2: Apply a uniform negative PSPI coating on the surface of the reconstructed wafer. Figure 2 shown.

[0035] Step 3: Align the chip area on the surface of the reconstructed wafer coated with PSPI and perform small line width pattern exposure. Figure 3shown.

[0036] Step 4: Align the EMC area on the reconstructed wafer surface coated with PSPI and perform high-energy exposure to achieve the requirement of enhancing the adhesion between PSPI and EMC. Figure 4 shown.

[0037] Step 5: Develop the reconstructed wafer so that the exposed portion of the negative PSPI is retained, thereby obtaining the desired pattern. Figure 5 shown.

[0038] Step 6: The reconstructed wafer is subjected to oxygen-free and high-temperature treatment to solidify the PSPI into a stable PI, thereby obtaining a dielectric layer consistent with the design pattern; Figure 6 shown.

[0039] Furthermore, a package unit may consist of one chip or multiple chips interconnected to form a system and package. Passive components may include one or more optional dummy die, which are made of materials with appropriate thermal expansion coefficients and volume sizes, and are only used to adjust and improve the warpage of the package body caused by the mismatch of thermal expansion coefficients between the packaged components and the plastic packaging materials.

[0040] Although the present invention has been described above with reference to the embodiments, various modifications may be made thereto and parts thereof may be replaced by equivalents without departing from the scope of the present invention. In particular, as long as there is no structural conflict, the various features in the embodiments disclosed in the present invention may be used in combination with each other in any manner, and the fact that these combinations are not exhaustively described in this specification is only for the sake of omitting space and saving resources. Therefore, the present invention is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A method for producing a negative PSPI pattern using zone exposure, characterized in that: The steps include: Step 1: Stick the chip on the metal carrier according to the drawing and recast it into a wafer with a larger chip spacing; Step 2: uniformly coating negative PSPI on the surface of the reconstructed wafer; Step 3: Align the chip area on the surface of the reconstructed wafer coated with PSPI and perform small line width pattern exposure; Step 4: Align the EMC area on the surface of the reconstructed wafer coated with PSPI and perform high-energy exposure to meet the requirement of enhancing the adhesion between PSPI and EMC; Step 5: The reconstructed wafer is developed so that the exposed portion of the negative PSPI is retained, thereby obtaining the desired pattern; Step 6: The reconstructed wafer is subjected to oxygen-free and high-temperature treatment to solidify the PSPI into PI with stable properties, thereby obtaining a dielectric layer consistent with the designed pattern.

2. The method for producing a negative PSPI pattern using zone exposure according to claim 1, characterized in that: A packaging unit consists of a chip or multiple chips interconnected to form a system and package.

3. The method for producing a negative PSPI pattern using zone exposure according to claim 1, characterized in that: The passive component includes one or more optional dummy dies, which are composed of materials with appropriate thermal expansion coefficients and volume sizes, and are used to adjust and improve the warpage of the package body caused by the mismatch in thermal expansion coefficients between the packaged components and the plastic packaging materials.

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