Three-dimensional ultra-large bandwidth packaging structure and preparation method thereof

Abstract

The invention discloses a three-dimensional ultra-large bandwidth packaging structure and a preparation method thereof, and provides a novel three-dimensional packaging chip structure, an embedded chip and an outer-layer chip can form a vertically interconnected three-dimensional packaging structure, and connection between the three-dimensional packaging chips and external interconnection are realized through copper bumps. A three-dimensional ultra-large bandwidth packaging structure with the shortest interconnection distance is prepared, and the interconnection bandwidth can reach a high-speed interconnection structure of a 1000G level.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor advanced packaging substrates, and in particular to a three-dimensional ultra-large bandwidth packaging structure and a preparation method thereof. Background Art

[0002] With the vigorous development of mobile computing, Internet of Things, big data and artificial intelligence, chip packaging technology is facing more stringent requirements. Among the existing packaging technologies, MCM multi-chip packaging technology mounts the chip on the packaging substrate by flipping it. The chip interconnects the signal input and output ports through the wiring in the substrate. In the vertical direction, secondary packaging is performed to form a package-on-package structure, and the upper and lower chips are interconnected, thus forming a three-dimensional packaging structure.

[0003] However, the packaging cost of MCM multi-chip packaging technology is relatively high. Since the interconnection of the first layer of chips is through the packaging substrate, and the rewiring interconnection of the packaging substrate is prepared through blind holes to prepare the signal interconnection of the upper and lower layers of the multi-layer wiring, the signal bandwidth capacity of the blind hole structure is upper limit 50G, which will cause insufficient chip interconnection bandwidth. At the same time, the distance between the chip and the chip signal connection is far, resulting in insertion loss of signal interconnection; in addition, during the packaging process, directly mounting the adhesive material on one side of the chip will result in poor stability, which will also cause the chip's heat dissipation performance. Summary of the invention

[0004] The main purpose of the present invention is to provide a three-dimensional ultra-large bandwidth packaging structure and a preparation method thereof.

[0005] The technical solution adopted by the present invention is: a three-dimensional ultra-large bandwidth packaging structure and a preparation method thereof, comprising the following steps:

[0006] Step 1: Select a separable copper foil as a temporary substrate, and design and manufacture a metal bump layer on the separable copper foil;

[0007] Step 2: designing and manufacturing a wiring circuit layer on the metal bump layer;

[0008] Step 3: Making copper pillars on the wiring circuit layer, wherein the height of the copper pillars is greater than or equal to 50 μm, and grooves required for embedding heterogeneous chips are formed between the copper pillars;

[0009] Step 4: mounting a heterogeneous chip in the groove, wherein the heterogeneous chip has copper bumps and an adhesive material is provided on the back of the heterogeneous chip;

[0010] Step 5: Fill the dielectric material and grind it to form the first layer of chip embedding mounting structure, and peel off the separable copper foil;

[0011] Step 6: After the inner layer wiring is completed, the outer layer chip is packaged in a flip-chip manner to form a three-dimensional ultra-large bandwidth packaging structure.

[0012] Furthermore, the seed layer of the wiring line layer is produced by magnetron sputtering, and the thickness of the seed layer is less than 1 μm.

[0013] Furthermore, the metal bump layer is one or more layers, the wiring line layer is one or more layers, and the peripheries of the metal bump layer and the wiring line layer are filled with dielectric material.

[0014] Furthermore, the copper column is manufactured by photolithography and electroplating processes.

[0015] Furthermore, the thickness of the separable copper foil is 3-5 μm; and the size of the outer chip is larger than that of the heterogeneous chip.

[0016] Furthermore, the dielectric material is one or more of epoxy resin, polyimide, polyethylene or polypropylene.

[0017] Furthermore, the dielectric material uses vacuum film pressing technology to achieve the pressing of the dielectric material without film flow.

[0018] Compared with the prior art, the present invention has the following beneficial effects:

[0019] The present invention adopts upper and lower heterogeneous chips to form a three-dimensional ultra-large bandwidth packaging structure. The upper and lower chips are directly interconnected through copper bumps and copper pillars, and the signal bandwidth is increased from 50G level to 1000G level; the distance between the upper and lower chips can be ignored, and a longer interconnection distance will cause signal loss; the chip at the bottom of the three-dimensional chip can be embedded to effectively dissipate the bottom heat; the production cost of the three-dimensional packaging structure is significantly lower than the original method, and it has more cost advantages. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic diagram of a process for preparing a three-dimensional ultra-large bandwidth packaging structure;

[0021] Figure 2-Figure 4 It is a schematic diagram of the structure of the metal bump layer and the wiring circuit layer;

[0022] Figure 5-Figure 8 Schematic diagram of the three-dimensional ultra-large bandwidth packaging structure. DETAILED DESCRIPTION

[0023] The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making a clearer and more definite definition of the protection scope of the present invention.

[0024] Example

[0025] The preparation method of a three-dimensional ultra-large bandwidth packaging structure includes the following steps: selecting a separable copper foil 1 as a temporary substrate, designing and manufacturing a metal bump layer 2 on the separable copper foil 1; designing and manufacturing a wiring line layer on the metal bump layer 2; manufacturing copper pillars 3 on the wiring line layer, wherein the height of the copper pillars 3 is greater than or equal to 50 μm, and grooves 4 required for embedding a heterogeneous chip 5 are formed between the copper pillars 3; mounting a heterogeneous chip 5 in the groove 4, wherein the heterogeneous chip 5 has copper bumps 51, and the back of the heterogeneous chip 5 has an adhesive material; filling a dielectric material 21 and grinding to form a first-layer chip embedding mounting structure, and peeling off the separable copper foil 1; after performing inner layer wiring, packaging an outer chip 6 in a flip-chip manner to form a three-dimensional ultra-large bandwidth packaging structure.

[0026] like Figure 2 As shown, a separable copper foil 1 is selected as a temporary substrate. The separable copper foil 1 includes a carrier layer 11, a peeling layer 12 and an ultra-thin copper foil layer 13, has good tensile strength and thermal stability, and is easy to peel off.

[0027] Figure 3 and Figure 4 In the process, a metal bump layer 2 is designed and manufactured on a separable copper foil 1, and the metal bump layer 2 is coated on the surface of the copper foil by an electroplating process to enhance the adhesion of the electroplated metal bump layer 2 and serve as an electron channel. A dielectric material is filled around the metal bump layer 2, and the dielectric material is selected from polypropylene, which has stable physical and chemical properties and can provide good insulation performance to prevent short circuits between circuits. The metal bump layer 2 is exposed on the surface of the dielectric material by a thinning process. The metal bump layer 2 can be one layer or multiple layers, and direct interconnection is achieved between the multiple layers. A wiring line layer is designed and manufactured on the metal bump layer 2;

[0028] The dielectric material is laminated without film flow through vacuum film pressing technology, thereby achieving consistent internal stress and warping-free multi-layer wiring.

[0029] like Figure 5-8 As shown, a copper pillar 3 is made on the wiring circuit layer, the height of the copper pillar 3 is greater than or equal to 50μm, and a groove 4 required for embedding a heterogeneous chip 5 is formed between the copper pillars 3, providing the required vertical space for embedding the heterogeneous chip 3; a heterogeneous chip 5 is mounted in the groove 4, the heterogeneous chip 5 has a copper bump 51, and there is an adhesive material on the back of the heterogeneous chip 5; the dielectric material 21 is filled and ground to form a first layer chip embedding mounting structure, and the separable copper foil 1 is peeled off; after the inner layer wiring is performed, the outer layer chip 6 is packaged in a flip-chip manner to form a three-dimensional ultra-large bandwidth packaging structure.

[0030] The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiment. Any equivalent modifications or changes made by ordinary technicians in this field based on the contents disclosed by the present invention should be included in the protection scope recorded in the claims.

Claims

1. A three-dimensional ultra-large bandwidth packaging structure and a preparation method thereof, characterized in that: The following steps are involved: Step 1: Select a separable copper foil (1) as a temporary substrate, and design and manufacture a metal bump layer (2) on the separable copper foil (1); Step 2: designing and manufacturing a wiring circuit layer on the metal bump layer (2); Step 3: Making copper pillars (3) on the wiring circuit layer, wherein the height of the copper pillars (3) is greater than or equal to 50 μm, and grooves (4) required for embedding the heterogeneous chip (5) are formed between the copper pillars (3); Step 4: mounting a heterogeneous chip (5) in the groove (4), wherein the heterogeneous chip (5) has copper bumps (51) and an adhesive material is provided on the back of the heterogeneous chip (5); Step 5: Filling the dielectric material (21) and grinding to form a first layer chip embedding mounting structure, and peeling off the separable copper foil (1); Step 6: After the inner layer wiring is completed, the outer layer chip (6) is packaged in a flip-chip manner to form a three-dimensional ultra-large bandwidth packaging structure.

2. A three-dimensional ultra-large bandwidth packaging structure and a method for preparing the same according to claim 1, characterized in that: The seed layer of the wiring line layer is produced by magnetron sputtering, and the thickness of the seed layer is less than 1 μm.

3. The three-dimensional ultra-large bandwidth packaging structure and the preparation method thereof according to claim 1, characterized in that: The metal bump layer (2) is one or more layers, the wiring line layer is one or more layers, and the peripheries of the metal bump layer (2) and the wiring line layer are filled with dielectric material (21).

4. The three-dimensional ultra-large bandwidth packaging structure and the preparation method thereof according to claim 1, characterized in that: The copper column (3) is manufactured through photolithography and electroplating processes.

5. The three-dimensional ultra-large bandwidth packaging structure and the preparation method thereof according to claim 1, characterized in that: The thickness of the separable copper foil (1) is 3-5 μm; the size of the outer chip (6) is larger than that of the heterogeneous chip (5).

6. The three-dimensional ultra-large bandwidth packaging structure and the preparation method thereof according to claim 1, characterized in that: The dielectric material (21) is one or more of epoxy resin, polyimide, polyethylene or polypropylene.

7. A three-dimensional ultra-large bandwidth packaging structure and a method for preparing the same according to claim 6, characterized in that: The dielectric material (21) uses vacuum film pressing technology to achieve the pressing of dielectric materials without film flow.

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