Level conversion circuit and chip

Abstract

The invention discloses a level conversion circuit and a chip, and relates to the technical field of circuits. The level conversion circuit comprises a first switch, a second switch, a first step-down circuit, a second step-down circuit, a first boost circuit, a second boost circuit and a third boost circuit. A first control signal is configured to be a first voltage value or a second voltage value, and a second control signal is configured to be a third voltage value or a fourth voltage value to control the on or off of a first switch and a second switch, so that the functions of one-way level conversion, two-way level conversion and level conversion closing are realized; in practical application, the direction of level conversion can be flexibly adjusted, and the influence caused by signal connection of two ports between chips or inside the chips is avoided.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and in particular to a level conversion circuit and a chip. Background Art

[0002] In automotive domain controller products, communication signals between chips or within chips often have inconsistent power domains, and level conversion circuits are used at this time. There are often some communication pins that are multiplexed, such as a pin of the System on Chip (SOC) that is a mode configuration function during the initialization phase and should be used as an input; and a pin of the Universal Asynchronous Receiver / Transmitter (UART) output function during normal operation and should be used as an output; or a bidirectional communication function that is both an input and an output. At this time, in order to avoid the impact of conflicts in the input and output states of pins between different chips (affecting the function or even burning the pins), a circuit is needed to implement a level conversion function with controllable direction.

[0003] It can be seen that providing a direction-controllable level conversion circuit is a technical problem that needs to be solved urgently by people skilled in the art. Summary of the invention

[0004] The object of the present invention is to provide a level conversion circuit and a chip to solve the technical problem that the direction of level conversion cannot be controlled during level conversion.

[0005] To solve the above technical problems, the present invention provides a level conversion circuit, comprising: a first switch, a second switch, a first step-down circuit, a second step-down circuit, a first step-up circuit, a second step-up circuit and a third step-up circuit;

[0006] The first end of the first switch is used to receive a first control signal; the second end of the first switch is respectively connected to the first port, the output end of the first boost circuit and the input end of the first buck circuit; the third end of the first switch is respectively connected to the third end of the second switch, the output end of the first buck circuit and the output end of the second boost circuit;

[0007] The first end of the second switch is used to receive the second control signal; the second end of the second switch is respectively connected to the output end of the third boost circuit, the input end of the second buck circuit and the second port; the third end of the second switch is connected to the output end of the second buck circuit;

[0008] The first control signal is configured as a first voltage value or a second voltage value, and the second control signal is configured as a third voltage value or a fourth voltage value, and is used to control the opening or closing of the first switch and the second switch; wherein, the first voltage value is greater than a first level threshold of the power domain corresponding to the first control signal, the second voltage value is less than a second level threshold of the power domain corresponding to the first control signal, the third voltage value is greater than a third level threshold of the power domain corresponding to the second control signal, the fourth voltage value is less than a fourth level threshold of the power domain corresponding to the second control signal, the first level threshold is greater than the second level threshold, and the third level threshold is greater than the fourth level threshold.

[0009] Exemplarily, the supply voltage of the second boost circuit is the same as the supply voltage of the first boost circuit, and the supply voltage of the first boost circuit is greater than or equal to the supply voltage of the third boost circuit;

[0010] Or, the supply voltage of the second boost circuit is the same as the supply voltage of the third boost circuit, and the supply voltage of the first boost circuit is less than or equal to the supply voltage of the third boost circuit.

[0011] Exemplarily, the level conversion circuit is a bidirectional level conversion circuit, the first control signal is configured as the first voltage value, and the second control signal is configured as the third voltage value;

[0012] The level conversion circuit is a unidirectional level conversion circuit, the first port is an input port, the second port is an output port, the first control signal is configured as the first voltage value, and the second control signal is configured as the fourth voltage value;

[0013] Or, the level conversion circuit is a unidirectional level conversion circuit, and the second port is an input end, the first port is an output end, the first control signal is configured as the second voltage value, and the second control signal is configured as the third voltage value;

[0014] The level conversion circuit turns off the level conversion function, the first control signal is configured as the second voltage value, the second control signal is configured as the fourth voltage value, and the first switch and the second switch are both in a closed state.

[0015] Exemplarily, it also includes a first current limiting circuit and a second current limiting circuit;

[0016] The input end of the first current limiting circuit is used to receive the first control signal; the output end of the first current limiting circuit is connected to the first end of the first switch;

[0017] The input end of the second current limiting circuit is used to receive the second control signal; the output end of the second current limiting circuit is connected to the first end of the second switch.

[0018] Exemplarily, the first current limiting circuit includes a first resistor, and the second current limiting circuit includes a second resistor;

[0019] The first end of the first resistor is used to receive the first control signal;

[0020] The second end of the first resistor is connected to the first end of the first switch;

[0021] The first end of the second resistor is used to receive the second control signal;

[0022] The second end of the second resistor is connected to the first end of the second switch.

[0023] Exemplarily, the first switch is a first N-type MOS transistor, and the second switch is a second N-type MOS transistor;

[0024] The first end of the first switch is the gate of the first N-type MOS transistor; the second end of the first switch is the source of the first N-type MOS transistor; the third end of the first switch is the drain of the first N-type MOS transistor;

[0025] The first end of the second switch is the gate of the second N-type MOS transistor; the second end of the second switch is the source of the second N-type MOS transistor; and the third end of the first switch is the drain of the second N-type MOS transistor.

[0026] Exemplarily, the first step-down circuit includes a first diode, and the second step-down circuit includes a second diode;

[0027] The input end of the first step-down circuit is the anode of the first diode, and the output end of the first step-down circuit is the cathode of the first diode;

[0028] The input end of the second step-down circuit is the anode of the second diode, and the output end of the second step-down circuit is the cathode of the second diode.

[0029] Exemplarily, the first boost circuit, the second boost circuit and the third boost circuit all include a pull-up resistor.

[0030] Exemplarily, the first port and the second port are ports on the same chip or ports on different chips.

[0031] In order to solve the above technical problem, the present invention further provides a level conversion chip, comprising the above level conversion circuit.

[0032] In the level conversion circuit provided by the present invention, which includes a first switch, a second switch, a first step-down circuit, a second step-down circuit, a first step-up circuit, a second step-up circuit and a third step-up circuit, the first control signal is configured as a first voltage value or a second voltage value, and the second control signal is configured as a third voltage value or a fourth voltage value to control the opening or closing of the first switch and the second switch, so that the direction of the level conversion can be controlled during the level conversion.

[0033] Specifically, first, when the first control signal is configured as a first voltage value (because the first voltage value is greater than the first level threshold of the power domain corresponding to the first control signal, that is, the first control signal is configured as a high level), when the second control signal is configured as a third voltage value (because the third voltage value is greater than the third level threshold of the power domain corresponding to the second control signal, that is, the third control signal is configured as a high level), if the first port is an input port at this time and a high level is input, the first switch is closed, and under the action of the third boost circuit, the second switch is also in a closed state. At the same time, under the action of the third boost circuit, the second port outputs a high level; if the first port inputs a low level, the first switch is turned on, and under the action of the second step-down circuit, the second switch is also in a turned-on state. At this time, the second port outputs a low level; similarly, the level conversion principle when the second port is used as an input port and the first port is used as an output port is the same as the principle when the first port is used as an input port and the second port is used as an output port, thereby realizing the function of bidirectional level conversion;

[0034] Secondly, when one of the first control signal and the second control signal is configured as a high level and the other is configured as a low level, when the port corresponding to the control signal configured as a low level (such as the first control signal corresponding to the first port and the second control signal corresponding to the second port) is used as the input end, no matter whether the input is a high level or a high level, the second switch cannot be turned on, resulting in the level of the port corresponding to the control signal configured as a high level always being a high level, that is, the level conversion cannot be performed from the port corresponding to the control signal configured as a low level to the port corresponding to the control signal configured as a high level. When the port corresponding to the control signal configured as a high level is used as the input end and a high level is input, the port corresponding to the control signal configured as a low level outputs a high level; when the port corresponding to the control signal configured as a high level is input with a low level, the port corresponding to the control signal configured as a low level outputs a low level. It can be seen that the circuit can realize the level conversion from the port corresponding to the control signal configured as a high level to the port corresponding to the control signal configured as a low level, but cannot realize the level conversion from the port corresponding to the control signal configured as a low level to the port corresponding to the control signal configured as a high level, thereby realizing the function of unidirectional level conversion;

[0035] Again, when the first control signal and the second control signal are both configured as low levels, the first switch and the second switch are both in the disconnected state, thereby achieving the function of closing the level conversion.

[0036] It can be seen that the level conversion circuit provided by the present invention can realize a unidirectional level conversion function and a bidirectional level conversion function, and can also turn off the level conversion function, that is, realize a direction-controllable level conversion function.

[0037] In addition, the present invention also provides a level conversion chip, including the above-mentioned level conversion circuit, and has the same effect as above. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0039] Figure 1 A schematic diagram of a level conversion circuit provided by an embodiment of the present invention;

[0040] Figure 2 A circuit diagram capable of realizing a direction-controllable level conversion function is provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0041] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0042] The core of the present invention is to provide a level conversion circuit and a chip to solve the technical problem that the direction of level conversion cannot be controlled during level conversion.

[0043] In order to enable those skilled in the art to better understand the solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. Figure 1 A schematic diagram of a level conversion circuit provided by an embodiment of the present invention is shown in FIG. Figure 1 As shown, the level conversion circuit includes: a first switch, a second switch, a first step-down circuit, a second step-down circuit, a first step-up circuit, a second step-up circuit and a third step-up circuit;

[0044] The first end of the first switch is used to receive the first control signal; the second end of the first switch is respectively connected to the first port, the output end of the first boost circuit and the input end of the first buck circuit; the third end of the first switch is respectively connected to the third end of the second switch, the output end of the first buck circuit and the output end of the second boost circuit;

[0045] The first end of the second switch is used to receive the second control signal; the second end of the second switch is respectively connected to the output end of the third boost circuit, the input end of the second buck circuit and the second port; the third end of the second switch is connected to the output end of the second buck circuit.

[0046] The first port and the second port are ports on the same chip or ports on different chips. The level conversion circuit realizes a direction-controllable level conversion function between the first port and the second port. There is no limitation on the first switch and the second switch, such as being realized by a metal-oxide-semiconductor field-effect transistor (Metal-Oxide-SemiconductorField-Effect Transistor), referred to as MOSFET (MOS Field-Effect Transistor), or by a triode. There is no limitation on the first buck circuit and the second buck circuit, as long as they can play the role of bucking. There is no limitation on the first boost circuit, the second boost circuit and the third boost circuit, as long as they can play the role of boosting.

[0047] The power domain corresponding to the first control signal is the power domain corresponding to the first boost circuit; the power domain corresponding to the second control signal is the power domain corresponding to the first boost circuit or the power domain corresponding to the third boost circuit. When the first control signal is configured as the first voltage value, since the first voltage value is greater than the first level threshold of the power domain corresponding to the first control signal (the first level threshold is greater than the second level threshold), the first control signal is configured as the first voltage value, which can be considered as the first control signal configured as a high level; when the first control signal is configured as the second voltage value, since the second voltage value is less than the second level threshold of the power domain corresponding to the first control signal, the first control signal is configured as the second voltage value, which can be considered as the first control signal configured as a low level. When the second control signal is configured as the third voltage value, since the third voltage value is greater than the third level threshold of the power domain corresponding to the second control signal (the third level threshold is greater than the fourth level threshold), the second control signal is configured as the third voltage value, which can be considered as the second control signal configured as a high level; when the second control signal is configured as the fourth voltage value, since the fourth voltage value is less than the fourth level threshold of the power domain corresponding to the second control signal, the second control signal is configured as the fourth voltage value, which can be considered as the second control signal configured as a low level. In practice, the corresponding level threshold is determined according to the voltage value corresponding to the power domain.

[0048] The first control signal is configured as a first voltage value or a second voltage value, and the second control signal is configured as a third voltage value or a fourth voltage value, and is used to control the opening or closing of the first switch and the second switch. It is worth noting that the first control signal is configured as the first voltage value or the second voltage value, and the second control signal is configured as the third voltage value or the fourth voltage value, depending on the specific functions implemented by the circuit, including a unidirectional level conversion function (such as converting 3.3V of the first port to 5.0V that can be received by the second port, but not converting 5.0V of the second port to 3.3V that can be received by the first port; or converting 5.0V of the second port to 3.3V that can be received by the first port, but not converting 3.3V of the first port to 5.0V that can be received by the second port), a bidirectional level conversion function (such as being able to convert 3.3V of the first port to 5.0V that can be received by the second port, and converting 5.0V of the second port to 3.3V that can be received by the first port) and a closed level conversion function (neither converting 3.3V of the first port to 5.0V that can be received by the second port, nor converting 5.0V of the second port to 3.3V that can be received by the first port).

[0049] There is no limitation on the supply voltage of the second boost circuit located between the first switch and the second switch. Specifically, the supply voltage of the second boost circuit is the same as the supply voltage of the first boost circuit, and at this time, the supply voltage of the first boost circuit is greater than or equal to the supply voltage of the third boost circuit;

[0050] Or, the supply voltage of the second boost circuit is the same as the supply voltage of the third boost circuit. In this case, the supply voltage of the first boost circuit is less than or equal to the supply voltage of the third boost circuit.

[0051] When the level conversion circuit is used to implement a direction-controllable level conversion function, the first control signal and the second control signal are configured as follows:

[0052] When the level conversion circuit is a bidirectional level conversion circuit, the first control signal is configured as a first voltage value (i.e., a high level), and the second control signal is configured as a third voltage value (i.e., a high level);

[0053] The level conversion circuit is a unidirectional level conversion circuit, and the first port is an input port, the second port is an output port, the first control signal is configured as a first voltage value (i.e., a high level), and the second control signal is configured as a fourth voltage value (i.e., a low level);

[0054] Or, the level conversion circuit is a unidirectional level conversion circuit, and the second port is an input terminal, the first port is an output terminal, the first control signal is configured as a second voltage value (i.e., a low level), and the second control signal is configured as a third voltage value (i.e., a high level);

[0055] The level conversion circuit turns off the level conversion function, the first control signal is configured as the second voltage value (ie, low level), the second control signal is configured as the fourth voltage value (ie, low level), and the first switch and the second switch are both in the off state.

[0056] In addition, in order to protect the first switch and the second switch, a first current limiting circuit and a second current limiting circuit are further provided in the level conversion circuit.

[0057] The input end of the first current limiting circuit is used to receive the first control signal; the output end of the first current limiting circuit is connected to the first end of the first switch;

[0058] The input end of the second current limiting circuit is used to receive the second control signal; the output end of the second current limiting circuit is connected to the first end of the second switch.

[0059] Specifically, the first current limiting circuit includes a first resistor, and the second current limiting circuit includes a second resistor;

[0060] The first end of the first resistor is used to receive a first control signal;

[0061] The second end of the first resistor is connected to the first end of the first switch;

[0062] The first end of the second resistor is used to receive a second control signal;

[0063] The second end of the second resistor is connected to the first end of the second switch.

[0064] In some embodiments, the first switch is a first N-type MOS transistor, and the second switch is a second N-type MOS transistor;

[0065] The first end of the first switch is the gate of the first N-type MOS transistor; the second end of the first switch is the source of the first N-type MOS transistor; the third end of the first switch is the drain of the first N-type MOS transistor;

[0066] The first end of the second switch is the gate of the second N-type MOS transistor; the second end of the second switch is the source of the second N-type MOS transistor; and the third end of the first switch is the drain of the second N-type MOS transistor.

[0067] In some embodiments, the first buck circuit includes a first diode, and the second buck circuit includes a second diode;

[0068] The input end of the first step-down circuit is the anode of the first diode, and the output end of the first step-down circuit is the cathode of the first diode;

[0069] The input end of the second step-down circuit is the anode of the second diode, and the output end of the second step-down circuit is the cathode of the second diode.

[0070] The first boost circuit, the second boost circuit and the third boost circuit all include a pull-up resistor.

[0071] In order to enable those skilled in the art to better understand the solution of the present invention, the structure and working principle of the level conversion circuit capable of realizing controllable direction provided by the present invention are described below by taking the first switch and the second switch both being N-type MOS tubes as an example.

[0072] Figure 2 A circuit diagram for realizing a direction-controllable level conversion function provided by an embodiment of the present invention. Figure 2 As shown, the first port is A PORT port, the second port is B PORT port, and the level conversion of A PORT port and B PORT port is controlled by the circuit. The first switch Q1 and the second switch Q2 are both N-type MOS tubes, the first buck circuit is a first parasitic diode D1 connected in parallel with the first switch Q1, the second buck circuit is a second parasitic diode D2 connected in parallel with the second switch Q2, the first boost circuit includes a third resistor R3, the second boost circuit includes a fourth resistor R4, the third boost circuit includes a fifth resistor R5, the first control signal is GPIO1, the second control signal is GPIO2, the first current limiting circuit includes a first resistor R1, and the second current limiting circuit includes a second resistor R2.

[0073] Specifically, 1. A PORT and B PORT are two pins on different chips or the same chip, and can be in input, output or bidirectional transmission mode.

[0074] 2.VCCA is the power domain corresponding to the A PORT signal, VCCB is the power domain corresponding to the B PORT signal, and VCCA≤VCCB must be satisfied.

[0075] 3. The third resistor R3 and the fifth resistor R5 are pull-up resistors corresponding to the PORT, and are used to maintain the default level.

[0076] 4. The fourth resistor R4 is a pull-up resistor, which is used to maintain the default network level between the two MOS tubes.

[0077] 5. GPIO1 and GPIO2 are used to control the on / off of the first switch Q1 and the second switch Q2 respectively. The power domain of GPIO1 is VCCA, and the power domain of GPIO2 can be VCCA or VCCB.

[0078] 6. The first resistor R1 and the second resistor R2 are both current limiting resistors, which limit the current flowing from GPIO to the gate (G) of the MOS tube.

[0079] 7. Both the first switch Q1 and the second switch Q2 are N-channel MOS tubes, which are divided into three poles: gate (G), source (S), and drain (D). The voltage difference between the G pole and the S pole can control the conduction between the S pole and the D pole. The voltage difference between the G pole and the S pole is represented by VGS. When VGS exceeds the threshold voltage, the S pole and the D pole are connected; when VGS is lower than the threshold voltage, the S pole and the D pole are closed.

[0080] In addition, there is a parasitic diode between the S pole and the D pole, with the direction being from the S pole to the D pole.

[0081] The VGS threshold of the first switch Q1 and the VGS threshold of the second switch Q2 must both be smaller than VCCA / VCCB.

[0082] use Figure 2 The principle of realizing the direction-controlled level conversion function in the circuit diagram shown is as follows:

[0083] (1) Turn off level conversion: GPIO1 and GPIO2 are both low level. At this time, no matter whether A PORT / B PORT is high level or low level, the VGS voltage is less than or equal to 0, and the two MOS tubes are in the non-conducting state, that is, the connection between A PORT and B PORT is disconnected.

[0084] (2) Bidirectional level conversion: GPIO1 and GPIO2 are both high level. At this time, if A PORT inputs a high level, the VGS of the first switch Q1 = 0, and the S and D poles of the first switch Q1 are closed; B PORT is the output. Under the action of the fifth resistor R5 (pull-up resistor), the VGS of the second switch Q2 = 0, and the S and D poles of the second switch Q2 are closed. At this time, B PORT is only connected to the fifth resistor R5, so it outputs a high level.

[0085] If the input of PORT A is low level, the VGS of the first switch Q1 is equal to VCCA, which is greater than the threshold voltage, and the S pole and the D pole of the first switch Q1 are connected. The on-resistance is generally very low, and the voltage drop generated thereby can be ignored. Then the D pole of the second switch Q2 and the first switch Q1 are at a low level. Furthermore, due to the presence of the parasitic diode of the second switch Q2, the S pole of the second switch Q2 will also be pulled down to a low level, thereby making the VGS of the second switch Q2 equal to VCCB, which is greater than the threshold voltage, and the S pole and the D pole of the second switch Q2 are connected. Furthermore, PORT B ​​becomes a low level.

[0086] The principle of B PORT as input is similar to that of A PORT input, so it will not be repeated here. In this way, the bidirectional level conversion function can be realized.

[0087] (3) Unidirectional level conversion: If A PORT needs to transmit to B PORT and B PORT cannot transmit to A PORT, GPIO1 is high level and GPIO2 is low level; if B PORT needs to transmit to A PORT and A PORT cannot transmit to B PORT, GPIO1 is low level and GPIO2 is high level.

[0088] The principles of the two situations are similar. Here we take the case where A PORT needs to transmit to B PORT and B PORT cannot transmit to A PORT as an example:

[0089] At this time, A PORT is used as input. When the input is high level, since GPIO1 is high level, VGS is less than the threshold voltage, and the S pole and D pole of the first switch Q1 are disconnected. The same principle as described in Section (2) is used. At this time, the output of B PORT is high level.

[0090] When A PORT inputs a low level, VGS is greater than the threshold voltage, the S and D poles of the first switch Q1 are turned on, and the D pole of the second switch Q2 is at a low level. The same principle as described in Section (2) also pulls the S pole of the second switch Q2 down to a low level, that is, B PORT is at a low level.

[0091] If B PORT is used as input and GPIO2 is at a low level, the principle described in Section (1) applies. Regardless of whether B PORT inputs a high level or a low level, the VGS voltage of the second switch Q2 is less than or equal to 0, and the S and D poles of the second switch Q2 are disconnected. Furthermore, A PORT is always at a high level, that is, the B PORT level state cannot be transmitted to A PORT, thereby realizing a unidirectional level conversion function.

[0092] Table 1 shows the Figure 2 The control logic information of the circuit diagram shown.

[0093] Table 1

[0094]

[0095] In the level conversion circuit provided by the embodiment of the present invention, which includes a first switch, a second switch, a first step-down circuit, a second step-down circuit, a first step-up circuit, a second step-up circuit and a third step-up circuit, the first control signal is configured as a first voltage value or a second voltage value, and the second control signal is configured as a third voltage value or a fourth voltage value to control the opening or closing of the first switch and the second switch, so that the direction of the level conversion can be controlled during the level conversion, and the functions of unidirectional level conversion, bidirectional level conversion and level conversion shutdown are realized, so that the direction of the level conversion can be flexibly adjusted in actual application, avoiding the influence caused by the signal connection between two ports between chips or inside a chip.

[0096] A level conversion circuit is described above, and this embodiment further provides a level conversion chip. The level conversion chip provided in this embodiment includes the above-mentioned level conversion circuit. The embodiment of the level conversion circuit has been described in detail above, and the embodiment of the level conversion chip is not repeated here, and has the same beneficial effects as the above-mentioned level conversion circuit.

[0097] The above is a detailed introduction to a level conversion circuit and chip provided by the present invention. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referred to each other. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, the present invention can also be improved and modified, and these improvements and modifications also fall within the scope of protection of the present invention.

[0098] It should also be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

Claims

1. A level conversion circuit, characterized in that: include: A first switch, a second switch, a first step-down circuit, a second step-down circuit, a first step-up circuit, a second step-up circuit, and a third step-up circuit; The first end of the first switch is used to receive a first control signal; the second end of the first switch is respectively connected to the first port, the output end of the first boost circuit and the input end of the first buck circuit; the third end of the first switch is respectively connected to the third end of the second switch, the output end of the first buck circuit and the output end of the second boost circuit; The first end of the second switch is used to receive the second control signal; the second end of the second switch is respectively connected to the output end of the third boost circuit, the input end of the second buck circuit and the second port; the third end of the second switch is connected to the output end of the second buck circuit; The first control signal is configured as a first voltage value or a second voltage value, and the second control signal is configured as a third voltage value or a fourth voltage value, and is used to control the opening or closing of the first switch and the second switch; wherein, the first voltage value is greater than a first level threshold of the power domain corresponding to the first control signal, the second voltage value is less than a second level threshold of the power domain corresponding to the first control signal, the third voltage value is greater than a third level threshold of the power domain corresponding to the second control signal, the fourth voltage value is less than a fourth level threshold of the power domain corresponding to the second control signal, the first level threshold is greater than the second level threshold, and the third level threshold is greater than the fourth level threshold.

2. The level conversion circuit according to claim 1, characterized in that: The supply voltage of the second boost circuit is the same as the supply voltage of the first boost circuit, and the supply voltage of the first boost circuit is greater than or equal to the supply voltage of the third boost circuit; Or, the supply voltage of the second boost circuit is the same as the supply voltage of the third boost circuit, and the supply voltage of the first boost circuit is less than or equal to the supply voltage of the third boost circuit.

3. The level conversion circuit according to claim 1, characterized in that: The level conversion circuit is a bidirectional level conversion circuit, the first control signal is configured as the first voltage value, and the second control signal is configured as the third voltage value; The level conversion circuit is a unidirectional level conversion circuit, the first port is an input port, the second port is an output port, the first control signal is configured as the first voltage value, and the second control signal is configured as the fourth voltage value; Or, the level conversion circuit is a unidirectional level conversion circuit, and the second port is an input end, the first port is an output end, the first control signal is configured as the second voltage value, and the second control signal is configured as the third voltage value; The level conversion circuit turns off the level conversion function, the first control signal is configured as the second voltage value, the second control signal is configured as the fourth voltage value, and the first switch and the second switch are both in a closed state.

4. The level conversion circuit according to claim 1, characterized in that: Also includes a first current limiting circuit and a second current limiting circuit; The input end of the first current limiting circuit is used to receive the first control signal; the output end of the first current limiting circuit is connected to the first end of the first switch; The input end of the second current limiting circuit is used to receive the second control signal; the output end of the second current limiting circuit is connected to the first end of the second switch.

5. The level conversion circuit according to claim 4, characterized in that: The first current limiting circuit includes a first resistor, and the second current limiting circuit includes a second resistor; The first end of the first resistor is used to receive the first control signal; The second end of the first resistor is connected to the first end of the first switch; The first end of the second resistor is used to receive the second control signal; The second end of the second resistor is connected to the first end of the second switch.

6. The level conversion circuit according to any one of claims 1 to 5, characterized in that: The first switch is a first N-type MOS transistor, and the second switch is a second N-type MOS transistor; The first end of the first switch is the gate of the first N-type MOS transistor; the second end of the first switch is the source of the first N-type MOS transistor; the third end of the first switch is the drain of the first N-type MOS transistor; The first end of the second switch is the gate of the second N-type MOS transistor; the second end of the second switch is the source of the second N-type MOS transistor; and the third end of the first switch is the drain of the second N-type MOS transistor.

7. The level conversion circuit according to claim 6, characterized in that: The first step-down circuit includes a first diode, and the second step-down circuit includes a second diode; The input end of the first step-down circuit is the anode of the first diode, and the output end of the first step-down circuit is the cathode of the first diode; The input end of the second step-down circuit is the anode of the second diode, and the output end of the second step-down circuit is the cathode of the second diode.

8. The level conversion circuit according to claim 1, characterized in that: The first boost circuit, the second boost circuit and the third boost circuit all include pull-up resistors.

9. The level conversion circuit according to claim 1, characterized in that: The first port and the second port are ports on the same chip or ports on different chips.

10. A level conversion chip, characterized in that: A level conversion circuit comprising any one of claims 1 to 9.

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