Level switching circuit capable of automatically sensing direction

Abstract

The invention discloses an automatic direction induction level conversion circuit, which comprises a first voltage domain circuit and a second voltage domain circuit which have the same structure, and can automatically input an input signal A of the first voltage domain circuit to a second level conversion module through a first voltage domain circuit driving input module. A driving signal is output to a second voltage domain circuit to drive an output module to control weak driving and control a monostable circuit to generate corresponding strong driving at the same time, and a second signal B in the same phase is output; or similarly, the input signal B of the second voltage domain circuit is automatically converted into a first signal A with the same phase. According to the level conversion circuit, the transmission direction of the switching signal can be automatically sensed without an additional signal, bidirectional level conversion is realized, and the system structure is simplified; meanwhile, strong driving output is started in a short time through the monostable circuit, the output driving capacity and transmission speed are improved, strong driving output on the other side is closed through a feedback signal, and mistaken starting of the bidirectional level conversion circuit is avoided.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuits, and in particular to a level conversion circuit for automatic direction sensing. Background Art

[0002] In modern integrated circuit design, many different functions are often integrated on the same chip to form a complex system on chip (SoC). In order to achieve a good compromise between circuit performance and power consumption, multi-voltage technology is usually used to enable different functional modules to operate at different voltages to obtain optimal performance and power consumption. However, this multi-voltage design also brings new challenges, namely how to efficiently and reliably transmit information between two systems with different voltages.

[0003] In order to transfer information between two systems with different voltages, a corresponding level conversion circuit must be used to achieve data conversion between circuits with different supply voltages. The function of the level conversion circuit is to convert the signal level of one voltage domain to the signal level of another voltage domain while ensuring the integrity and timing requirements of the signal. Traditional level conversion circuits are mainly divided into two types: unidirectional level conversion and bidirectional level conversion.

[0004] Unidirectional level conversion circuits can only realize signal transmission in a single direction and are usually used in scenarios where the data transmission direction is fixed. However, in practical applications, bidirectional data transmission is required between two voltage domains in many cases, which requires the use of bidirectional level conversion circuits. Existing bidirectional level conversion circuits usually adopt a direction detection mechanism based on control signals, that is, an additional control signal is used to indicate the direction of data transmission. However, this solution has the following problems: 1. Inaccurate transmission direction detection: Since the control signal may have delays or jitters, the direction detection is inaccurate, resulting in data transmission errors. 2. Weak driving capability: Traditional bidirectional level conversion circuits usually adopt a simple transmission gate structure with limited driving capability, which is difficult to meet the needs of high-speed data transmission. 3. High circuit complexity and power consumption: Additional control signals increase circuit complexity and power consumption, which is not conducive to low-power design.

[0005] In order to solve the above problems, researchers have proposed a variety of improvement schemes, such as direction detection circuits based on current detection, direction detection circuits based on delay-locked loops, etc. However, these schemes still have problems such as complex circuits, high power consumption, and slow speed, which are difficult to meet the requirements of modern integrated circuits for high performance and low power consumption.

[0006] Therefore, there is an urgent need for a new type of bidirectional level conversion circuit that can achieve automatic direction sensing, high driving capability, low power consumption and high-speed data transmission to meet the needs of modern integrated circuit design. Summary of the invention

[0007] The problem to be solved by the present invention is to provide an automatic direction-sensing level conversion circuit, which can automatically detect the data transmission direction and complete the level conversion without the need for additional control signals, realize accurate bidirectional level conversion, and have a higher transmission rate.

[0008] The present invention adopts the following technical solution: an automatic direction sensing level conversion circuit, comprising: a first voltage domain circuit, a second voltage domain circuit, a first level conversion module, and a second level conversion module; the first voltage domain circuit and the second voltage domain circuit have the same structure, both including a drive input module and a drive output module; the first voltage domain circuit is connected to a first signal terminal, the second voltage domain circuit is connected to a second signal terminal, and the first signal terminal and the second signal terminal are bidirectional ports.

[0009] The level conversion circuit inputs the first signal A input to the first signal terminal into the second level conversion module through the driving input module of the first voltage domain circuit, generates a driving signal C2 at the output terminal of the second level conversion module, inputs it to the driving output module of the second voltage domain circuit, controls the monostable circuit in the driving output module to generate a corresponding strong drive, and controls the weak drive at the same time, outputs a second signal B in phase with the first signal A to the second signal terminal; or inputs the second signal B input to the second signal terminal into the first level conversion module through the driving input module of the second voltage domain circuit, generates a driving signal D2 at the output terminal of the first level conversion module, inputs it to the driving output module of the first voltage domain circuit, controls the monostable circuit in the driving output module to generate a corresponding strong drive, and controls the weak drive at the same time, outputs the first signal A in phase with the second signal B to the first signal terminal.

[0010] Preferably, the driving input module of the first voltage domain circuit comprises: a first inverter INV1, a second inverter INV2, a first NAND gate NAND1, a second NAND gate NAND2, a first NOR gate NOR1, and a fourth rising edge monostable circuit; The first voltage domain voltage signal is C1, the first input end of the first NOR gate NOR1 is connected to the first signal end, the second input end inputs the first voltage domain voltage signal C1, the output end is connected to the input end of the second inverter INV2, and the output end of the second inverter INV2 outputs the driving signal C2 through the second level conversion module; The first voltage domain voltage signal C1 is also input to the first input terminal of the second NAND gate NAND2, the first signal terminal is connected to the second input terminal of the second NAND gate NAND2 through the fourth rising edge monostable circuit, and the output terminal of the second NAND gate NAND2 is connected to the second input terminal of the first NAND gate NAND1; The first input end of the first NAND gate NAND1 is connected to the output end of the first inverter INV1, the input end of the first inverter INV1 is connected to the drive signal D3 generated by the first voltage domain circuit drive output module, and the output end of the first NAND gate NAND1 is connected to the second input end of the first NOR gate NOR1 through the first voltage domain voltage signal C1.

[0011] Preferably, the driving output module of the first voltage domain circuit includes: a sixth inverter INV6, a first NMOS tube NM1, a second NMOS tube NM2, a first PMOS tube PM1, a second PMOS tube PM2, a first rising edge monostable circuit, and a first falling edge monostable circuit; The driving signal D2 is input into the gate of the first PMOS transistor PM1 through the first rising edge monostable circuit, and is simultaneously input into the gate of the first NMOS transistor NM1 through the first falling edge monostable circuit; the source of the first PMOS transistor PM1 is connected to the first power supply voltage VCC1, and the drain is connected to the drain of the first NMOS transistor NM1; the source of the first NMOS transistor NM1 is grounded; a strong drive is generated between the drain of the first PMOS transistor PM1 and the drain of the first NMOS transistor NM1, and is output to the first signal terminal; The drive signal D2 is also input to the input end of the sixth inverter INV6, and a drive signal D3 is generated at the output end of the sixth inverter INV6. The drive signal D3 is input to the drain of the second PMOS tube PM2 and the second NMOS tube NM2; the source of the second PMOS tube PM2 is connected to the first power supply voltage VCC1, and the drain is connected to the drain of the second NMOS tube NM2; the source of the second NMOS tube NM2 is grounded; a weak drive is generated between the drain of the second PMOS tube PM2 and the drain of the second NMOS tube NM2, and output to the first signal end.

[0012] Preferably, the driving input module of the second voltage domain circuit includes: a fourth inverter INV4, a fifth inverter INV5, a third NAND gate NAND3, a fourth NAND gate NAND4, a second NOR gate NOR2, and a third rising edge monostable circuit; The second voltage domain voltage signal is D1, the first input end of the second NOR gate NOR2 is connected to the second signal end, the second input end inputs the second voltage domain voltage signal D1, the output end is connected to the input end of the fifth inverter INV5, and the output end of the fifth inverter INV5 outputs the driving signal D2 through the first level conversion module; The second voltage domain voltage signal D1 is also input to the first input terminal of the third NAND gate NAND3, the second signal terminal is connected to the second input terminal of the third NAND gate NAND3 through the third rising edge monostable circuit, and the output terminal of the third NAND gate NAND3 is connected to the second input terminal of the fourth NAND gate NAND4; The first input end of the fourth NAND gate NAND4 is connected to the output end of the fourth inverter INV4, the input end of the fourth inverter INV4 is connected to the drive signal C3 generated by the second voltage domain circuit drive output module, and the output end of the fourth NAND gate NAND4 is connected to the second input end of the second NOR gate NOR2 through the second voltage domain voltage signal D1.

[0013] Preferably, the driving output module of the second voltage domain circuit includes: a third inverter INV3, a third NMOS tube NM3, a fourth NMOS tube NM4, a third PMOS tube PM3, a fourth PMOS tube PM4, a second rising edge monostable circuit, and a second falling edge monostable circuit; The driving signal C2 is input into the gate of the fourth PMOS transistor PM4 through the second rising edge monostable circuit, and is simultaneously input into the gate of the fourth NMOS transistor NM4 through the second falling edge monostable circuit; the source of the fourth PMOS transistor PM4 is connected to the second power supply voltage VCC2, and the drain is connected to the drain of the fourth NMOS transistor NM4; the source of the fourth NMOS transistor NM4 is grounded; a strong drive is generated between the drain of the fourth PMOS transistor PM4 and the drain of the fourth NMOS transistor NM4, and is output to the second signal terminal; The driving signal C2 is also input to the input end of the third inverter INV3, and the driving signal C3 is generated at the output end of the third inverter INV3. The driving signal C3 is input to the drains of the third PMOS tube PM3 and the third NMOS tube NM3; the source of the third PMOS tube PM3 is connected to the second power supply voltage VCC2, the drain is connected to the drain of the third NMOS tube NM3, and the source of the third NMOS tube NM3 is grounded; a weak drive is generated between the drain of the third PMOS tube PM3 and the drain of the third NMOS tube NM3, and output to the second signal end.

[0014] Preferably, when the first signal terminal is the input terminal and the second signal terminal is the output terminal, the first voltage domain voltage signal C1 is at a low level, and the input first signal A passes through the first NOR gate NOR1, the second inverter INV2, and the second level conversion module in sequence to generate a drive signal C2 which is input to the drive output module of the second voltage domain circuit, controls the second rising edge monostable circuit and the second falling edge monostable circuit to generate a strong drive, and controls the weak drive at the same time, and outputs a second signal B which is in phase with the first signal A; The driving signal C2 simultaneously generates a driving signal C3 through the third inverter INV3, which is fed back to the input end of the fourth inverter INV4, and generates a second voltage domain voltage signal D1 with a phase opposite to the second signal B through the fourth NAND gate NAND4, which is input to the second input end of the second NOR gate NOR2. The two input signals of the second NOR gate NOR2 have opposite phases and output a low level. After passing through the fifth inverter INV5 and the first level conversion module, the driving signal D2 is generated to be a high level. The strong drive in the first voltage domain circuit driving output module is not turned on and the driving signal D3 remains at a low level, which does not affect the input of the first signal A at the first signal end.

[0015] Preferably, when the second signal terminal is the input terminal and the first signal terminal is the output terminal, the second voltage domain voltage signal D1 is at a low level, and the input second signal B passes through the second NOR gate NOR2, the fifth inverter INV5, and the first level conversion module in sequence to generate a drive signal D2 which is input to the drive output module of the first voltage domain circuit, controls the first rising edge monostable circuit and the first falling edge monostable circuit to generate a strong drive, and controls the weak drive at the same time, and outputs a first signal A which is in phase with the second signal B; The driving signal D2 simultaneously generates a driving signal D3 through the sixth inverter INV2, which is fed back to the input end of the first inverter INV1, and generates a first voltage domain voltage signal C1 with a phase opposite to the first signal A through the first NAND gate NAND1, which is input to the second input end of the first NOR gate NOR1. The two input signals of the first NOR gate NOR1 are in opposite phases and output a low level. After passing through the second inverter INV2 and the second level conversion module, the driving signal C2 is generated to be a high level. The strong drive in the second voltage domain circuit driving output module is not turned on and the driving signal C3 remains at a low level, which does not affect the input of the second signal B at the second signal end.

[0016] Preferably, the first PMOS transistor PM1, the first NMOS transistor NM1, the third PMOS transistor PM3, and the third NMOS transistor NM3 are strong drive transistors; the second PMOS transistor PM2, the second NMOS transistor NM2, the fourth PMOS transistor PM4, and the fourth NMOS transistor NM4 are weak drive transistors.

[0017] Preferably, the first, second, third, and fourth rising edge monostable circuits and the first and second falling edge monostable circuits are all monostable circuits, and their working states include steady state and temporary steady state; the monostable circuit flips from steady state to temporary steady state through an external trigger pulse, and automatically returns to steady state after maintaining the temporary steady state for a period of time.

[0018] Preferably, the monostable circuit comprises an RC circuit composed of a resistor R and a MOS capacitor NM, and the maintenance time of the temporary stable state of the monostable circuit depends on the charging and discharging time of the RC circuit.

[0019] Compared with the prior art, the present invention adopts the above technical solution and has the following technical effects: 1. The level conversion circuit of the present invention can not only realize bidirectional level conversion, but also automatically perform direction sensing and switch the transmission direction of the signal without the need for additional signals to control the transmission direction, thus simplifying the system structure, reducing costs and power consumption, and improving data transmission speed.

[0020] 2. The level conversion circuit of the present invention turns on the strong drive output in a short time through the monostable circuit, thereby improving the output drive capability and transmission speed. At the same time, the strong drive output on the other side is turned off through the feedback signal, thereby avoiding the false start of the bidirectional level conversion circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a structural diagram of the level conversion circuit of the automatic direction sensing of the present invention; Figure 2 This is a structural diagram of a rising edge monostable circuit of the present invention; Figure 3 This is a structural diagram of a falling edge monostable circuit of the present invention; Figure 4 This is a timing waveform diagram of the level conversion of the present invention. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the application is further elaborated in detail below in conjunction with the accompanying drawings. The described embodiments are only a part of the embodiments involved in the present invention. All non-innovative embodiments of other researchers in the field on this embodiment belong to the protection scope of the present invention. At the same time, for the step numbering in the embodiment of the present invention, it is only set for the convenience of explanation, and the order between the steps is not limited in any way. The execution order of each step in the embodiment can be adaptively adjusted according to the understanding of those skilled in the art.

[0023] In one embodiment of the present invention, a level conversion circuit for automatic direction sensing, such as Figure 1 As shown, it includes: a first voltage domain circuit VCCA, a second voltage domain circuit VCCB, a first level conversion module, and a second level conversion module; The first voltage domain circuit VCCA and the second voltage domain circuit VCCB have the same structure, both including a driving input module and a driving output module; the first voltage domain circuit VCCA is connected to the first signal terminal, and the second voltage domain circuit VCCB is connected to the second signal terminal, the first signal terminal and the second signal terminal are bidirectional ports, and the first level conversion module and the second level conversion module adopt conventional circuits.

[0024] Specifically, in the first voltage domain circuit VCCA, the driving input module includes: a first inverter INV1, a second inverter INV2, a first NAND gate NAND1, a second NAND gate NAND2, a first NOR gate NOR1, and a fourth rising edge monostable circuit; the driving output module includes: a sixth inverter INV6, a first NMOS tube NM1, a second NMOS tube NM2, a first PMOS tube PM1, a second PMOS tube PM2, a first rising edge monostable circuit, and a first falling edge monostable circuit.

[0025] Specifically, in the second voltage domain circuit VCCB, the driving input module includes: a fourth inverter INV4, a fifth inverter INV5, a third NAND gate NAND3, a fourth NAND gate NAND4, a second NOR gate NOR2, and a third rising edge monostable circuit; the driving output module includes: a third inverter INV3, a third NMOS tube NM3, a fourth NMOS tube NM4, a third PMOS tube PM3, a fourth PMOS tube PM4, a second rising edge monostable circuit, and a second falling edge monostable circuit.

[0026] Among them, the first PMOS transistor PM1, the first NMOS transistor NM1, the third PMOS transistor PM3, and the third NMOS transistor NM3 are strong drive transistors; the second PMOS transistor PM2, the second NMOS transistor NM2, the fourth PMOS transistor PM4, and the fourth NMOS transistor NM4 are weak drive transistors.

[0027] The initial state voltage of the first voltage domain circuit VCCA is the first voltage domain voltage signal C1, and the initial state voltage of the second voltage domain circuit VCCB is the second voltage domain voltage signal D1. Figure 1 Among them, C2, C3, C4, C5, D2, D3, D4, and D5 are all internal driving signals.

[0028] When the first signal terminal is an input terminal and the second signal terminal is an output terminal, such as Figure 4 As shown, the first voltage domain voltage signal C1 is kept at a low level, and the input first signal A passes through the first NOR gate NOR1, the second inverter INV2 and the second level conversion module in sequence to generate a drive signal C2 which is input to the second voltage domain circuit VCCB; the drive output module of the second voltage domain circuit VCCB controls the second rising edge monostable circuit to generate a drive signal C4 which is input to the gate of the fourth PMOS tube PM4, and controls the second falling edge monostable circuit to generate a drive signal C5 which is input to the gate of the fourth NMOS tube NM4, so that a strong drive is generated between the drain of the fourth PMOS tube PM4 and the drain of the fourth NMOS tube NM4, and at the same time controls a weak drive to be generated between the drain of the third PMOS tube PM3 and the drain of the third NMOS tube NM3, and outputs a second signal B which is in phase with the first signal A.

[0029] At the same time, the driving signal C2 is input into the third inverter INV3 to generate the driving signal C3, and the driving signal C3 is fed back to the input end of the fourth inverter INV4, and the second voltage domain voltage signal D1 with a phase opposite to the second signal B is generated through the fourth NAND gate NAND4, and is input to the second input end of the second NOR gate NOR2, so that the two input signals of the second NOR gate NOR2 are in opposite phases, and the second NOR gate NOR2 maintains a low level output, and after passing through the fifth inverter INV5 and the first level conversion module, the driving signal D2 is generated to remain at a high level. Therefore, the strong drive in the driving output module of the first voltage domain circuit VCCA will not be turned on, and the bidirectional level conversion circuit can be prevented from being turned on by mistake. Moreover, the driving signal D3 in the driving output module of the first voltage domain circuit VCCA remains at a low level, which does not affect the input of the first signal A on the first signal end side.

[0030] Similarly, when the second signal terminal is the input terminal and the first signal terminal is the output terminal, the second voltage domain voltage signal D1 is maintained at a low level, and the input second signal B passes through the second NOR gate NOR2, the fifth inverter INV5 and the first level conversion module in sequence to generate a drive signal D2 that is input to the first voltage domain circuit VCCA; the drive output module of the first voltage domain circuit VCCA controls the first rising edge monostable circuit to generate a drive signal D4 that is input to the gate of the first PMOS tube PM1, and controls the first falling edge monostable circuit to generate a drive signal D5 that is input to the gate of the first NMOS tube NM1, generates a strong drive between the drain of the first PMOS tube PM1 and the drain of the first NMOS tube NM1, and controls the weak drive between the drain of the second PMOS tube PM2 and the drain of the second NMOS tube NM2, and outputs a first signal A that is in phase with the second signal B.

[0031] At the same time, the drive signal D2 is input into the sixth inverter INV6 to generate the drive signal D3, and the drive signal D3 is fed back to the input end of the first inverter INV1, and the first voltage domain voltage signal C1 with a phase opposite to the first signal A is generated through the first NAND gate NAND1, and is input to the second input end of the first NOR gate NOR1, so that the two input signals of the first NOR gate NOR1 are in opposite phases, and the first NOR gate NOR1 maintains a low level output, and after passing through the second inverter INV2 and the second level conversion module, the drive signal C2 is generated to remain at a high level. Therefore, the strong drive in the second voltage domain circuit VCCB drive output module will not be turned on, and the bidirectional level conversion circuit can be prevented from being turned on by mistake. Moreover, the drive signal C3 in the second voltage domain circuit VCCB drive output module remains at a low level, which does not affect the input of the second signal B on the second signal end side.

[0032] In particular, in the present embodiment, the first, second, third, and fourth rising edge monostable circuits and the first and second falling edge monostable circuits are all monostable circuits, which have two different working states, namely, a steady state and a quasi-stable state. Under the action of an external trigger pulse, the monostable circuit can flip from a steady state to a quasi-stable state, and automatically return to a steady state after maintaining the quasi-stable state for a period of time.

[0033] The duration of the temporary stable state depends on the charging and discharging time of the RC circuit in the monostable circuit, and has nothing to do with the width and amplitude of the trigger pulse. Figure 1 The transient stable state time of the monostable circuit is short, which is used to start strong drive in a short time to improve the output driving capability and transmission speed.

[0034] Specifically, a rising edge triggered monostable circuit such as Figure 2 As shown, Figure 2 Here R1 is a resistor, PM5~PM10 are PMOS tubes, and NM5~NM10 are NMOS tubes.

[0035] In steady state, the output signal OUT of the circuit remains at a high level. When the input signal IN changes from a low level to a high level at the rising edge, the gate signals of the PMOS tube PM10 and the NMOS tube NM9 quickly change to a low level. Due to the delay generated by the resistor R1 and the MOS capacitor NM6, the gates of the PMOS tube PM9 and the NMOS tube NM10 temporarily remain at a high level. At this time, the output signal OUT briefly changes to a low level, and the circuit enters a temporary steady state; after a period of time, the gates of the PMOS tube PM9 and the NMOS tube NM10 change to a low level, and the output signal OUT changes back to a high level, and the circuit returns to a steady state.

[0036] Specifically, a falling edge triggered monostable circuit such as Figure 3 As shown, Figure 3 In the figure, R2 is a resistor, PM11~PM16 are PMOS tubes, and NM11~NM16 are NMOS tubes. The principle is similar to the monostable circuit triggered by the rising edge.

[0037] In steady state, the output signal OUT of the circuit remains at a low level. At the falling edge of the input signal IN changing from a high level to a low level, the gate signals of the PMOS tube PM16 and the NMOS tube NM16 quickly change to a low level. Due to the delay generated by the resistor R2 and the MOS capacitor PM12, the gates of the PMOS tube PM15 and the NMOS tube NM15 temporarily remain at a low level. At this time, the output signal OUT briefly changes to a high level, and the circuit enters a temporary steady state. After a period of time, the gates of the PMOS tube PM15 and the NMOS tube NM15 change to a high level, and the output signal OUT changes to a low level, and the circuit returns to a steady state.

[0038] In summary, the automatic direction sensing level conversion circuit of the present invention can not only realize bidirectional level conversion, but also can automatically sense the transmission direction of the switching signal, without the need for additional signals to control the transmission direction, thus simplifying the system structure and reducing costs. At the same time, the present invention turns on the strong drive output in a short time through a monostable circuit, thereby improving the output drive capability and transmission speed, and turns off the strong drive output on the other side through a feedback signal, thereby avoiding the false start of the bidirectional level conversion circuit.

[0039] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A level conversion circuit for automatic direction sensing, characterized in that: include: A first voltage domain circuit, a second voltage domain circuit, a first level conversion module, and a second level conversion module; The first voltage domain circuit and the second voltage domain circuit have the same structure, and both include a driving input module and a driving output module; The first voltage domain circuit is connected to the first signal terminal, the second voltage domain circuit is connected to the second signal terminal, and the first signal terminal and the second signal terminal are bidirectional ports; The level conversion circuit inputs the first signal A input to the first signal terminal into the second level conversion module through the driving input module of the first voltage domain circuit, generates a driving signal C2 at the output terminal of the second level conversion module, inputs it to the driving output module of the second voltage domain circuit, controls the monostable circuit in the driving output module to generate a corresponding strong drive, and controls the weak drive at the same time, outputs the second signal B which is in phase with the first signal A to the second signal terminal; or inputs the second signal B input to the second signal terminal into the first level conversion module through the driving input module of the second voltage domain circuit, generates a driving signal D2 at the output terminal of the first level conversion module, inputs it to the driving output module of the first voltage domain circuit, controls the monostable circuit in the driving output module to generate a corresponding strong drive, and controls the weak drive at the same time, outputs the first signal A which is in phase with the second signal B to the first signal terminal.

2. The level conversion circuit for automatic direction sensing according to claim 1, characterized in that: The driving input module of the first voltage domain circuit includes: a first inverter INV1, a second inverter INV2, a first NAND gate NAND1, a second NAND gate NAND2, a first NOR gate NOR1, and a fourth rising edge monostable circuit; The first voltage domain voltage signal is C1, the first input end of the first NOR gate NOR1 is connected to the first signal end, the second input end inputs the first voltage domain voltage signal C1, the output end is connected to the input end of the second inverter INV2, and the output end of the second inverter INV2 outputs the driving signal C2 through the second level conversion module; The first voltage domain voltage signal C1 is also input to the first input terminal of the second NAND gate NAND2, the first signal terminal is connected to the second input terminal of the second NAND gate NAND2 through the fourth rising edge monostable circuit, and the output terminal of the second NAND gate NAND2 is connected to the second input terminal of the first NAND gate NAND1; The first input end of the first NAND gate NAND1 is connected to the output end of the first inverter INV1, the input end of the first inverter INV1 is connected to the drive signal D3 generated by the first voltage domain circuit drive output module, and the output end of the first NAND gate NAND1 is connected to the second input end of the first NOR gate NOR1 through the first voltage domain voltage signal C1.

3. The level conversion circuit for automatic direction sensing according to claim 2, characterized in that: The driving output module of the first voltage domain circuit includes: a sixth inverter INV6, a first NMOS tube NM1, a second NMOS tube NM2, a first PMOS tube PM1, a second PMOS tube PM2, a first rising edge monostable circuit, and a first falling edge monostable circuit; The driving signal D2 is input into the gate of the first PMOS transistor PM1 through the first rising edge monostable circuit, and is simultaneously input into the gate of the first NMOS transistor NM1 through the first falling edge monostable circuit; the source of the first PMOS transistor PM1 is connected to the first power supply voltage VCC1, and the drain is connected to the drain of the first NMOS transistor NM1; the source of the first NMOS transistor NM1 is grounded; a strong drive is generated between the drain of the first PMOS transistor PM1 and the drain of the first NMOS transistor NM1, and is output to the first signal terminal; The drive signal D2 is also input to the input end of the sixth inverter INV6, and a drive signal D3 is generated at the output end of the sixth inverter INV6. The drive signal D3 is input to the drain of the second PMOS tube PM2 and the second NMOS tube NM2; the source of the second PMOS tube PM2 is connected to the first power supply voltage VCC1, and the drain is connected to the drain of the second NMOS tube NM2; the source of the second NMOS tube NM2 is grounded; a weak drive is generated between the drain of the second PMOS tube PM2 and the drain of the second NMOS tube NM2, and output to the first signal end.

4. The level conversion circuit for automatic direction sensing according to claim 3, characterized in that: The driving input module of the second voltage domain circuit includes: a fourth inverter INV4, a fifth inverter INV5, a third NAND gate NAND3, a fourth NAND gate NAND4, a second NOR gate NOR2, and a third rising edge monostable circuit; The second voltage domain voltage signal is D1, the first input end of the second NOR gate NOR2 is connected to the second signal end, the second input end inputs the second voltage domain voltage signal D1, the output end is connected to the input end of the fifth inverter INV5, and the output end of the fifth inverter INV5 outputs the driving signal D2 through the first level conversion module; The second voltage domain voltage signal D1 is also input to the first input terminal of the third NAND gate NAND3, the second signal terminal is connected to the second input terminal of the third NAND gate NAND3 through the third rising edge monostable circuit, and the output terminal of the third NAND gate NAND3 is connected to the second input terminal of the fourth NAND gate NAND4; The first input end of the fourth NAND gate NAND4 is connected to the output end of the fourth inverter INV4, the input end of the fourth inverter INV4 is connected to the drive signal C3 generated by the second voltage domain circuit drive output module, and the output end of the fourth NAND gate NAND4 is connected to the second input end of the second NOR gate NOR2 through the second voltage domain voltage signal D1.

5. The level conversion circuit for automatic direction sensing according to claim 4, characterized in that: The driving output module of the second voltage domain circuit includes: a third inverter INV3, a third NMOS tube NM3, a fourth NMOS tube NM4, a third PMOS tube PM3, a fourth PMOS tube PM4, a second rising edge monostable circuit, and a second falling edge monostable circuit; The driving signal C2 is input to the gate of the fourth PMOS transistor PM4 through the second rising edge monostable circuit, and is simultaneously input to the gate of the fourth NMOS transistor NM4 through the second falling edge monostable circuit; the source of the fourth PMOS transistor PM4 is connected to the second power supply voltage VCC2, and the drain is connected to the drain of the fourth NMOS transistor NM4; the source of the fourth NMOS transistor NM4 is grounded; a strong drive is generated between the drain of the fourth PMOS transistor PM4 and the drain of the fourth NMOS transistor NM4, and is output to the second signal terminal; The drive signal C2 is also input to the input end of the third inverter INV3, and the drive signal C3 is generated at the output end of the third inverter INV3. The drive signal C3 is input to the drains of the third PMOS tube PM3 and the third NMOS tube NM3; the source of the third PMOS tube PM3 is connected to the second power supply voltage VCC2, the drain is connected to the drain of the third NMOS tube NM3, and the source of the third NMOS tube NM3 is grounded; a weak drive is generated between the drain of the third PMOS tube PM3 and the drain of the third NMOS tube NM3, and output to the second signal end.

6. The level conversion circuit for automatic direction sensing according to claim 5, characterized in that: When the first signal terminal is the input terminal and the second signal terminal is the output terminal, the first voltage domain voltage signal C1 is at a low level, and the input first signal A passes through the first NOR gate NOR1, the second inverter INV2, and the second level conversion module in sequence to generate a drive signal C2 which is input to the drive output module of the second voltage domain circuit, controls the second rising edge monostable circuit and the second falling edge monostable circuit to generate a strong drive, and controls the weak drive at the same time, and outputs a second signal B which is in phase with the first signal A; The driving signal C2 simultaneously generates a driving signal C3 through the third inverter INV3, which is fed back to the input end of the fourth inverter INV4, and generates a second voltage domain voltage signal D1 with a phase opposite to the second signal B through the fourth NAND gate NAND4, which is input to the second input end of the second NOR gate NOR2. The two input signals of the second NOR gate NOR2 have opposite phases and output a low level. After passing through the fifth inverter INV5 and the first level conversion module, the driving signal D2 is generated to be a high level. The strong drive in the first voltage domain circuit driving output module is not turned on and the driving signal D3 remains at a low level, which does not affect the input of the first signal A at the first signal end.

7. The level conversion circuit for automatic direction sensing according to claim 5, characterized in that: When the second signal terminal is the input terminal and the first signal terminal is the output terminal, the second voltage domain voltage signal D1 is at a low level, and the input second signal B passes through the second NOR gate NOR2, the fifth inverter INV5, and the first level conversion module in sequence to generate a drive signal D2 which is input to the drive output module of the first voltage domain circuit, controls the first rising edge monostable circuit and the first falling edge monostable circuit to generate a strong drive, and controls the weak drive at the same time, and outputs a first signal A which is in phase with the second signal B; The driving signal D2 simultaneously generates a driving signal D3 through the sixth inverter INV2, which is fed back to the input end of the first inverter INV1, and generates a first voltage domain voltage signal C1 with a phase opposite to the first signal A through the first NAND gate NAND1, which is input to the second input end of the first NOR gate NOR1. The two input signals of the first NOR gate NOR1 are in opposite phases and output a low level. After passing through the second inverter INV2 and the second level conversion module, the driving signal C2 is generated to be a high level. The strong drive in the second voltage domain circuit driving output module is not turned on and the driving signal C3 remains at a low level, which does not affect the input of the second signal B at the second signal end.

8. The level conversion circuit for automatic direction sensing according to claim 5, characterized in that: The first PMOS transistor PM1, the first NMOS transistor NM1, and the third PMOS transistor PM3, the third NMOS transistor NM3 are strong drive transistors; the second PMOS transistor PM2, the second NMOS transistor NM2, the fourth PMOS transistor PM4, the fourth NMOS transistor NM4 are weak drive transistors.

9. The level conversion circuit for automatic direction sensing according to claim 5, characterized in that: The first, second, third and fourth rising edge monostable circuits and the first and second falling edge monostable circuits are all monostable circuits, and their working states include steady state and temporary steady state; the monostable circuit flips from steady state to temporary steady state through an external trigger pulse, and then automatically returns to steady state.

10. The level conversion circuit for automatic direction sensing according to claim 9, characterized in that: The monostable circuit includes an RC circuit composed of a resistor R and a MOS capacitor NM. The maintenance time of the temporary stable state of the monostable circuit depends on the charging and discharging time of the RC circuit.

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