Distributed power management circuit

Abstract

A distributed power management circuit is provided. The distributed power management circuit includes a primary power management integrated circuit (PMIC) and a distributed PMIC separate from the primary PMIC. The primary PMIC is coupled to the distributed PMIC via a conductive path. Notably, the parasitic capacitance of the primary PMIC may interact with the trace inductance of the conductive path to produce an equivalent notch that may reduce the linearity performance of the distributed PMIC. In this regard, in the embodiments disclosed herein, a deQ circuit is provided in the distributed power management circuit to reduce the quality factor (Q factor) of the equivalent notch, thereby improving the linearity performance of the distributed PMIC. Furthermore, the deQ circuit may be configured so as to increase the open loop gain of the distributed PMIC to help reduce current flow in the distributed PMIC, thereby improving the overall energy efficiency of the distributed power management circuit.

Description

[0001] Related Applications

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 386,573 filed on December 8, 2022 and the benefit of U.S. Provisional Patent Application No. 63 / 491,438 filed on March 21, 2023, the disclosures of the foregoing applications are hereby incorporated by reference in their entirety. Technical Field

[0003] The technology of the present disclosure generally relates to a distributed power management circuit, and more particularly, to a distributed power management circuit including a main power management integrated circuit (PMIC) and a distributed PMIC. Background Art

[0004] Mobile communication devices have become increasingly common in today's society for providing wireless communication services. The popularity of these mobile communication devices is driven in part by the many functions now enabled on such devices. Increased processing power in such devices means that mobile communication devices have evolved from mere communication tools to sophisticated mobile multimedia centers capable of enhancing the user experience.

[0005] The redefined user experience requires higher data rates provided by wireless communication technologies, such as fifth generation new radio (5G-NR) technologies, which are configured to transmit (multiple) millimeter wave (mmWave) radio frequency (RF) signals in the mmWave spectrum at frequencies above 12 GHz. To achieve higher data rates, mobile communication devices may employ power amplifiers to increase the output power of the mmWave RF signals (e.g., to maintain sufficient energy per bit).

[0006] Envelope tracking (ET) and average power tracking (APT) are power management techniques designed to improve the efficiency level of power amplifiers to help reduce power consumption and heat dissipation of power management circuits. In a typical power management circuit, a power amplifier is configured to amplify an RF signal based on a time-varying voltage that tracks the time-varying envelope of the RF signal. It can be appreciated that the better the time-varying voltage tracks the time-varying power envelope, the higher the linearity that can be achieved by the power amplifier, especially when the RF signal is modulated over a wide modulation bandwidth (e.g., >100MHz). Summary of the invention

[0007] Embodiments of the present disclosure relate to a distributed power management circuit. The distributed power management circuit includes a main power management integrated circuit (PMIC) and a distributed PMIC separated from the main PMIC. The main PMIC is coupled to the distributed PMIC via a conductive path. It is worth noting that the parasitic capacitance of the main PMIC may interact with the trace inductance of the conductive path to produce an equivalent notch that may reduce the linearity performance of the distributed PMIC. In this regard, in the embodiments disclosed herein, a deQ circuit is provided in the distributed power management circuit to reduce the quality factor (Q factor) of the equivalent notch, thereby improving the linearity performance of the distributed PMIC. In addition, the deQ circuit can be configured to increase the open-loop gain of the distributed PMIC to help reduce the current flow in the distributed PMIC, thereby improving the overall energy efficiency of the distributed power management circuit.

[0008] In one aspect, a distributed power management circuit is provided. The distributed power management circuit includes a distributed PMIC. The distributed PMIC is configured to generate a distributed voltage based on a distributed target voltage. The distributed power management circuit also includes a main PMIC. The main PMIC is configured to generate the distributed target voltage and provide a low-frequency current to the distributed PMIC via a conductive path provided between the main PMIC and the distributed PMIC. The distributed power management circuit also includes a deQ circuit. The deQ circuit is provided between the distributed PMIC and the main PMIC. The deQ circuit is configured to resonate at a series resonant frequency to reduce the quality factor, i.e., the Q factor, of an equivalent notch caused by the equivalent inductance of the conductive path and the equivalent capacitance of the main PMIC.

[0009] On the other hand, a wireless device is provided. The wireless device includes at least one primary antenna provided on a first side of the wireless device. The wireless device also includes at least one secondary antenna provided on a second side of the wireless device. The wireless device also includes at least one primary power amplifier circuit. The at least one primary power amplifier circuit is configured to amplify a radio frequency (RF) signal based on a voltage for transmission via the at least one primary antenna. The wireless device also includes at least one distributed power amplifier circuit. The at least one distributed power amplifier circuit is configured to amplify the RF signal based on a distributed voltage for transmission via the at least one secondary antenna. The wireless device also includes a distributed power management circuit. The distributed power management circuit includes a distributed PMIC. The distributed PMIC is configured to generate the distributed voltage based on a distributed target voltage and provide the distributed voltage to the at least one distributed power amplifier circuit. The distributed power management circuit also includes a main PMIC. The main PMIC is configured to generate the voltage and provide the voltage to the at least one primary power amplifier circuit. The main PMIC is also configured to generate the distributed target voltage and provide a low-frequency current to the distributed PMIC via a conductive path provided between the main PMIC and the distributed PMIC. The distributed power management circuit further includes a deQ circuit. The deQ circuit is provided between the distributed PMIC and the main PMIC. The deQ circuit is configured to resonate at a series resonant frequency to reduce a quality factor, i.e., a Q factor, of an equivalent notch caused by an equivalent inductance of a conductive path and an equivalent capacitance of the main PMIC.

[0010] Those skilled in the art will appreciate the scope of the present disclosure and become aware of additional aspects thereof after reading the following detailed description of the preferred embodiments and the associated drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0012] FIG1 is a schematic diagram of a wireless device, wherein an equivalent notch present in a conventional distributed power management circuit may degrade the overall linearity performance of the wireless device;

[0013] Figure 2A and 2B is a schematic diagram of an exemplary distributed power management circuit, which may be provided in the wireless device of FIG. 1 to effectively reduce the Q factor of the equivalent notch;

[0014] Figure 3 yes Figure 2A and2B A schematic diagram of an exemplary deQ network in a deQ circuit of a distributed power management circuit;

[0015] Figures 4A-4C Is to provide about Figure 3 How can the deQ circuit in Figure 2A and 2B A graph of an exemplary illustration of the overall performance of a distributed power management circuit;

[0016] Figure 5 yes Figure 2A and 2B A schematic diagram of an exemplary distributed control circuit in a distributed power management circuit of FIG. 1 ; and

[0017] Figure 6 Which can provide Figure 2A and 2B Schematic diagram of exemplary user components of a distributed power management circuit. DETAILED DESCRIPTION

[0018] The embodiments set forth below represent information necessary to enable those skilled in the art to practice the embodiments and to illustrate the best mode for practicing the embodiments. After reading the following description with reference to the accompanying drawings, those skilled in the art will understand the concepts of the present disclosure and will appreciate the applications of these concepts not specifically set forth herein. It should be understood that these concepts and applications are within the scope of the present disclosure and the appended claims.

[0019] It will be appreciated that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish different elements. For example, without departing from the scope of the present disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more items in the associated listed items.

[0020] It should be understood that when an element such as a layer, a region or a substrate is referred to as being "on another element" or "extending onto another element", it may be directly on another element or directly extending onto another element, or there may also be an intermediate element. On the contrary, when an element is referred to as being "directly on another element" or "extending directly onto another element", there is no intermediate element. Similarly, it should be understood that when an element such as a layer, a region or a substrate is referred to as being "above another element" or "extending above another element", it may be directly above another element or directly extending above another element, or there may also be an intermediate element. On the contrary, when an element is referred to as being "directly above another element" or "extending directly above another element", there is no intermediate element. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to another element, or there may be an intermediate element. On the contrary, when an element is referred to as being "directly connected" or "directly coupled" to another element, there is no intermediate element.

[0021] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe one element, layer or region's relationship to another element, layer or region as illustrated in the figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0022] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are also intended to include the plural forms. It should also be understood that when used herein, the terms "comprises", "comprising", "includes", and / or "including" specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0023] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that, unless expressly defined herein, the terms used herein should be interpreted as having a meaning consistent with their meaning in the context of this specification and the relevant art, and will not be interpreted in an idealized or overly formal sense.

[0024] Embodiments of the present disclosure relate to a distributed power management circuit. The distributed power management circuit includes a main power management integrated circuit (PMIC) and a distributed PMIC separated from the main PMIC. The main PMIC is coupled to the distributed PMIC via a conductive path. It is worth noting that the parasitic capacitance of the main PMIC may interact with the trace inductance of the conductive path to produce an equivalent notch that may reduce the linearity performance of the distributed PMIC. In this regard, in the embodiments disclosed herein, a deQ circuit is provided in the distributed power management circuit to reduce the quality factor (Q factor) of the equivalent notch, thereby improving the linearity performance of the distributed PMIC. In addition, the deQ circuit can be configured to increase the open-loop gain of the distributed PMIC to help reduce the current flow in the distributed PMIC, thereby improving the overall energy efficiency of the distributed power management circuit.

[0025] In discussing Figure 2A Before beginning the distributed power management circuit of the present disclosure, a brief discussion of a wireless device incorporating an existing distributed power management circuit is first provided in FIG. 1 to help understand how an undesirable equivalent notch between a main PMIC and a distributed PMIC may affect the overall linearity performance of the wireless device.

[0026] 1 is a schematic diagram of a wireless device 10 in which an equivalent notch 12 between a main PMIC 14 and a distributed PMIC 16 may degrade the overall linearity performance of the wireless device 10. In a non-limiting example, the wireless device 10 may include at least one primary antenna 18 disposed on a first side 20 (e.g., a top side) of the wireless device 10 and at least one secondary antenna 22 disposed on a second side 24 (e.g., a bottom side) of the wireless device 10. It is noteworthy that the primary antenna 18 and the secondary antenna 22 are so disposed to help mitigate the so-called hand-blocking effect in the wireless device 10.

[0027] The wireless device 10 also includes at least one main power amplifier circuit 26 and at least one distributed power amplifier circuit 28. The main power amplifier circuit 26 is provided next to the main antenna 18 to generate a power amplifier based on the voltage V CC The radio frequency (RF) signal 30 is amplified for transmission via the primary antenna 18. A distributed power amplifier circuit 28 is provided adjacent to the secondary antenna 22 to generate a power amplifier based on the distributed voltage DV CC The RF signal 30 is amplified for transmission via the secondary antenna 22. Notably, the wireless device 10 is configured to transmit the RF signal 30 via the primary antenna 18 (when the secondary antenna 22 is blocked) or the secondary antenna 22 (when the primary antenna 18 is blocked).

[0028] The wireless device 10 also includes an existing distributed power management circuit 32, which includes a main PMIC 14 and a distributed PMIC 16. Specifically, the main PMIC 14 is provided closer to the main power amplifier circuit 26 than to the distributed power amplifier circuit 28. In contrast, the distributed PMIC 16 is provided closer to the distributed power amplifier circuit 28 than to the main power amplifier circuit 26.

[0029] The main PMIC 14 is coupled to the distributed PMIC 16 via a conductive path 38 (eg, a conductive trace). Thus, the distributed PMIC 16 will experience an equivalent trace inductance L caused by the conductive path 38. T and the equivalent capacitance C of the main PMIC 14 VO (eg, parasitic capacitance). Note that, contrary to indicating the actual physical circuit, the equivalent notch 12 is shown here to represent the equivalent trace inductance L T and equivalent capacitance C VO collective effect.

[0030] The equivalent notch 12 can be at the equivalent series resonant frequency f RESONANCE The lower resonance and corresponds to the Q factor shown in the following equations (Equation 1 and Equation 2).

[0031]

[0032] As shown in the equation (Equation 2), the Q factor of the equivalent notch 12 is related to the equivalent series resonant frequency f of the distributed PMIC 16. RESONANCE and modulation bandwidth f BWIDTH When the equivalent series resonant frequency f RESONANCE Approximate bandwidth f BWIDTH When the equivalent series resonant frequency f RESONANCE With the modulation bandwidth f BWIDTH When the equivalent series resonant frequency f RESONANCE Close enough to the modulation bandwidth f BWIDTH When the equivalent notch 12 is smaller than the equivalent notch 12, the equivalent notch 12 may cause linearity degradation in the distributed PMIC 16 and, therefore, in the distributed power amplifier circuit 28. Since it may be difficult to completely eliminate the equivalent notch 12, it is desirable to reduce the Q factor of the equivalent notch 12 as much as possible to help avoid or at least mitigate linearity degradation in the distributed PMIC 16 and the distributed power amplifier circuit 28.

[0033] At this point, Figure 2A1 is a schematic diagram of an exemplary distributed power management circuit 40, which can replace the existing distributed power management circuit 32 in the wireless device 10 of FIG. 1 to effectively reduce the Q factor of the equivalent notch 12. Herein, the distributed power management circuit 40 includes a main PMIC 42, a distributed PMIC 44, and a conductive path 46 (e.g., a conductive trace) coupling the main PMIC 42 with the distributed PMIC 44. In a non-limiting example, the main PMIC 42 may be functionally equivalent to the main PMIC 14 in FIG. 1 and disposed closer to the main power amplifier circuit 26, while the distributed PMIC 44 may be functionally equivalent to the distributed PMIC 16 in FIG. 1 and disposed closer to the distributed power amplifier circuit 28.

[0034] Since the main PMIC 42 is coupled to the distributed PMIC 44 through the conductive path 46, an equivalent notch 48 exists between the main PMIC 42 and the distributed PMIC 44. Similar to the equivalent notch 12 in FIG. 1, the equivalent notch 48 is caused by the equivalent trace inductance L of the conductive path 46. T and the equivalent capacitance C of the main PMIC 42 VO Therefore, the equivalent notch 48 will be associated with the Q factor described by the above equation (Equation 2). Therefore, the equivalent notch 48 will cause the same linearity problem to the distributed PMIC 44 as previously described in FIG. 1 .

[0035] To help reduce the Q factor of the equivalent notch 48, according to an embodiment of the present disclosure, the distributed power management circuit 40 is configured to additionally include a deQ circuit 50. In the context of the present disclosure, "deQ" means "reducing the Q factor of the equivalent notch 48". Q As described in detail below, the deQ circuit 50 is configured to deQ The deQ circuit 50 can be configured to increase the open-loop gain of the distributed PMIC 44, thereby reducing the current in the distributed PMIC 44. Therefore, it is possible to improve the linearity performance of the distributed PMIC 44 and the overall energy efficiency of the distributed power management circuit 40. In addition, the deQ circuit 50 can help reduce the peak voltage experienced by the main PMIC 42, thereby protecting the main PMIC 42 from exceeding the inherently safe operating area. In a non-limiting example, the deQ circuit 50 can protect the main PMIC 42 from the breakdown voltage (also known as BVDSS). In this article, the breakdown voltage is the voltage that can break down the reverse biased body-drift diode through the avalanche multiplication process when the gate and source of the MOSFET are shorted together and allow a large amount of current to flow between the source and drain of the metal oxide semiconductor field effect transistor (MOSFET).

[0036] In an embodiment, the master PMIC 42 includes a master voltage processing circuit 52, a switch circuit 54, and a master control circuit 56. Herein, the master voltage processing circuit 52 is configured to generate a voltage based on the amplifier target voltage V AMP A voltage V is generated at the main voltage output 57 CC The switch circuit 54 includes a multi-level charge pump (MCP) 58 and a power inductor L P Specifically, the MCP 58 is configured to BAT And generate a low frequency voltage V according to the duty cycle signal 60 (eg, a sawtooth signal) DC . Power inductor L P is coupled to the auxiliary voltage output 62 and is configured to be based on the low frequency voltage V DC The low-frequency current I is induced at the auxiliary voltage output 62. DC In this context, the auxiliary voltage output 62 is additionally coupled to the conductive path 46 so that the low-frequency current I DC May be provided to the distributed PMIC 44 via conductive paths 46 .

[0037] In a non-limiting example, the MCP 58 may be a buck-boost DC-DC converter that may operate in a buck mode and / or a boost mode. When operating in the buck mode, the MCP 58 may generate 0×V BAT (i.e., 0V) or 1×V BAT (i.e., V BAT ) of the low frequency voltage V DC When operating in boost mode, the MCP 58 can generate 2×V BAT (i.e., 2V BAT ) of the low frequency voltage V DC The duty cycle signal 60 may be determined such that the MCP 58 generates 0×V BAT , 1×V BAT and / or 2V BAT The low frequency voltage V DC For example, the duty cycle signal 60 may be determined so that the MCP 58 generates an average of 30% @ 0×V BAT 、30%@1×V BAT and 40%@2×V BAT The low frequency voltage V DC Therefore, by adapting the duty cycle signal 60, it is possible to control the low frequency voltage V DC And thus control the low frequency current I DC .

[0038] In an embodiment, the main control circuit 56 includes a main controller 64 and a pulse width modulation (PWM) modulator 66. For example, the main controller 64, which can be a relay type controller (BBC), is configured to generate a pulse width modulation (PWM) modulator 66 based on a voltage V CC Set the target voltage V TGT Generates the amplifier target voltage V AMP In a non-limiting example, the master controller 64 may receive a target voltage V from a transceiver circuit (not shown). TGT On the other hand, the PWM modulator 66 is configured to be based on the PWM target voltage V PWM The duty cycle signal 60 is generated. As described in detail later, the PWM target voltage V PWM Provided by the distributed PMIC 44 to the PWM modulator 66 to help regulate the low frequency current I provided to the distributed PMIC 44 DC .

[0039] The distributed PMIC 44 includes a distributed voltage processing circuit 68. The distributed voltage processing circuit 68 is configured to generate a voltage signal based on the distributed amplifier target voltage DV TGT-AMP A distributed voltage DV is generated at a distributed voltage output 70 CC Specifically, the distributed voltage processing circuit 68 includes a distributed voltage amplifier 72 and a distributed offset capacitor DC OFF The distributed voltage amplifier 72 is configured to generate a voltage based on the distributed amplifier target voltage DV TGT-AMP and distributed supply voltage DV SUP Generate distributed initial voltage DV AMP , the distributed amplifier target voltage is the distributed initial voltage DV AMP Set the target. Distributed offset capacitor DC OFF is coupled between the distributed voltage amplifier 72 and the distributed voltage output 70. In an embodiment, the distributed offset capacitor DC OFF is configured to distribute the initial voltage DV AMP Increase the distributed offset voltage DV OFF , thereby generating a distributed voltage DV at the distributed voltage output 70 CC (DV CC =DV AMP +DV OFF The distributed voltage processing circuit 68 further includes a feedback path 73, which is configured to convert the distributed voltage DV CC Feedback from DV CC-FB Provided to the distributed voltage amplifier 72.

[0040] In this paper, the distributed offset capacitor DC OFF The low frequency current I DCand / or the distributed high frequency current DI supplied by the distributed voltage amplifier 72 AMP Charge to increase the distributed offset voltage DV OFF . Distributed offset capacitors DC OFF It can also be absorbed by the distributed high-frequency current DI in the distributed voltage amplifier 72 AMP discharge to reduce the distributed offset voltage DV OFF In an embodiment, the distributed voltage amplifier 72 is configured to generate a distributed sensing current DI SENSE To indicate the distributed high frequency current DI supplied or absorbed by the distributed voltage amplifier 72 AMP The actual amount.

[0041] According to an embodiment of the present disclosure, the deQ circuit 50 includes a deQ network 74 and a distributed inductor L DPA . Distributed inductor L DPA The deQ network 74 may be provided on the conductive path 46 but external to the distributed PMIC 44, or integrated into the distributed PMIC 44 and external to the conductive path 46. On the other hand, the deQ network 74 is disposed within the main PMIC 42 and is coupled to the conductive path 46 via the auxiliary voltage output 62. In this regard, the deQ network 74 is not on the conductive path 46 (also referred to as external thereto).

[0042] In an alternative embodiment, the distributed inductor L DPA may be provided on conductive path 46, but closer to main PMIC 42. In this regard, Figure 2B is a schematic diagram providing an exemplary illustration of a distributed power management circuit 40, wherein the distributed inductor L DPA Provided external to the main PMIC 42 and on the conductive path 46 . Figure 2A and 2B Common elements between the present invention are shown with common element numbers and will not be described again in this article.

[0043] Figure 3 is a schematic diagram providing an exemplary illustration of a deQ network 74 configured in accordance with an embodiment of the present disclosure. Figure 2A , 2B Common elements between and 3 are shown therein with common element numbers and will not be re-described here.

[0044] The deQ network 74 includes a capacitor C coupled in series between the auxiliary voltage output 62 and ground (GND). R , resistor R R and switch S R In a non-limiting example, the deQ network 74 can be closed by closing the switch S R to activate, and by opening the switch SR It is worth noting that due to the deQ network 74 and the equivalent capacitor C VO In parallel, the deQ network 74 can therefore reduce the Q factor of the equivalent notch 48 when the deQ network 74 is activated.

[0045] For example, the equivalent impedance Z(s) of the deQ network 74 may be calculated in the equation (Equation 3) as follows.

[0046]

[0047] By replacing "s" with "jω" (ω represents the pulsation frequency), the equation (Equation 3) can be rewritten as equation (Equation 4).

[0048]

[0049] Therefore, the Q factor of Z(jω) can be determined as in the following equation (Equation 5).

[0050]

[0051] From the equation (Equation 5), it can be seen that the Q factor contains two terms, one as a function of 1 / ω and the other as a function of ω. In order to achieve the lowest Q factor, the deQ network 74 must have a series resonant frequency f that satisfies the condition dQ factor / dω=0. deQ Therefore, the series resonant frequency f deQ and the corresponding minimum Q factor (denoted as “Q MIN ”) can be expressed in the following equations (Equation 6 and Equation 7).

[0052]

[0053] From the equation (Equation 7), we can see that Q MIN By increasing C R However, according to the equation (Equation 6), the higher C R It can also reduce f deQ , so the distributed inductor L DPA It is necessary in the deQ circuit 50. In this paper, the distributed inductor L DPA For the series resonant frequency f deQ In an embodiment, the distributed inductor L can be determined based on the following equation (Equation 8): DPA The optimal value of .

[0054]

[0055] Return to reference Figure 2A , in addition to helping in the series resonant f deQ Next Q MIN In addition, the distributed inductor L DPA It also presents a relatively high impedance Z to the distributed PMIC 44, and in particular to the distributed voltage amplifier 72. DPA It is understandable that the higher impedance Z DPA The current in the distributed voltage amplifier 72 can be reduced, thereby helping to reduce energy waste in the distributed PMIC 44. In addition, the higher impedance Z DPA The distributed voltage amplifier 72 and the equivalent inductor L T and equivalent capacitance C VO Isolation helps reduce distributed voltage DV CC In addition, the distributed inductor L DPA The series resonant frequency f deQ moves well within the modulation bandwidth of the distributed voltage amplifier 72, thereby minimizing the distributed voltage DV CC Around the series resonant frequency f deQ Therefore, the linearity, error vector magnitude (EVM), and adjacent channel leakage ratio (ACLR) of the distributed PMIC 44 can be improved.

[0056] Figure 4A and 4B It is shown Figure 3 How can the deQ circuit 50 in the Figure 2A and 2B The overall performance of the distributed power management circuit 40 is shown in FIG. Figure 4A is a graph showing the phase improvement provided by the deQ circuit 50 in FIGS. 2 and 3 .

[0057] exist Figure 4A In the example, the first curve 76 shows the impedance Z without the deQ circuit 50. DPA With distributed voltage DV CC and the second curve 78 shows the relative phase between the impedance Z with the deQ circuit 50 DPA With distributed voltage DV CC As shown, without the deQ circuit 50, the impedance Z DPA With distributed voltage DV CC The relative phase between the series resonant frequency f deQ In contrast, with the deQ circuit 50, the impedance Z DPA With distributed voltage DV CC The relative phase between the series resonant frequency f deQKeep stable.

[0058] Figure 4B is a diagram showing the impedance Z provided by the deQ circuit 50 in FIGS. 2 and 3 DPA Here, the first curve 80 shows the impedance Z in decibels (dB) without the deQ circuit 50. DPA and frequency, and the second curve 82 shows the impedance Z in dB with the deQ circuit 50 DPA As shown, without the deQ circuit 50, the impedance Z DPA At the series resonant frequency f deQ In contrast, with the deQ circuit 50, the impedance Z DPA At the series resonant frequency f deQ Keep stable.

[0059] It is worth noting that the impedance Z DPA does drop at frequency f0, regardless of whether deQ circuit 50 is employed. As described below, the reduced impedance Z can be corrected by increasing the modulation bandwidth (also called open-loop gain) of the distributed voltage amplifier 72 DPA .

[0060] Return to reference Figure 2A The distributed PMIC 44 further includes a distributed control circuit 84. The distributed control circuit 84 may be configured to control the distributed PMIC 44 based on the distributed sensing current DI SENSE The modulation bandwidth of the distributed voltage amplifier 72 is increased. In addition, by determining the capacitor C R , resistor R R and distributed inductor L DPA By using an appropriate value of deQ moves well into the increased modulation bandwidth of the distributed voltage amplifier 72, thereby facilitating correction Figure 4B The reduced impedance Z shown in DPA .

[0061] Figure 4C 2 is a graph showing the impedance Z caused by increasing the modulation bandwidth of the distributed voltage amplifier 72. DPA In this paper, curve 86 shows the improvement of Figure 4B The impedance Z shown in DPA Compared to the improved impedance Z' at frequency f0 DPA .

[0062] Return to reference Figure 2A The distributed control circuit 84 is also configured to be based on the distributed target voltage DV TGT, Distributed initial voltage DV AMP and the distributed sensing current DI SENSE Determine the PWM target voltage V PWM . Figure 5 2 is a schematic diagram providing an exemplary illustration of a distributed control circuit 84 configured in accordance with an embodiment of the present disclosure. Figure 5 Common elements between are shown in these figures with common element numbers and will not be re-described herein.

[0063] Distributed control circuit 84 includes distributed operational amplifier circuit 88 and distributed common controller 90. Distributed operational amplifier circuit 88 includes operational amplifier 92. Operational amplifier 92 includes an inverting input terminal "-" coupled to distributed common controller 90 via input circuit 94. Operational amplifier 92 also includes a non-inverting input terminal "+" directly coupled to distributed common controller 90. Operational amplifier 92 also includes an output terminal 96, which is coupled to Figure 2A and 2B The PWM modulator 66 in the circuit thus sets the PWM target voltage V PWM is provided to the PWM modulator 66. The output terminal 96 is also coupled to the inverting input terminal "-" via a feedback circuit 98.

[0064] Distributed common controller 90 from Figure 2A and 2B The master PMIC 42 in receives the distributed target voltage DV TGT Therefore, the distributed common controller 90 can determine the distributed offset target voltage DV TGT-OFF and the distributed offset voltage DV OFF In an embodiment, the distributed offset target voltage DV TGT-OFF According to the distributed target voltage DV TGT The distributed common controller 90 can also be predefined and stored in the distributed common controller 90 based on the distributed initial voltage DV AMP and distributed voltage DV CC-FB The feedback determines the distributed offset voltage DV OFF Then, the distributed common controller 90 can set the distributed offset voltage DV OFF and the distributed offset target voltage DV TGT-OFF The inverting input terminal "-" and the non-inverting input terminal "+" of the operational amplifier 92 are provided respectively. Herein, the operational amplifier 92 also receives the distributed sensing current DI from the distributed voltage processing circuit 68 via the inverting input terminal "-". SENSE , and thus generate the PWM target voltage V PWM , as shown in the equation below (Equation 9).

[0065] V PWM =DV TGT-OFF +Z FB / Z IN *(DV TGT-OFF -DV OFF )-Z FB *DI SENSE (Equation 9)

[0066] In the equation (Equation 9), Z IN represents the corresponding impedance of the input circuit 94, and Z FB represents the corresponding impedance of the feedback circuit 98. PWM target voltage V PWM The PWM modulator 66 can adapt the duty cycle signal 60 to control the switch circuit 54 according to the distributed target voltage DV TGT Modulate low frequency current I DC Therefore, it is possible to reduce or even eliminate the distributed high-frequency current DI in the distributed PMIC 44 AMP , thereby helping to improve the efficiency of the distributed voltage amplifier 72 and reduce energy consumption in the distributed power management circuit 40.

[0067] Figure 2A and 2B The distributed power management circuit 40 may be provided in the user device to support the above embodiments. In this regard, Figure 6 Which can provide Figure 2A and 2B Schematic diagram of an exemplary user element 100 of the distributed power management circuit 40.

[0068] Herein, user element 100 can be any type of user element, such as a mobile terminal, smart watch, tablet computer, computer, navigation device, access point and similar wireless communication device supporting wireless communication, such as cellular, wireless local area network (WLAN), Bluetooth and near field communication. User element 100 will generally include control system 102, baseband processor 104, transmission circuit system 106, receiving circuit system 108, antenna switch circuit system 110, multiple antennas 112 and user interface circuit system 114. In a non-limiting example, for example, control system 102 can be a field programmable gate array (FPGA). In this regard, control system 102 can include at least a microprocessor, an embedded memory circuit and a communication bus interface. Receive circuit system 108 receives radio frequency signals from one or more base stations via antenna 112 and through antenna switch circuit system 110. Low noise amplifier and filter cooperate to amplify and eliminate broadband interference from received signals for processing. Downconversion and digitization circuitry (not shown) then downconverts the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using an analog-to-digital converter (ADC).

[0069] The baseband processor 104 processes the digitized received signal to extract the information or data bits transmitted in the received signal. Such processing typically includes demodulation, decoding, and error correction operations, which will be discussed in more detail below. The baseband processor 104 is typically implemented in one or more digital signal processors (DSPs) and application specific integrated circuits (ASICs).

[0070] For transmission, the baseband processor 104 receives digitized data, which may represent voice, data, or control information, from the control system 102, and encodes the digitized data for transmission. The encoded data is output to the transmit circuit system 106, where a digital-to-analog converter (DAC) converts the digitally encoded data into an analog signal, and a modulator modulates the analog signal onto a carrier signal at the desired transmit frequency or frequencies. A power amplifier amplifies the modulated carrier signal to a level suitable for transmission and delivers the modulated carrier signal to an antenna 112 via an antenna switch circuit system 110. Multiple antennas 112 and duplicate transmit circuit systems 106 and receive circuit systems 108 may provide spatial diversity. Those skilled in the art will understand the modulation and processing details.

[0071] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the claims below.

Claims

1. A distributed power management circuit (40), comprising: A distributed power management integrated circuit PMIC (44) is configured to generate a power supply voltage based on a distributed target voltage (DV TGT ) generates a distributed voltage (DV CC ); A master PMIC (42) is configured to generate the distributed target voltage (DV TGT ) and provides a low frequency current (I ) to the distributed PMIC (44) via a conductive path (46) provided between the main PMIC (42) and the distributed PMIC (44). DC ); as well as A deQ circuit (50) is provided between the distributed PMIC (44) and the main PMIC (42) and is configured to deQ ) to reduce the equivalent inductance (L) of the conductive path (46) T ) and the equivalent capacitance (C VO ) together cause the quality factor of the equivalent notch (48), i.e., the Q factor.

2. The distributed power management circuit (40) according to claim 1, wherein the deQ circuit (50) comprises: a deQ network (74) provided within the master PMIC (42) and coupled to the conductive path (46) via an auxiliary voltage output (62); as well as Distributed inductor (L DPA ), which is provided outside the main PMIC (42).

3. The distributed power management circuit (40) according to claim 2, wherein the distributed inductor (L DPA ) is provided as one of the following: on the conductive path (46) and external to the distributed PMIC (44); and Outside the conductive path (46) and inside the distributed PMIC (44).

4. The distributed power management circuit (40) according to claim 2, wherein the distributed inductor (L DPA ) is provided on the conductive path (46) and is external to the main PMIC (42).

5. The distributed power management circuit (40) according to claim 2, wherein the distributed inductor (L DPA ) is also configured to connect the distributed PMIC (44) to the equivalent inductance (L T ) and the equivalent capacitance (C VO )isolation.

6. The distributed power management circuit (40) of claim 2, wherein the deQ network (74) comprises a capacitor (C R )、Resistors (R R ) and switch (S R ), the deQ network (74) is connected to the switch (S R ) is closed and is activated and R ) is deactivated when it is disconnected.

7. The distributed power management circuit (40) according to claim 6, wherein the capacitor (C R ), the resistor (R R ) and the distributed inductor (L DPA ) are jointly selected to increase the modulation bandwidth of the distributed PMIC so that the series resonant frequency of the deQ circuit can fall within the modulation bandwidth of the distributed PMIC.

8. The distributed power management circuit (40) of claim 2, wherein the master PMIC (42) comprises: A switcher circuit (54) coupled to the auxiliary voltage output (62) and comprising: A multi-level charge pump MCP (58) is configured to generate a low frequency voltage (V DC );as well as Power Inductor(L P ), which is configured to be based on the low frequency voltage (V DC ) and the low frequency current (I DC );as well as A pulse width modulation (PWM) modulator (66) is coupled to the MCP (58) and is configured to generate a pulse width modulation (PWM) signal based on a PWM target voltage (V PWM ) generates the duty cycle signal (60).

9. The distributed power management circuit (40) of claim 8, wherein the distributed PMIC (44) comprises: A distributed voltage amplifier (72) configured to: Based on the distributed power supply voltage (DV SUP ) and the distributed amplifier target voltage (DV TGT-AMP ) generates a distributed initial voltage (DV AMP );and Generates a high frequency current (DI) indicative of a current flowing through the distributed voltage amplifier (72) AMP ) of the distributed sensing current (DI SENSE ); Distributed offset capacitors (DC OFF ), which is coupled to the distributed voltage amplifier (72) and the distributed inductor (L DPA ), and is configured to distribute the initial voltage (DV AMP ) increases the distributed offset voltage (DV OFF ) to generate said distributed voltage (DVCC) at a distributed voltage output (70); as well as A distributed control circuit (84) is configured to control the distributed target voltage (DV TGT ), the distributed initial voltage (DV AMP ) and the distributed sensing current (DI SENSE ) determines the PWM target voltage (V PWM ).

10. The distributed power management circuit (40) according to claim 9, wherein the distributed control circuit (84) comprises: A distributed operational amplifier circuit (88) coupled to the PWM modulator (66) and configured to generate a current sense signal based on the distributed sense current (DI SENSE ), the distributed offset voltage (DV OFF ) and the distributed offset target voltage (DV TGT-OFF ) generates the PWM target voltage (V PWM ); as well as A distributed common controller (90) coupled to the distributed operational amplifier circuit (88) and configured to: Based on the distributed voltage (DV CC ) feedback (DV CC-FB ) and the distributed initial voltage (DV AMP ) determines the distributed offset voltage (DV OFF );and Based on the distributed target voltage (DV TGT ) determines the distributed offset target voltage (DV TGT-OFF ).

11. The distributed power management circuit of claim 1, wherein the deQ circuit is further configured to reduce a peak voltage seen by the master PMIC, thereby protecting the master PMIC from exceeding an intrinsically safe operating region.

12. A wireless device (10), comprising: at least one primary antenna (18) provided on a first side (20) of the wireless device (10); at least one secondary antenna (22) provided on a second side (24) of the wireless device (10); At least one main power amplifier circuit (26) configured to CC ) amplifying a radio frequency (RF) signal (30) for transmission via the at least one primary antenna (18); At least one distributed power amplifier circuit (28) configured to generate a power amplifier circuit based on a distributed voltage (DV CC ) amplifying the RF signal (30) for transmission via the at least one secondary antenna (22); as well as A distributed power management circuit (40), comprising: A distributed power management integrated circuit PMIC (44) is configured to generate a power supply voltage based on a distributed target voltage (DV TGT ) generates the distributed voltage (DV CC ) and the distributed voltage (DV CC ) is provided to the at least one distributed power amplifier circuit (28); A master PMIC (42) configured to: Generate the voltage (V CC ) and provides the voltage to the at least one main power amplifier circuit (26); and Generate the distributed target voltage (DV TGT ) and provides a low frequency current (I ) to the distributed PMIC (44) via a conductive path (46) provided between the main PMIC (42) and the distributed PMIC (44). DC ); as well as A deQ circuit (50) is provided between the distributed PMIC (44) and the main PMIC (42) and is configured to deQ ) to reduce the equivalent inductance (L) of the conductive path (46) T ) and the equivalent capacitance (C VO ) together cause the quality factor of the equivalent notch (48), i.e., the Q factor.

13. The wireless device of claim 12, wherein: The at least one primary power amplifier circuit is provided closer to the at least one primary antenna than to the at least one secondary antenna; and The at least one distributed power amplifier circuit is provided closer to the at least one secondary antenna than to the at least one primary antenna.

14. The wireless device of claim 12, wherein the deQ circuit comprises: a deQ network provided inside the master PMIC and coupled to the conductive path via an auxiliary voltage output; as well as A distributed inductor is provided outside the main PMIC.

15. The wireless device of claim 14, wherein the distributed inductor is provided as one of: on the conductive path and external to the distributed PMIC; and Outside the conductive path and inside the distributed PMIC.

16. The wireless device of claim 14, wherein the distributed inductor is provided on the conductive path and is external to the main PMIC. 17 . The wireless device of claim 14 , wherein the distributed inductor is further configured to isolate the distributed PMIC from the equivalent inductance of the conductive path and the equivalent capacitance of the main PMIC.

18. The wireless device of claim 14, wherein the deQ network comprises a capacitor, a resistor, and a switch coupled in series between the auxiliary voltage output and ground, the deQ network being activated when the switch is closed and being deactivated when the switch is open.

19. The wireless device of claim 14, wherein the master PMIC comprises: a switcher circuit coupled to the auxiliary voltage output and comprising: a multi-level charge pump MCP configured to generate a low frequency voltage based on the duty cycle signal; and a power inductor configured to induce the low frequency current at the auxiliary voltage output based on the low frequency voltage; and A pulse width modulation (PWM) modulator is coupled to the MCP and is configured to generate the duty cycle signal based on a PWM target voltage.

20. The wireless device of claim 12, wherein the deQ circuit is further configured to reduce a peak voltage seen by the master PMIC, thereby protecting the master PMIC from exceeding an intrinsically safe operating region.

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