Method and device for generating power ground network of chip, equipment and medium

Abstract

The embodiment of the invention provides a method, a device and equipment for generating a power ground network of a chip and a medium. The method comprises the following steps: acquiring a process file and a standard cell library; the process file comprises design rules of elements in the power ground network; the standard cell library comprises a design rule of a standard cell area in the power ground network; determining a target power ground strategy and configuration parameters according to the process file and the standard cell library; generating a power ground network of the standard unit region, a power ground network of the memory and a power ground network of the custom module according to the power ground strategy and the configuration parameters; and generating the power ground network of the chip according to the power ground network of the standard unit area, the power ground network of the memory and the power ground network of the custom module. Therefore, when the power supply ground network is generated, the condition of wrong configuration is effectively avoided, the iteration efficiency of back-end layout and wiring is effectively improved, and the quality of the chip power supply is ensured.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a method for generating a power ground network of a chip, a device for generating a power ground network of a chip, an electronic device and a computer-readable storage medium. Background Art

[0002] With the development of computer technology, chips have become a widespread and indispensable component. In the design of the digital back-end of the chip, a hierarchical design method is often used, that is, the design of each module and the top layer in the chip is divided according to the function. During the design, in order to reduce the area cost of the chip, the layout of each module and the top layer needs to be adjusted continuously. After each layout adjustment, the power ground network needs to be regenerated and the winding evaluation needs to be performed. During the evaluation, it is necessary to adjust the layout and reconfigure the relevant parameters to generate the power ground network. This method is difficult to avoid incorrect configuration, which affects the iteration efficiency of the back-end layout and routing and the quality of the chip power supply. Summary of the invention

[0003] In view of the above problems, embodiments of the present invention are proposed to provide a method for generating a power ground network of a chip, a device for generating a power ground network of a chip, an electronic device and a computer-readable storage medium that overcome the above problems or at least partially solve the above problems.

[0004] In order to solve the above problems, an embodiment of the present invention discloses a method for generating a power ground network of a chip, wherein the chip comprises: a standard cell area, a memory and a custom module, and the method comprises:

[0005] Acquire a process file and a standard cell library; the process file includes design rules for components in a power ground network; the standard cell library includes design rules for standard cell regions in the power ground network;

[0006] Determining a target power supply strategy and configuration parameters according to the process file and the standard cell library;

[0007] Generate a power ground network of the standard cell area, a power ground network of the memory, and a power ground network of the custom module according to the power ground strategy and configuration parameters;

[0008] A power ground network of the chip is generated according to the power ground network of the standard cell area, the power ground network of the memory and the power ground network of the custom module.

[0009] Optionally, determining a power supply strategy and configuration parameters according to the process file and the standard cell library includes:

[0010] Determining keywords in design rules for components in the power ground network and design rules for standard cell regions in the power ground network;

[0011] Determining a plurality of power supply strategies from a preset power supply strategy set according to the keyword;

[0012] Determining a target power supply strategy from the plurality of power supply strategies;

[0013] Acquire configuration parameters corresponding to the target power supply strategy.

[0014] Optionally, generating the power ground network of the standard cell area, the power ground network of the memory, and the power ground network of the custom module according to the power ground strategy and configuration parameters includes:

[0015] Obtain a circuit netlist, a constraint file, and a layout file; the circuit netlist is a file of the connection relationship between the components in the power ground network; the constraint file is a file of the design parameters of the power ground network; the layout file is a file of the position layout of the components in the power ground network;

[0016] Assigning values ​​to the parameters in the process file according to the configuration parameters to obtain the process file after the values ​​are assigned;

[0017] A power ground network of a standard cell area, a power ground network of a memory and a power ground network of a custom module are generated according to the circuit netlist, the constraint file, the layout file and the assigned process file.

[0018] Optionally, the generating the power ground network of the chip according to the power ground network of the standard cell area, the power ground network of the memory and the power ground network of the custom module further comprises:

[0019] Performing layout and routing on the power ground network of the chip;

[0020] After the layout and routing is completed, a voltage reduction analysis and a design rule check are performed on the power ground network after the layout and routing to obtain a check result;

[0021] According to the inspection result, a target power ground network is determined, and the target power ground network is output in a preset format.

[0022] Optionally, determining the target power ground network to be output in a preset format according to the inspection result includes:

[0023] When the inspection result meets a preset condition, determining the power ground network of the chip as a target power ground network, and outputting the target power ground network in a preset format;

[0024] When the inspection result does not meet the preset conditions, adjusting the parameters in the process file;

[0025] The target power ground network is determined according to the circuit netlist, the constraint file, the layout file and the adjusted process file.

[0026] Optionally, generating a power ground network of a standard cell area, a power ground network of a memory, and a power ground network of a custom module according to the circuit netlist, the constraint file, the layout file, and the assigned process file includes:

[0027] Determine a plurality of horizontal routing metal parameters and a plurality of vertical routing metal parameters according to the circuit netlist, the constraint file, the layout file and the assigned process file;

[0028] A power ground network of a standard cell region, a power ground network of a memory, and a power ground network of a custom module are generated according to the plurality of lateral routing metal parameters and the plurality of vertical routing metal parameters.

[0029] Optionally, generating a power ground network of a standard cell area, a power ground network of a memory, and a power ground network of a custom module according to the plurality of lateral routing metal parameters and the plurality of vertical routing metal parameters includes:

[0030] Determine, from the plurality of lateral routing metal parameters and the plurality of vertical routing metal parameters, lateral routing metal parameters and vertical routing metal parameters that match the standard cell area, lateral routing metal parameters and vertical routing metal parameters that match the memory, and lateral routing metal parameters and vertical routing metal parameters that match the custom module;

[0031] Generating a power ground network of the standard cell area according to the matching of the lateral routing metal parameters and the vertical routing metal parameters of the standard cell area;

[0032] Generating a power ground network of the memory according to the matching of the horizontal routing metal parameters and the vertical routing metal parameters of the memory;

[0033] A power ground network of the custom module is generated according to the horizontal routing metal parameters and the vertical routing metal parameters that match the custom module.

[0034] Optionally, generating the power ground network of the chip according to the power ground network of the standard cell area, the power ground network of the memory and the power ground network of the custom module includes:

[0035] Determining a vertical routing metal parameter of a top layer from the plurality of vertical routing metal parameters;

[0036] The power ground network of the chip is generated according to the vertical routing metal parameters of the top layer, the power ground network of the standard cell area, the power ground network of the memory and the power ground network of the custom module.

[0037] The embodiment of the present invention further discloses a device for generating a power ground network of a chip, wherein the chip comprises: a standard cell area, a memory and a custom module, and the device comprises:

[0038] An acquisition module, used to acquire a process file and a standard cell library; the process file includes design rules for components in a power ground network; the standard cell library includes design rules for a standard cell area in the power ground network;

[0039] A determination module, used to determine a target power supply strategy and configuration parameters according to the process file and the standard cell library;

[0040] A first generating module, configured to generate a power ground network of the standard cell area, a power ground network of the memory, and a power ground network of the custom module according to the power ground strategy and configuration parameters;

[0041] The second generating module is used to generate a power ground network of the chip according to the power ground network of the standard cell area, the power ground network of the memory and the power ground network of the custom module.

[0042] Optionally, the determining module includes:

[0043] A first determination submodule, used to determine keywords in the design rules of the components in the power ground network and the design rules of the standard cell area in the power ground network;

[0044] A second determination submodule, configured to determine a plurality of power supply strategies from a preset power supply strategy set according to the keyword;

[0045] A third determination submodule, configured to determine a target power supply strategy from the plurality of power supply strategies;

[0046] The first acquisition submodule is used to acquire configuration parameters corresponding to the target power supply strategy.

[0047] Optionally, the first generating module includes:

[0048] The second acquisition submodule is used to acquire a circuit netlist, a constraint file and a layout file; the circuit netlist is a file of the connection relationship between the components in the power ground network; the constraint file is a file of the design parameters of the power ground network; the layout file is a file of the position layout of the components in the power ground network;

[0049] An assignment submodule, used for assigning values ​​to the parameters in the process file according to the configuration parameters to obtain the process file after the assignment;

[0050] The first generation submodule is used to generate a power ground network of a standard cell area, a power ground network of a memory and a power ground network of a custom module according to the circuit netlist, the constraint file, the layout file and the assigned process file.

[0051] Optionally, the device further comprises:

[0052] A wiring module, used for laying out and wiring the power ground network of the chip;

[0053] An inspection module, used for performing voltage reduction analysis and design rule inspection on the power ground network after layout and routing to obtain inspection results after the layout and routing is completed;

[0054] The output module is used to determine the target power ground network according to the inspection result, and output the target power ground network in a preset format.

[0055] Optionally, the output module includes:

[0056] A first output submodule, configured to determine the power ground network of the chip as a target power ground network when the inspection result meets a preset condition, and output the target power ground network in a preset format;

[0057] An adjustment submodule, used for adjusting the parameters in the process file when the inspection result does not meet the preset conditions;

[0058] The fourth determination submodule is used to determine the target power ground network according to the circuit netlist, the constraint file, the layout file and the adjusted process file.

[0059] Optionally, the first generating submodule includes:

[0060] A determination unit, configured to determine a plurality of horizontal routing metal parameters and a plurality of vertical routing metal parameters according to the circuit netlist, the constraint file, the layout file, and the assigned process file;

[0061] A generating unit is used to generate a power ground network of a standard cell area, a power ground network of a memory, and a power ground network of a custom module according to the plurality of horizontal routing metal parameters and the plurality of vertical routing metal parameters.

[0062] Optionally, the generating unit includes:

[0063] A determination subunit, used to determine, from the plurality of horizontal routing metal parameters and the plurality of vertical routing metal parameters, horizontal routing metal parameters and vertical routing metal parameters that match the standard cell area, horizontal routing metal parameters and vertical routing metal parameters that match the memory, and horizontal routing metal parameters and vertical routing metal parameters that match the custom module;

[0064] A first generating subunit, configured to generate a power ground network of a standard cell region according to the lateral routing metal parameters and the vertical routing metal parameters matching the standard cell region;

[0065] A second generation subunit, configured to generate a power ground network of the memory according to the matching horizontal wiring metal parameters and vertical wiring metal parameters of the memory;

[0066] The third generating subunit is used to generate a power ground network of the custom module according to the horizontal routing metal parameters and the vertical routing metal parameters that match the custom module.

[0067] Optionally, the second generating module includes:

[0068] A fifth determination submodule, configured to determine the vertical routing metal parameters of the top layer from the plurality of vertical routing metal parameters;

[0069] The second generation submodule is used to generate the power ground network of the chip according to the vertical routing metal parameters of the top layer, the power ground network of the standard cell area, the power ground network of the memory and the power ground network of the custom module.

[0070] The present invention also discloses an electronic device, including a memory, a processor and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps of the method for generating a power ground network of a chip as described above are implemented.

[0071] The present invention also discloses a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the method for generating a power ground network of a chip as described above are implemented.

[0072] The embodiments of the present invention include the following advantages:

[0073] In an embodiment of the present invention, a process file and a standard cell library are first obtained, wherein the process file includes design rules for components in a power ground network, and the standard cell library includes design rules for standard cell regions in the power ground network. Then, according to the process file and the standard cell library, a target power ground strategy and configuration parameters are determined. Then, according to the power ground strategy and configuration parameters, a power ground network of the standard cell region, a power ground network of a memory, and a power ground network of a custom module are generated. Finally, according to the power ground network of the standard cell region, the power ground network of the memory, and the power ground network of the custom module, a power ground network of a chip is generated. Thus, after the target power ground strategy and configuration parameters are determined according to the process file and the standard cell library, the power ground network of the chip is automatically generated, which can effectively avoid the occurrence of incorrect configuration when generating the power ground network, effectively improve the iteration efficiency of back-end layout and routing, and ensure the quality of chip power supply. BRIEF DESCRIPTION OF THE DRAWINGS

[0074] Figure 1 It is a flowchart of the steps of a method for generating a power ground network of a chip provided by an embodiment of the present invention;

[0075] Figure 2 is a flow chart of steps for determining a target power supply strategy provided by an embodiment of the present invention;

[0076] Figure 3 is a structural block diagram of a standard cell area provided by an embodiment of the present invention;

[0077] Figure 4 is a schematic diagram of a power ground network of a standard cell area provided by an embodiment of the present invention;

[0078] Figure 5 is a structural block diagram of a single storage area in a memory provided by an embodiment of the present invention;

[0079] Figure 6 is a schematic diagram of a power ground network of a memory provided by an embodiment of the present invention;

[0080] Figure 7 It is a structural block diagram of a single custom module area in a custom module provided by an embodiment of the present invention;

[0081] Figure 8 is a schematic diagram of a power ground network of a custom module provided by an embodiment of the present invention;

[0082] Fig. 9 is a layout schematic diagram in a layout file provided by an embodiment of the present invention;

[0083] Fig.10 is a schematic diagram of a top-layer metal power ground network provided by an embodiment of the present invention;

[0084] Fig.11 It is a structural block diagram of a device for generating a power ground network of a chip provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0085] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0086] In the related art, it is difficult to avoid the situation of wrong configuration in the way of generating power ground network, thereby affecting the iteration efficiency of back-end layout and routing and the quality of chip power supply. In order to solve the above technical problems, the present invention provides a method for generating power ground network of a chip, firstly obtains process files and standard cell libraries, wherein the process files include design rules of components in the power ground network, and the standard cell library includes design rules of standard cell areas in the power ground network, and then determines the target power ground strategy and configuration parameters according to the process files and the standard cell library, and then generates the power ground network of the standard cell area, the power ground network of the memory and the power ground network of the custom module according to the power ground strategy and configuration parameters, and finally generates the power ground network of the chip according to the power ground network of the standard cell area, the power ground network of the memory and the power ground network of the custom module, so that the power ground network of the chip can be automatically generated after the target power ground strategy and configuration parameters are determined according to the process files and the standard cell library, which can effectively avoid the situation of wrong configuration when generating the power ground network, effectively improve the iteration efficiency of back-end layout and routing, and ensure the quality of chip power supply.

[0087] Reference Figure 1 , shows a flow chart of steps of a method for generating a power ground network of a chip provided by an embodiment of the present invention, wherein the chip comprises: a standard cell area, a memory and a custom module, and the method may specifically comprise the following steps:

[0088] Step 101, obtaining a process file and a standard cell library; the process file includes design rules for components in a power ground network; the standard cell library includes design rules for standard cell regions in the power ground network.

[0089] In an embodiment of the present invention, a chip may include: a standard cell area, a memory, and a custom module. The standard cell is a basic logic circuit module that is pre-designed and optimized. The design and layout of the standard cell area are crucial to ensuring the normal operation and optimization of the chip. The memory is also a storage module, which is mainly used to store data. Custom modules are some small digital functional modules built with digital standard cells, generally div clock division modules, mux clock selection modules, delaychain timing delay control modules, etc. When generating the power ground network of the chip, the process file and the standard cell library can be obtained first, wherein the process file may include the design rules of the components in the power ground network, and the standard cell library may include the design rules of the standard cell area in the power ground network.

[0090] For example, sc9mc_logic0040ll_base_rvt_c50_*.lib is a standard cell library with a height of 9 TRACK made for the SMIC40 process, indicating that the standard cell is 9 TRACK high, and logic0040ll represents a 40nm process; sc12mc_logic0040ll_base_rvt_c50_*.lib is a standard cell library with a height of 12 TRACK made for the SMIC40 process, indicating that the standard cell is 12 TRACK high, and logic0040ll represents a 40nm process. indicates 40nm process; sc9mc_cln40ulp_base_svtulp_c40_*.lib is a standard cell library with a height of 9TRACK made for TSMC40 process, indicating that the standard cell is 9TRACK height, cln40ulp indicates 40nm process; hhg90_tlscl10cnmv0_base_*.lib is a standard cell library with a height of 10TRACK designed for 90nm process, indicating 90nm process, tlscl10cnmv0 indicates the standard cell height of 10TRACK, etc.

[0091] In the present invention, there may be parameters in the process file, and the parameters may be technical variable parameters, and the variable parameters may be used to determine which process the process file uses, how many winding metal layers are used, and the type and / or thickness of the top metal layer, and other information. For example, the variable parameter in the process file is StarRC_40LGLL_1P7M_6Ic_1TMc_ALPA1_CMAX, which may determine that the process file uses a 40nm process, uses 7 layers of metal winding, and the top metal layer is metal aluminum. For another example, the variable parameter in the process file is HHW_FSA90E1L07_6M_MTT14K_CWORST, which may determine that the process file uses a 90nm process, uses 6 layers of metal winding, and the top metal layer is 14K thick metal copper.

[0092] Step 102: Determine a target power supply strategy and configuration parameters according to the process file and the standard cell library.

[0093] In the embodiment of the present invention, after the process file and the standard cell library are acquired, the target power supply strategy and configuration parameters can be determined according to the process file and the standard cell library.

[0094] In one embodiment, a power ground strategy and configuration parameters are determined based on a process file and a standard cell library, including: determining keywords in design rules for components in a power ground network and design rules for standard cell regions in the power ground network; determining multiple power ground strategies from a preset power ground strategy set based on the keywords; determining a target power ground strategy from the multiple power ground strategies; and obtaining configuration parameters corresponding to the target power ground strategy.

[0095] Specifically, Figure 2 FIG. 1 is a flowchart showing a strategy for determining a target power supply provided by an embodiment of the present invention. Figure 2 The sc12mc_logic0040ll_base_rvt_c50_*.lib in the file belongs to the standard cell library, and StarRC_40LGLL_1P7M_6Ic_1TMc_ALPA1_CMAX belongs to the process file. You can use the grep command in the tcl language to determine the corresponding keywords in the process file and the standard cell library, and then determine multiple power ground strategies from the preset power ground strategy set based on the keywords. Figure 2 Strategies 1 to 8 in the above all belong to multiple determined power ground strategies. In the present invention, the preset power ground strategy set is a set that has been taped out and verified by a large number of actual projects, and has fewer problems with voltage drop analysis and physical DRC (design_rule_check). Then, the strategy is selected by selecting the command to select the applicable target power ground strategy. For example, taking the SMIC40nm process and the 9Track standard cell library as an example, a total of 7 layers of metal winding resources of 1p7m are used. After matching and selection, it is determined to adopt power ground strategy 1: smic40ll_arm_9t_1p7. Then the configuration parameters corresponding to power ground strategy 1 can be obtained.

[0096] Step 103 : generating a power ground network of the standard cell area, a power ground network of the memory, and a power ground network of the custom module according to the power ground strategy and configuration parameters.

[0097] In the embodiment of the present invention, after the target power ground strategy and configuration parameters are determined, the power ground network of the standard cell area, the power ground network of the memory and the power ground network of the custom module can be generated respectively according to the power ground strategy and configuration parameters.

[0098] In one embodiment, a power ground network of a standard cell area, a power ground network of a memory, and a power ground network of a custom module are generated according to a power ground strategy and configuration parameters, including: obtaining a circuit netlist, a constraint file, and a layout file; the circuit netlist is a file of connection relationships between components in the power ground network; the constraint file is a file of design parameters of the power ground network; the layout file is a file of position layout of components in the source ground network; according to the configuration parameters, parameters in a process file are assigned to obtain an assigned process file; according to the circuit netlist, the constraint file, the layout file, and the assigned process file, a power ground network of a standard cell area, a power ground network of a memory, and a power ground network of a custom module are generated.

[0099] Specifically, after the front-end designer completes the code design and performs the synthesis process, a circuit netlist will be provided to the back-end designer. The circuit netlist is a file of the connection relationship between the components in the power ground network. The back-end designer and the synthesis process personnel need to communicate in advance about which library files to use for the circuit netlist, and obtain the constraint file corresponding to the circuit netlist. The constraint file is a file of the design parameters of the power ground network. The layout file can also be obtained from the layout designer. The layout file is a file of the position layout of each component in the source ground network. Then the configuration parameters are obtained, and the parameters in the process file are assigned to obtain the assigned process file. Finally, according to the circuit netlist, constraint file, layout file and assigned process file, the power ground network of the standard cell area, the power ground network of the memory and the power ground network of the custom module are generated. Therefore, there is no need to spend extra time to debug the parameters, which significantly improves the iteration efficiency of the entire back-end design process, and avoids the problem of power ground strategy errors or parameter configuration errors when junior engineers undertake new project modules.

[0100] In one embodiment, a power ground network of a standard cell area, a power ground network of a memory, and a power ground network of a custom module are generated according to a circuit netlist, a constraint file, a layout file, and a process file after assignment, including: determining a plurality of horizontal routing metal parameters and a plurality of vertical routing metal parameters according to the circuit netlist, the constraint file, the layout file, and the process file after assignment; generating a power ground network of a standard cell area, a power ground network of a memory, and a power ground network of a custom module according to the plurality of horizontal routing metal parameters and the plurality of vertical routing metal parameters.

[0101] For example: according to the circuit netlist, constraint file, layout file and assigned process file, determine that the multiple horizontal routing metals are: M1, M2, M4, M6, and the multiple vertical routing metals are M3, M5, M7, with a total of seven layers of winding metal, and determine the corresponding parameters of the multiple horizontal routing metals and the parameters of the multiple vertical routing metals. Then, based on the multiple horizontal routing metal parameters and the multiple vertical routing metal parameters, generate the power ground network of the standard cell area, the power ground network of the memory, and the power ground network of the custom module.

[0102] In one embodiment, generating a power ground network of a standard cell area, a power ground network of a memory, and a power ground network of a custom module according to a plurality of lateral routing metal parameters and a plurality of vertical routing metal parameters may include: determining, from the plurality of lateral routing metal parameters and the plurality of vertical routing metal parameters, the lateral routing metal parameters and the vertical routing metal parameters that match the standard cell area, the lateral routing metal parameters and the vertical routing metal parameters that match the memory, and the lateral routing metal parameters and the vertical routing metal parameters that match the custom module; generating a power ground network of the standard cell area according to the lateral routing metal parameters and the vertical routing metal parameters that match the standard cell area; generating a power ground network of the memory according to the lateral routing metal parameters and the vertical routing metal parameters that match the memory; generating a power ground network of the custom module according to the lateral routing metal parameters and the vertical routing metal parameters that match the custom module.

[0103] Specifically, Figure 3 , which shows a structural block diagram of a standard cell region provided by an embodiment of the present invention, Figure 3Cell* is the basic cell in the standard cell library. It is a module with basic logic functions and physical characteristics. It is the basic building block of digital integrated circuit design and is used to implement various logic functions, such as (AND gate, OR gate, NOT gate, trigger, etc.). These cells can be reused to build complex digital circuits. Std_cell_rail is the standard cell power rail, which provides power and ground for standard cells. These power rails are usually arranged along the top and bottom of the standard cell row to ensure that each cell can obtain a stable power supply, thereby ensuring the normal operation of the circuit. This design can ensure a stable power supply, reduce noise and voltage drop, and improve the reliability and performance of the circuit, which is crucial in the back-end physical design. Standard cells are a set of basic logic function modules with fixed layout and physical characteristics, which are used to implement various logic functions. These modules can be used multiple times to build complex digital circuits. They play an important role in improving design efficiency, ensuring reliability, and supporting automated design. power_port is the power port, and ground_port is the ground port. Since the lateral track power ground port of the standard cell uses M2 metal, the M3 and M6 metal layers are used to form the standard cell area power ground network and connected through the power ground through hole. Figure 4 As shown, a schematic diagram of a power ground network of a standard unit area provided by an embodiment of the present invention is shown, Power is the power supply, Ground is the ground line, VIA23, VIA34, VIA45, VIA56, and VIA67 represent through holes between different metal layers.

[0104] like Figure 5 As shown, a structural block diagram of a single storage area in a memory provided by an embodiment of the present invention is shown. SARM* is a single storage area in the memory. The power ground port (power_port, ground_port) in the memory uses M4 metal. In the layout file, the power ground port M4 is kept horizontally placed, so the power network on the memory is composed of two layers of metal, M5 and M6, and connected through power ground vias. Figure 6 , which is a schematic diagram of a power ground network of a memory provided by an embodiment of the present invention.

[0105] like Figure 7As shown, a structural block diagram of a single custom module area in a custom module provided by an embodiment of the present invention is shown. Custom_blcok* is a single custom module area in the custom module. The power ground port (power_port, ground_port) of the custom module uses M3 metal. In the layout file, the power ground port M3 is kept vertically placed, so a layer of M6 metal is used to form the power ground network on the custom module, and connected through the power ground through hole. Figure 8 , which is a schematic diagram of a power ground network of a custom module provided by an embodiment of the present invention.

[0106] In the present invention, according to the configuration parameters, when assigning values ​​to the parameters in the process file, for example, the parameters in the process file are M3 width, M3 power ground group spacing, M5 width, M5 power ground group spacing, M6 width, M6 power ground group spacing, and the type and size of metal through holes such as VIA23, VIA34, VIA45, VIA56, and VIA67, when assigning values, corresponding values ​​can be assigned to different parameters.

[0107] In one embodiment, a power ground network of a chip is generated based on a power ground network of a standard cell area, a power ground network of a memory, and a power ground network of a custom module, including: determining a vertical routing metal parameter of a top layer from a plurality of vertical routing metal parameters; generating a power ground network of the chip based on the vertical routing metal parameter of the top layer, the power ground network of the standard cell area, the power ground network of the memory, and the power ground network of the custom module.

[0108] Specifically, the power ground networks of the standard cell area, memory, and custom module all use the M6 ​​metal layer, and the power ground type is the same, so the M6 ​​metal layer is usually planned and distributed uniformly, so that the power ground networks of the cell area, memory, and custom module can be linked as a whole. After the power ground networks of the cell area, memory, and custom module are generated, you can see that the M6 ​​metal layer connects the three power ground networks, and the other power metal layers M3 and M5 are not connected. In order to meet higher voltage requirements, it is also necessary to lay a layer of M7 power ground metal layer vertically and connect it to M6 through the power ground through hole. The M7 metal layer belongs to the top metal layer and is also a thick metal, which is wider and thicker than the bottom metal (M1-M6). Fig. 9 As shown, a layout schematic diagram in a layout file provided by an embodiment of the present invention is shown, the Standard_cells area is a standard cell area, the Sram area is a memory area, the Custom_blcok area is a custom module area, and the Analog area is an analog area. Fig.10As shown, a schematic diagram of a top-layer metal power ground network provided by an embodiment of the present invention is shown. After a layer of vertical M7 power ground is laid and holes are punched, the power ground metals M6 and M7 form a stronger power ground network, ensuring the voltage requirements of the entire chip or module. After all power ground metal layers and power ground through holes are generated, the power ground network of the chip can be obtained.

[0109] In an embodiment of the present invention, a power ground network of a chip is generated according to a power ground network of a standard cell area, a power ground network of a memory and a power ground network of a custom module, and then the method further includes: performing layout and routing on the power ground network of the chip; after the layout and routing is completed, performing a voltage reduction analysis and a design rule check on the power ground network after the layout and routing to obtain a check result; and determining a target power ground network according to the check result, and outputting the target power ground network in a preset format.

[0110] Specifically, after the target power-ground network is generated, a fast layout and routing process can be performed in the EDA tool. After the layout and routing is completed, the power-ground network after layout and routing can be subjected to voltage reduction analysis and design planning detection. Finally, the target power-ground network is determined through the detection results, and the target power-ground network is output in the def format for subsequent processes. When the back-end design needs to be iteratively optimized due to timing issues, the def file can be directly called without regenerating the target power-ground network.

[0111] In one embodiment, based on the inspection result, a target power ground network to be output in a preset format is determined, including: when the inspection result meets the preset condition, the power ground network of the chip is determined as the target power ground network, and the target power ground network is output in a preset format; when the inspection result does not meet the preset condition, the parameters in the process file are adjusted; and the target power ground network is determined based on the circuit netlist, the constraint file, the layout file and the adjusted process file.

[0112] Specifically, after obtaining the test results, it can be determined whether the test results meet the preset conditions, for example, whether the test results are passed. If passed, the power ground network of the chip can be determined as the target power ground network, and the target power ground network can be output in a preset format. When the test result is not passed, the parameters in the process file can be manually adjusted, and then the power ground network of the standard cell area, the power ground network of the memory, and the power ground network of the custom module are generated according to the circuit netlist, constraint file, layout file and adjusted process file. Then, based on the power ground network of the standard cell area, the power ground network of the memory, and the power ground network of the custom module, the power ground network of the chip is generated.

[0113] In an embodiment of the present invention, a process file and a standard cell library are obtained; the process file includes design rules for components in a power ground network; the standard cell library includes design rules for standard cell regions in the power ground network; according to the process file and the standard cell library, a target power ground strategy and configuration parameters are determined; according to the power ground strategy and configuration parameters, a power ground network of the standard cell region, a power ground network of a memory, and a power ground network of a custom module are generated; according to the power ground network of the standard cell region, the power ground network of the memory, and the power ground network of a custom module, a power ground network of a chip is generated. Thus, after the target power ground strategy and configuration parameters are determined according to the process file and the standard cell library, the power ground network of the chip is automatically generated, which can effectively avoid the occurrence of incorrect configuration when generating the power ground network, effectively improve the iteration efficiency of the back-end layout and routing, and ensure the quality of the chip power supply.

[0114] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0115] Reference Fig.11 , shows a structural block diagram of a device for generating a power ground network of a chip provided by an embodiment of the present invention, wherein the chip includes: a standard cell area, a memory and a custom module, and specifically may include the following modules:

[0116] The acquisition module 1101 is used to acquire a process file and a standard cell library; the process file includes design rules for components in a power ground network; the standard cell library includes design rules for standard cell regions in the power ground network;

[0117] A determination module 1102, configured to determine a target power supply strategy and configuration parameters according to the process file and the standard cell library;

[0118] A first generating module 1103, configured to generate a power ground network of the standard cell area, a power ground network of the memory, and a power ground network of the custom module according to the power ground strategy and configuration parameters;

[0119] The second generating module 1104 is used to generate a power ground network of the chip according to the power ground network of the standard cell area, the power ground network of the memory and the power ground network of the custom module.

[0120] In one embodiment, the determining module 1102 includes:

[0121] A first determination submodule, used to determine keywords in the design rules of the components in the power ground network and the design rules of the standard cell area in the power ground network;

[0122] A second determination submodule, configured to determine a plurality of power supply strategies from a preset power supply strategy set according to the keyword;

[0123] A third determination submodule, configured to determine a target power supply strategy from the plurality of power supply strategies;

[0124] The first acquisition submodule is used to acquire configuration parameters corresponding to the target power supply strategy.

[0125] In one embodiment, the first generating module 1103 includes:

[0126] The second acquisition submodule is used to acquire a circuit netlist, a constraint file and a layout file; the circuit netlist is a file of the connection relationship between the components in the power ground network; the constraint file is a file of the design parameters of the power ground network; the layout file is a file of the position layout of the components in the power ground network;

[0127] An assignment submodule, used for assigning values ​​to the parameters in the process file according to the configuration parameters to obtain the process file after the assignment;

[0128] The first generation submodule is used to generate a power ground network of a standard cell area, a power ground network of a memory and a power ground network of a custom module according to the circuit netlist, the constraint file, the layout file and the assigned process file.

[0129] In one embodiment, the device further comprises:

[0130] A wiring module, used for laying out and wiring the power ground network of the chip;

[0131] An inspection module, used for performing voltage reduction analysis and design rule inspection on the power ground network after layout and routing to obtain inspection results after the layout and routing is completed;

[0132] The output module is used to determine the target power ground network according to the inspection result, and output the target power ground network in a preset format.

[0133] In one embodiment, the output module includes:

[0134] A first output submodule, configured to determine the power ground network of the chip as a target power ground network when the inspection result meets a preset condition, and output the target power ground network in a preset format;

[0135] An adjustment submodule, used for adjusting the parameters in the process file when the inspection result does not meet the preset conditions;

[0136] The fourth determination submodule is used to determine the target power ground network according to the circuit netlist, the constraint file, the layout file and the adjusted process file.

[0137] In one embodiment, the first generating submodule includes:

[0138] A determination unit, configured to determine a plurality of horizontal routing metal parameters and a plurality of vertical routing metal parameters according to the circuit netlist, the constraint file, the layout file, and the assigned process file;

[0139] A generating unit is used to generate a power ground network of a standard cell area, a power ground network of a memory, and a power ground network of a custom module according to the plurality of horizontal routing metal parameters and the plurality of vertical routing metal parameters.

[0140] In one embodiment, the generating unit comprises:

[0141] A determination subunit, used to determine, from the plurality of horizontal routing metal parameters and the plurality of vertical routing metal parameters, horizontal routing metal parameters and vertical routing metal parameters that match the standard cell area, horizontal routing metal parameters and vertical routing metal parameters that match the memory, and horizontal routing metal parameters and vertical routing metal parameters that match the custom module;

[0142] A first generating subunit, configured to generate a power ground network of a standard cell region according to the lateral routing metal parameters and the vertical routing metal parameters matching the standard cell region;

[0143] A second generation subunit, configured to generate a power ground network of the memory according to the matching horizontal routing metal parameters and vertical routing metal parameters of the memory;

[0144] The third generating subunit is used to generate a power ground network of the custom module according to the horizontal routing metal parameters and the vertical routing metal parameters that match the custom module.

[0145] In one embodiment, the second generating module 1104 includes:

[0146] A fifth determination submodule, configured to determine the vertical routing metal parameters of the top layer from the plurality of vertical routing metal parameters;

[0147] The second generation submodule is used to generate the power ground network of the chip according to the vertical routing metal parameters of the top layer, the power ground network of the standard cell area, the power ground network of the memory and the power ground network of the custom module.

[0148] In an embodiment of the present invention, an acquisition module is used to acquire a process file and a standard cell library; the process file includes design rules for components in a power ground network; the standard cell library includes design rules for standard cell regions in the power ground network; a determination module is used to determine a target power ground strategy and configuration parameters based on the process file and the standard cell library; a first generation module is used to generate a power ground network for a standard cell region, a power ground network for a memory, and a power ground network for a custom module based on the power ground strategy and configuration parameters; a second generation module is used to generate a power ground network for a chip based on the power ground network for a standard cell region, a power ground network for a memory, and a power ground network for a custom module. Thus, after determining the target power ground strategy and configuration parameters based on the process file and the standard cell library, the power ground network for the chip can be automatically generated, which can effectively avoid the occurrence of incorrect configuration when generating the power ground network, effectively improve the iteration efficiency of the back-end layout and routing, and ensure the quality of the chip power supply.

[0149] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0150] An embodiment of the present invention further provides an electronic device, including:

[0151] The invention comprises a processor, a memory and a computer program stored in the memory and capable of running on the processor. When the computer program is executed by the processor, each process of the embodiment of the method for generating a power ground network of the above chip is implemented, and the same technical effect can be achieved. To avoid repetition, it will not be described here.

[0152] An embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, each process of the embodiment of the method for generating a power ground network of the above chip is implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0153] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0154] It will be appreciated by those skilled in the art that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0155] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0156] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0157] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0158] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0159] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0160] The above describes in detail a method for generating a power ground network of a chip, a device for generating a power ground network of a chip, an electronic device and a computer-readable storage medium provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A method for generating a power ground network of a chip, characterized in that: The chip comprises: a standard cell area, a memory and a custom module, and the method comprises: Acquire a process file and a standard cell library; the process file includes design rules for components in a power ground network; the standard cell library includes design rules for standard cell regions in the power ground network; Determining a target power supply strategy and configuration parameters according to the process file and the standard cell library; Generate a power ground network of the standard cell area, a power ground network of the memory, and a power ground network of the custom module according to the power ground strategy and configuration parameters; A power ground network of the chip is generated according to the power ground network of the standard cell area, the power ground network of the memory and the power ground network of the custom module.

2. The method for generating a power ground network of a chip according to claim 1, characterized in that: Determining the power supply strategy and configuration parameters according to the process file and the standard cell library includes: Determining keywords in design rules for components in the power ground network and design rules for standard cell regions in the power ground network; Determining a plurality of power supply strategies from a preset power supply strategy set according to the keyword; Determining a target power supply strategy from the plurality of power supply strategies; Acquire configuration parameters corresponding to the target power supply strategy.

3. The method for generating a power ground network of a chip according to claim 1, characterized in that: The step of generating the power ground network of the standard cell area, the power ground network of the memory, and the power ground network of the custom module according to the power ground strategy and configuration parameters includes: Obtain a circuit netlist, a constraint file and a layout file; the circuit netlist is a file of the connection relationship between the components in the power ground network; the constraint file is a file of the design parameters of the power ground network; the layout file is a file of the position layout of the components in the power ground network; Assigning values ​​to the parameters in the process file according to the configuration parameters to obtain the process file after the values ​​are assigned; A power ground network of a standard cell area, a power ground network of a memory and a power ground network of a custom module are generated according to the circuit netlist, the constraint file, the layout file and the assigned process file.

4. The method for generating a power ground network of a chip according to claim 3, characterized in that: The power ground network of the chip is generated according to the power ground network of the standard cell area, the power ground network of the memory and the power ground network of the custom module, and then further comprises: Performing layout and routing on the power ground network of the chip; After the layout and routing is completed, a voltage reduction analysis and a design rule check are performed on the power ground network after the layout and routing to obtain a check result; According to the inspection result, a target power ground network is determined, and the target power ground network is output in a preset format.

5. The method for generating a power ground network of a chip according to claim 4, characterized in that: Determining a target power ground network for output in a preset format according to the inspection result includes: When the inspection result meets a preset condition, determining the power ground network of the chip as a target power ground network, and outputting the target power ground network in a preset format; When the inspection result does not meet the preset conditions, adjusting the parameters in the process file; The target power ground network is determined according to the circuit netlist, the constraint file, the layout file and the adjusted process file.

6. The method for generating a power ground network of a chip according to claim 3, characterized in that: The generating of the power ground network of the standard cell area, the power ground network of the memory and the power ground network of the custom module according to the circuit netlist, the constraint file, the layout file and the assigned process file comprises: Determine a plurality of horizontal routing metal parameters and a plurality of vertical routing metal parameters according to the circuit netlist, the constraint file, the layout file and the assigned process file; A power ground network of a standard cell region, a power ground network of a memory, and a power ground network of a custom module are generated according to the plurality of lateral routing metal parameters and the plurality of vertical routing metal parameters.

7. The method for generating a power ground network of a chip according to claim 6, characterized in that: The generating, according to the plurality of lateral routing metal parameters and the plurality of vertical routing metal parameters, a power ground network of a standard cell area, a power ground network of a memory, and a power ground network of a custom module comprises: Determine, from the plurality of lateral routing metal parameters and the plurality of vertical routing metal parameters, lateral routing metal parameters and vertical routing metal parameters that match the standard cell area, lateral routing metal parameters and vertical routing metal parameters that match the memory, and lateral routing metal parameters and vertical routing metal parameters that match the custom module; Generating a power ground network of the standard cell area according to the matching of the lateral routing metal parameters and the vertical routing metal parameters of the standard cell area; Generating a power ground network of the memory according to the matching of the horizontal routing metal parameters and the vertical routing metal parameters of the memory; A power ground network of the custom module is generated according to the horizontal routing metal parameters and the vertical routing metal parameters that match the custom module.

8. The method for generating a power ground network of a chip according to claim 7, characterized in that: The step of generating the power ground network of the chip according to the power ground network of the standard cell area, the power ground network of the memory and the power ground network of the custom module comprises: Determining a vertical routing metal parameter of a top layer from the plurality of vertical routing metal parameters; The power ground network of the chip is generated according to the vertical routing metal parameters of the top layer, the power ground network of the standard cell area, the power ground network of the memory and the power ground network of the custom module.

9. A device for generating a power ground network of a chip, characterized in that: The chip includes: a standard cell area, a memory and a custom module, and the device includes: An acquisition module, used to acquire a process file and a standard cell library; the process file includes design rules for components in a power ground network; the standard cell library includes design rules for a standard cell area in the power ground network; A determination module, used to determine a target power supply strategy and configuration parameters according to the process file and the standard cell library; A first generating module, configured to generate a power ground network of the standard cell area, a power ground network of the memory, and a power ground network of the custom module according to the power ground strategy and configuration parameters; The second generating module is used to generate a power ground network of the chip according to the power ground network of the standard cell area, the power ground network of the memory and the power ground network of the custom module.

10. An electronic device, characterized in that: include: A processor, a memory, and a computer program stored in the memory and capable of running on the processor, wherein when the computer program is executed by the processor, the steps of the method for generating a power ground network of a chip according to any one of claims 1 to 8 are implemented.

11. A computer-readable storage medium, characterized in that: The computer readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method for generating a power ground network of a chip according to any one of claims 1 to 8 are implemented.

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