Novel CMOS / SFQ interface circuit

Abstract

The invention provides a novel CMOS / SFQ interface circuit. The novel CMOS / SFQ interface circuit comprises a mutual inductance interface module and a superconducting combiner, the input end of the mutual inductance interface module is connected with an input current and is used for coupling the input current into a mutual inductance interface circuit to generate a coupling current, and the input current is a direct current square wave; when the current value of the coupling current at the rising edge is increased to meet a first condition along with the direct current square wave, the first output end of the mutual inductance interface module outputs a first SFQ signal, and when the current value of the coupling current at the falling edge is increased to meet a second condition, the second output end of the mutual inductance interface module outputs a second SFQ signal; the second output end of the mutual inductance interface module outputs a second SFQ signal; the first input end of the superconducting combiner is connected with the first output end of the mutual inductance interface module, the second input end of the superconducting combiner is connected with the second output end of the mutual inductance interface module, and the superconducting combiner outputs the first SFQ signal or the second SFQ signal. According to the invention, the working frequency of the SFQ can be improved.

Description

Technical Field

[0001] The invention relates to superconducting technology, in particular to a novel CMOS / SFQ interface circuit. Background Art

[0002] With the rapid development of society, the amount of data that needs to be processed has expanded dramatically, and higher and higher requirements have been placed on the computing power of computers. Superconducting circuits based on Josephson junctions have gradually entered people's field of vision. Superconducting RSFQ devices are mainly realized through superconducting Josephson junctions. Since the switching frequency of superconducting Josephson junctions is only in the order of picoseconds (ps), they can operate at extremely high frequencies. Superconducting single flux quantum (SFQ) circuit technology is considered to be one of the next generation of digital circuit technology alternatives due to its low power consumption and ultra-high speed. This technology has huge advantages in power consumption and heat dissipation, making RSFQ circuits promising to realize large-scale, high-performance and low-power computer systems in the future.

[0003] However, the integration level of the international and domestic superconducting SFQ process is still low, and it is difficult to achieve the development of large-scale computer systems in the short term by relying solely on SFQ devices. Therefore, the SFQ circuit and the mainstream complementary metal oxide semiconductor (CMOS) circuit are integrated together, and the superiority of the SFQ circuit in high-frequency signal processing is used to realize the components with the highest frequency requirements in the system, and the CMOS circuit is used to realize the components with the second lowest frequency requirements in the system. Based on this idea, the design of the interface circuit between the CMOS circuit and the SFQ circuit has become a hot topic in current research.

[0004] One of the major advantages of SFQ circuits is that the operating frequency of circuit devices is high. When SFQ circuits and CMOS circuits are integrated together to realize a computer computing system, the problem of clock synchronization of circuits under two different processes needs to be solved. For the entire system, the clock on the SFQ chip can be directly controlled by an externally controlled FPGA circuit to achieve synchronous clock control with the CMOS circuit; a high-frequency clock can also be generated internally on the SFQ chip, and in this case, the external CMOS circuit can only work with an asynchronous clock.

[0005] As far as synchronous clock control is concerned, the highest frequency at which the SFQ chip can operate depends on the FPGA circuit that generates the clock. The current highest-specification FPGA can achieve a clock frequency of about 10GHz (developed based on the Ultra Scale Kintex series of FPGA boards), which is much lower than the frequency at which the SFQ circuit can easily operate, such as 50GHz.

[0006] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0007] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a novel CMOS / SFQ interface circuit for solving the problem of low operating frequency of the SFQ circuit in the FPGA and SFQ chip integrated circuit system in the prior art.

[0008] To achieve the above-mentioned and other related purposes, the present invention provides a novel CMOS / SFQ interface circuit, including a mutual inductance interface module and a superconducting combiner;

[0009] The input end of the mutual inductance interface module is connected to the input current, and is used to couple the input current to the mutual inductance interface circuit to generate a coupling current, and the input current is a DC square wave; when the coupling current increases with the current value of the DC square wave at the rising edge to meet the first condition, the first output end of the mutual inductance interface module outputs a first SFQ signal, and when the coupling current increases with the current value of the DC square wave at the falling edge to meet the second condition, the second output end of the mutual inductance interface module outputs a second SFQ signal;

[0010] The first input end of the superconducting combiner is connected to the first output end of the mutual inductance interface module, the second input end of the superconducting combiner is connected to the second output end of the mutual inductance interface module, and the superconducting combiner outputs the first SFQ signal or the second SFQ signal.

[0011] Optionally, the mutual inductance interface module includes a self-inductance coil, a SQUID loop, a first JTL and a second JTL;

[0012] The self-inductance coil forms a mutual inductance with the mutual inductance coil in the SQUID loop, and couples the input current connected to the self-inductance coil into the SQUID loop to generate the coupling current;

[0013] One end of the first JTL is connected to the first end of the mutual inductance coil, the other end of the first JTL is connected to the first input end of the superconducting combiner, and the first SFQ signal is output to the superconducting combiner through the first JTL;

[0014] One end of the second JTL is connected to the second end of the mutual inductance coil, the other end of the second JTL is connected to the second input end of the superconducting combiner, and the second SFQ signal is output to the superconducting combiner through the first JTL.

[0015] Optionally, the first end of the mutual inductance coil is connected to a first current source, and the bias current source provides a bias current for the mutual inductance interface module.

[0016] Optionally, the SQUID loop further includes a first Josephson junction and a second Josephson junction;

[0017] The first Josephson junction is connected to the first end of the mutual inductance coil, and when the first condition is met, the first Josephson junction is triggered to generate a first pulse, and the first JTL outputs a first SFQ signal under the action of the first pulse;

[0018] The second Josephson junction is connected to the second end of the mutual inductance coil. When the second condition is met, the second Josephson junction is triggered to generate a second pulse, and the second JTL outputs a second SFQ signal under the action of the second pulse.

[0019] Optionally, the first condition is

[0020] I ou1 +I b >I max1

[0021] In the formula, I ou1 I is the coupling current obtained by mutual inductance after the rising edge of the DC square wave arrives. b is the bias current, I max1 is the critical current of the first Josephson junction J1.

[0022] Optionally, the second condition is

[0023] I ou2 +I b >I max2

[0024] In the formula, I ou2 I is the coupling current obtained by mutual inductance after the falling edge of the DC square wave arrives. b is the bias current, I max2 is the critical current of the second Josephson junction J2.

[0025] Optionally, the superconducting combiner includes a first buffer, a second buffer and an output unit;

[0026] The input end of the first buffer is connected to the first output end OUT1 of the mutual inductance interface module, and is used to buffer the first SFQ signal being transmitted;

[0027] The input end of the second buffer is connected to the second output end OUT2 of the mutual inductance interface module, and is used to buffer the second SFQ signal being transmitted;

[0028] The first buffer and the second buffer have the same output terminal and are connected to the input terminal of the output unit; the output unit outputs the first SFQ signal or the second SFQ signal.

[0029] Optionally, the first buffer includes a Josephson junction JB1, a Josephson junction JB2, an inductor LB2 and an inductor LAB1;

[0030] One end of the inductor LB2 is connected to the Josephson junction JB1, and the other end of the inductor LB2 is connected to one end of the Josephson junction JB2; the other end of the Josephson junction JB2 is connected to one end of the inductor LAB1, and the other end of the inductor LAB1 is the output end of the first buffer.

[0031] Optionally, the second buffer includes a Josephson junction JA1, a Josephson junction JA2, an inductor LA2 and an inductor LAB1;

[0032] One end of the inductor LA2 is connected to the Josephson junction JA1, and the other end of the inductor LA2 is connected to one end of the Josephson junction JA2; the other end of the Josephson junction JA2 is connected to one end of the inductor LAB1, and the other end of the inductor LAB1 is the output end of the second buffer.

[0033] As described above, the novel CMOS / SFQ interface circuit of the present invention has the following beneficial effects:

[0034] A novel CMOS / SFQ interface circuit of the present invention comprises a mutual inductance interface module and a superconducting combiner; an input current (direct current square wave) is mutually inducted by the mutual inductance interface module to obtain a coupling current, and a first SFQ signal and a second SFQ signal are output as the coupling current changes, which correspond to the rising edge and the falling edge of the direct current square wave respectively; specifically, the mutual inductance interface module couples the input current connected to its input end to the mutual inductance interface circuit to generate a coupling current, and when the coupling current increases with the current value of the direct current square wave at the rising edge to meet the first condition, the first output end of the mutual inductance interface module outputs the first SFQ signal; or when the coupling current increases with the current value of the direct current square wave at the falling edge to meet the second condition, the second output end of the mutual inductance interface module outputs the second SFQ signal; the first SFQ signal or the second SFQ signal is output through the superconducting combiner, thereby realizing sampling of the positive and negative edges of the direct current square wave current, and increasing the maximum frequency of SFQ operation by double sampling. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 Shown is a structural schematic diagram of a superconducting DC / SFQ conversion circuit.

[0036] Figure 2A schematic diagram showing simulation results of a superconducting DC / SFQ conversion circuit.

[0037] Figure 3 Shown is a principle structural block diagram of the novel CMOS / SFQ interface circuit of the present invention.

[0038] Figure 4 It is a schematic diagram showing the connection relationship of the mutual inductance interface module in the novel CMOS / SFQ interface circuit in a specific embodiment of the present invention.

[0039] Figure 5 It is a schematic diagram showing the connection relationship of the superconducting combiner in the novel CMOS / SFQ interface circuit in a specific embodiment of the present invention.

[0040] Figure 6 Shown is a schematic diagram of simulation results of a novel CMOS / SFQ interface circuit in a specific embodiment of the present invention. DETAILED DESCRIPTION

[0041] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0042] See also Figure 1-Figure 6 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0043] When synchronous clock control is adopted in the FPGA and SFQ chip integrated circuit system, the highest frequency at which the SFQ circuit can operate is essentially determined by the synchronous clock frequency that can be generated externally. Therefore, it is impossible to achieve a high frequency at which the SFQ can work easily.

[0044] In order to further improve the maximum frequency of the SFQ circuit in the FPGA and SFQ chip integrated circuit system, the present invention is to Figure 1 The interface circuit of a SFQ shown in the figure is studied and analyzed. The critical current of the Josephson junction J2 is larger than that of the Josephson junction J1. One side of the Josephson junction J1 is connected to the inductor L. The bias current I b It is mainly through the Josephson junction J2 junction and selects an appropriate size to make it in the precritical state. INDuring input, it is mainly grounded through the inductor L, and a small part flows through the Josephson junction J1 and the Josephson junction J2, causing the superconducting critical state of the Josephson junction J2 to reverse, while the Josephson junction J1 has no obvious change, and an SFQ pulse is generated at the output end, and a magnetic flux quantum enters the superconducting quantum interference device loop. IN When it decreases, the ring current and the bias current have the same direction in the Josephson junction J1, but opposite directions in the Josephson junction J2, causing the Josephson junction J1 to reverse, and the trapped magnetic flux quantum is released through the flipping of J1, and the circuit returns to its original state. Figure 1 The interface circuit of the SFQ is simulated, and the input signal is a DC square wave. Figure 2 As shown in the working waveform diagram, the output end of the SFQ interface circuit obtains a periodic SFQ signal.

[0045] Depend on Figure 2 It can be seen that the superconducting DC / SFQ conversion circuit implements positive edge sampling, that is, the output of the superconducting signal only occurs at the positive edge trigger of the DC square wave. Therefore, the present invention realizes increasing the operating frequency through double sampling by triggering at the interface between CMOS and SFQ (rising edge and falling edge), that is, clock sampling is performed on both the positive and negative edge SFQ interface circuits, so that the upper limit frequency of the SFQ core circuit is twice the frequency of the external control clock upper limit, thereby realizing the double data flow of DDR (double data rate, synchronous dynamic), and doubling the operation speed of the core SFQ circuit.

[0046] In a specific embodiment of the present invention, Figure 3 As shown, a novel CMOS / SFQ interface circuit includes a mutual inductance interface module and a superconducting combiner;

[0047] The input end of the mutual inductance interface module is connected to the input current I in , used to convert the input current I in The coupling current is coupled to the mutual inductance interface circuit to generate a coupling current, wherein the input current is a DC square wave; when the coupling current increases with the current value of the DC square wave at the rising edge to meet a first condition, the first output end of the mutual inductance interface module outputs a first SFQ signal SFQ1; when the coupling current increases with the current value of the DC square wave at the falling edge to meet a second condition, the second output end of the mutual inductance interface module outputs a second SFQ signal SFQ2;

[0048] The first input end of the superconducting combiner is connected to the first output end of the mutual inductance interface module, the second input end of the superconducting combiner is connected to the second output end of the mutual inductance interface module, and the superconducting combiner outputs the first SFQ signal SFQ1 or the second SFQ signal SFQ2.

[0049] The present invention obtains coupling current by mutual inductance of input current (DC square wave) through mutual inductance interface module, and outputs first SFQ signal and second SFQ signal as coupling current changes, which correspond to the rising edge and falling edge of DC square wave respectively, so as to realize sampling of positive and negative edges of DC square wave current, and improve the maximum frequency of SFQ operation by double sampling.

[0050] Furthermore, if Figure 4 As shown, the mutual inductance interface module in the specific embodiment of the present invention includes a self-inductance coil L0, a SQUID loop, a first JTL and a second JTL;

[0051] The self-inductance coil L0 forms a mutual inductance with the mutual inductance coil L1 in the SQUID loop. in Coupling into the SQUID loop generates the coupling current I ou ;

[0052] One end of the first JTL is connected to the first end of the mutual inductance coil L1, and the other end of the first JTL is connected to the first input end of the superconducting combiner, and the first SFQ signal SFQ1 is output to the superconducting combiner through the first JTL;

[0053] One end of the second JTL is connected to the second end of the mutual inductance coil L1 , and the other end of the second JTL is connected to the second input end of the superconducting combiner. The second SFQ signal SFQ2 is output to the superconducting combiner through the first JTL.

[0054] The first end of the mutual inductance coil L1 is connected to a first current source, and the first current source provides a bias current I for the mutual inductance interface module. b .

[0055] More specifically, the input current I in Coupled into the SQUID loop, that is, the coupling current of the mutual inductance coil L1 is I ou , when the rising edge of the DC square wave arrives, the coupling current I ou As the current value of the DC square wave at the rising edge increases to meet the first condition, a counterclockwise circulating current is generated in the SQUID loop, and the first SFQ signal SFQ1 is output to the first input terminal of the superconducting combiner through the first JTL; when the falling edge of the DC square wave arrives, the coupling current I ou When the current value of the DC square wave at the falling edge increases to meet the second condition, the ground state is restored in the SQUID loop, and the second SFQ signal SFQ2 is output to the second input terminal of the superconducting combiner through the second JTL.

[0056] Furthermore, the size of the mutual inductance coil can be adjusted according to the actual application scenario of the circuit: when input current amplification is required, the mutual inductance value can be increased, and when the input current amplitude needs to be reduced, a smaller mutual inductance coil can be used.

[0057] In a specific embodiment of the present invention, the SQUID loop further includes a first Josephson junction J1 and a second Josephson junction J2;

[0058] The first Josephson junction J1 is connected to the first end of the mutual inductance coil L1. When the first condition is met, the first Josephson junction J1 is triggered to generate a first pulse, and the first JTL outputs a first SFQ signal SFQ1 under the action of the first pulse.

[0059] The second Josephson junction J2 is connected to the second end of the mutual inductance coil L1. When the second condition is met, the second Josephson junction J2 is triggered to generate a second pulse, and the second JTL outputs a second SFQ signal SFQ2 under the action of the second pulse.

[0060] More specifically, when the rising edge of the DC square wave arrives, the mutual inductance coupling current I ou1 Flows through the first Josephson junction J1, with the rising edge current I in The coupling current I flowing through the first Josephson junction J1 increases. ou1 Increases, when the coupling current I flowing through the first Josephson junction J1 ou1 The original bias current I in the first Josephson junction J1 b The sum exceeds the critical current I of the first Josephson junction J1 max1 , the first Josephson junction J1 is triggered, generating a first pulse to be transmitted to the first JTL on the right, and generating a counterclockwise circulating current in the SQUID ring (J1-L1-J2). Under the action of the first pulse, the first JTL outputs a first SFQ signal SFQ1, that is, a SFQ1 signal is generated at the first output terminal OUT1 of the mutual inductance interface module; after analysis, it is determined that the first condition is I ou1 +I b >I max1 .

[0061] More specifically, when the falling edge of the DC square wave arrives, the reverse coupling current I ou2 The original bias current I in the second Josephson junction J2 b The sum exceeds the critical current I of the second Josephson junction J2 max2, the second Josephson junction J2 is triggered to generate a second pulse, which cancels the counterclockwise circulating current in the SQUID ring (J1-L1-J2) to restore the SQUID ring to its ground state. At the same time, the second pulse is transmitted to the second JTL on the left. Under the action of the second pulse, the second JTL outputs a second SFQ signal SFQ2, that is, a SFQ2 signal is generated at the second output terminal OUT2 of the mutual inductance interface module; after analysis, it is determined that the second condition is I ou2 +I b >I max2 .

[0062] The subsequent periodic DC square wave will continue the previous working process, such as Figure 6 As shown, SFQ signals are generated in the interface circuit at both the rising edge and the falling edge of the input DC square wave, but the two SFQ signals generated by the positive and negative edges are output through the superconducting combiner. Since the first SFQ signal is generated during the rising edge and the second SFQ signal is generated during the falling edge, the rising edge and the falling edge are sent at different times. Therefore, the superconducting combiner always outputs one SFQ signal, that is, the first SFQ signal or the second SFQ signal.

[0063] In a specific embodiment of the present invention, Figure 5 As shown, the superconducting combiner includes a first buffer, a second buffer and an output unit;

[0064] The input end of the first buffer is connected to the first output end OUT1 of the mutual inductance interface module, and is used to buffer the first SFQ signal being transmitted;

[0065] The input end of the second buffer is connected to the second output end OUT2 of the mutual inductance interface module, and is used to buffer the second SFQ signal being transmitted;

[0066] The first buffer and the second buffer have the same output terminal and are connected to the input terminal of the output unit; the output unit outputs the first SFQ signal or the second SFQ signal.

[0067] The present invention uses the first buffer and the second buffer to output the first SFQ signal and the second SFQ signal through the output unit.

[0068] In a specific embodiment of the present invention, Figure 5 As shown, the first buffer includes a Josephson junction JB1, a Josephson junction JB2, an inductor LB2 and an inductor LAB1; one end of the inductor LB2 is connected to the Josephson junction JB1, and the other end of the inductor LB2 is connected to one end of the Josephson junction JB2; the other end of the Josephson junction JB2 is connected to one end of the inductor LAB1, and the other end of the inductor LAB1 is the output end of the first buffer.

[0069] In a specific embodiment of the present invention, Figure 5 As shown, the second buffer includes a Josephson junction JA1, a Josephson junction JA2, an inductor LA2 and an inductor LAB1; one end of the inductor LA2 is connected to the Josephson junction JA1, and the other end of the inductor LA2 is connected to one end of the Josephson junction JA2; the other end of the Josephson junction JA2 is connected to one end of the inductor LAB1, and the other end of the inductor LAB1 is the output end of the second buffer.

[0070] In the present invention, the first buffer and the second buffer both have the inductor LAB1, so that the first SFQ signal output by the first buffer and the second SFQ signal output by the second buffer are both output through the output unit.

[0071] In a specific embodiment of the present invention, the superconducting combiner further includes an inductor LB1, one end of the inductor LB1 is connected to the first output end of the mutual inductance interface module, and the other end of the inductor LB1 is connected to one end of the inductor LB2.

[0072] In a specific embodiment of the present invention, the superconducting combiner further includes an inductor LA1, one end of the inductor LA1 is connected to the second output end of the mutual inductance interface module, and the other end of the inductor LA1 is connected to one end of the inductor LA2.

[0073] In a specific embodiment of the present invention, Figure 5 As shown, the output unit includes an inductor LAB2, an inductor LAB3 and a Josephson junction JAB1; one end of the inductor LAB2 is connected to the other end of the inductor LAB1 and the output end of the second current source, the other end of the inductor LAB2 is connected to the Josephson junction JAB1 and one end of the inductor LAB3, and the other end of the inductor LAB3 is the output end of the output unit; wherein the second current source provides a bias current IAB1 for the superconducting combiner.

[0074] The novel CMOS / SFQ interface circuit of the present invention samples the positive and negative edges of the input DC square wave through the mutual inductance interface module, and outputs different SFQs at different times. The first SFQ signal and the second SFQ signal are led to the two input ends of the superconducting combiner, so that the DC square wave current I input into the novel CMOS / SFQ interface circuit can be realized. in Superconducting sampling is performed on the positive and negative edges, and the effect of SFQ pulse clock is obtained at the output end of the superconducting combiner.

[0075] In summary, the novel CMOS / SFQ interface circuit proposed in the present invention adopts mutual inductance for current coupling. This current coupling signal transmission method can completely isolate the SFQ chip and FPGA, and completely shield the influence of the ground bounce noise of the superconducting chip from the outside world; the mutual inductance interface module realizes the sampling of the positive and negative edges of the input DC square wave, and outputs them separately through the superconducting combiner, thereby doubling the utilization rate of the frequency broadband, and further reducing the pressure on the synchronous clock source to send high-frequency synchronous clock frequency; that is, it can easily increase the SFQ operating frequency. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0076] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A novel CMOS / SFQ interface circuit, characterized in that: It includes a mutual inductance interface module and a superconducting combiner; The input end of the mutual inductance interface module is connected to the input current, and is used to couple the input current to the mutual inductance interface circuit to generate a coupling current, and the input current is a DC square wave; when the coupling current increases with the current value of the DC square wave at the rising edge to meet the first condition, the first output end of the mutual inductance interface module outputs a first SFQ signal, and when the coupling current increases with the current value of the DC square wave at the falling edge to meet the second condition, the second output end of the mutual inductance interface module outputs a second SFQ signal; The first input end of the superconducting combiner is connected to the first output end of the mutual inductance interface module, the second input end of the superconducting combiner is connected to the second output end of the mutual inductance interface module, and the superconducting combiner outputs the first SFQ signal or the second SFQ signal.

2. The novel CMOS / SFQ interface circuit according to claim 1, characterized in that: The mutual inductance interface module includes a self-inductance coil, a SQUID loop, a first JTL and a second JTL; The self-inductance coil forms a mutual inductance with the mutual inductance coil in the SQUID loop, and couples the input current connected to the self-inductance coil into the SQUID loop to generate the coupling current; One end of the first JTL is connected to the first end of the mutual inductance coil, the other end of the first JTL is connected to the first input end of the superconducting combiner, and the first SFQ signal is output to the superconducting combiner through the first JTL; One end of the second JTL is connected to the second end of the mutual inductance coil, the other end of the second JTL is connected to the second input end of the superconducting combiner, and the second SFQ signal is output to the superconducting combiner through the first JTL.

3. The novel CMOS / SFQ interface circuit according to claim 2, characterized in that: The first end of the mutual inductance coil is connected to a first current source, and the bias current source provides a bias current for the mutual inductance interface module.

4. The novel CMOS / SFQ interface circuit according to claim 3, characterized in that: The SQUID loop also includes a first Josephson junction and a second Josephson junction; The first Josephson junction is connected to the first end of the mutual inductance coil, and when the first condition is met, the first Josephson junction is triggered to generate a first pulse, and the first JTL outputs a first SFQ signal under the action of the first pulse; The second Josephson junction is connected to the second end of the mutual inductance coil. When the second condition is met, the second Josephson junction is triggered to generate a second pulse, and the second JTL outputs a second SFQ signal under the action of the second pulse.

5. The novel CMOS / SFQ interface circuit according to claim 4, characterized in that: The first condition is I ou1 +I b >I max1 In the formula, I ou1 I is the coupling current obtained by mutual inductance after the rising edge of the DC square wave arrives. b is the bias current, I max1 is the critical current of the first Josephson junction J1.

6. The novel CMOS / SFQ interface circuit according to claim 4, characterized in that: The second condition is I ou2 +I b >I max2 In the formula, I ou2 I is the coupling current obtained by mutual inductance after the falling edge of the DC square wave arrives. b is the bias current, I max2 is the critical current of the second Josephson junction J2.

7. The novel CMOS / SFQ interface circuit according to claim 5 or 6, characterized in that: The superconducting combiner comprises a first buffer, a second buffer and an output unit; The input end of the first buffer is connected to the first output end OUT1 of the mutual inductance interface module, and is used to buffer the first SFQ signal being transmitted; The input end of the second buffer is connected to the second output end OUT2 of the mutual inductance interface module, and is used to buffer the second SFQ signal being transmitted; The first buffer and the second buffer have the same output terminal and are connected to the input terminal of the output unit; the output unit outputs the first SFQ signal or the second SFQ signal.

8. The novel CMOS / SFQ interface circuit according to claim 7, characterized in that: The first buffer includes a Josephson junction JB1, a Josephson junction JB2, an inductor LB2 and an inductor LAB1; One end of the inductor LB2 is connected to the Josephson junction JB1, and the other end of the inductor LB2 is connected to one end of the Josephson junction JB2; the other end of the Josephson junction JB2 is connected to one end of the inductor LAB1, and the other end of the inductor LAB1 is the output end of the first buffer.

9. The novel CMOS / SFQ interface circuit according to claim 7, characterized in that: The second buffer includes a Josephson junction JA1, a Josephson junction JA2, an inductor LA2 and an inductor LAB1; One end of the inductor LA2 is connected to the Josephson junction JA1, and the other end of the inductor LA2 is connected to one end of the Josephson junction JA2; the other end of the Josephson junction JA2 is connected to one end of the inductor LAB1, and the other end of the inductor LAB1 is the output end of the second buffer.

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