Stacked semiconductor memory device and method of manufacturing same

Abstract

The invention relates to a stacked semiconductor memory device and a method of manufacturing the same. The stacked semiconductor memory device may include a first structure and a second structure. The first structure may include a first substrate, a capacitor array, and a first bonding layer. The first substrate may have an upper surface and a lower surface. The capacitor array may include a plurality of capacitors integrated on an upper surface of the first substrate. A first bonding layer may be formed on the capacitor array. The second structure may include a second substrate, an access array, and a second bonding layer. The second substrate may have an upper surface and a lower surface. The access array may include a plurality of access transistors integrated on an upper surface of the second substrate. A second bonding layer may be formed on a lower surface of the second substrate. The second bonding layer may be hybrid bonded to the first bonding layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0142100 filed in the Korean Intellectual Property Office on October 23, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments generally relate to a semiconductor integrated circuit device, and more particularly, to a stacked semiconductor memory device and a method of manufacturing the stacked semiconductor memory device. Background Art

[0004] Increasing the integration of semiconductor devices can improve performance and also reduce the cost of semiconductor devices for customers.

[0005] The integration level of semiconductor devices is a factor that determines the price of electronic components, wherein the integration level of two-dimensional or planar semiconductor devices can determine the pricing of electronic components based on the occupied area of ​​a unit memory cell.

[0006] In particular, there may be economic and physical limitations to increasing the integration density in two-dimensional semiconductor devices because fine patterns that increase the integration density may require expensive exposure equipment or an exposure device with high resolution.

[0007] In order to address limitations of two-dimensional semiconductor devices and to improve and achieve higher integration of semiconductor devices, memory cells may be stacked in a three-dimensional (3D) manner, or a technique for stacking a memory cell array and a peripheral circuit is disclosed.

[0008] A stacked semiconductor device may include a layer having elements formed through a variety of processes, so that maintenance of electrical characteristics between the elements may determine performance of the stacked semiconductor device. Summary of the invention

[0009] According to the disclosed embodiments, a stacked semiconductor memory device may be provided. The stacked semiconductor memory device may include a first structure and a second structure. The first structure may include a first substrate, a capacitor array, and a first bonding layer. The first substrate may have an upper surface and a lower surface. The capacitor array may include a plurality of capacitors integrated on the upper surface of the first substrate. The first bonding layer may be formed on the capacitor array. The second structure may include a second substrate, an access array, and a second bonding layer. The second substrate may have an upper surface and a lower surface. The access array may include a plurality of access transistors integrated on the upper surface of the second substrate. The second bonding layer may be formed on the lower surface of the second substrate. The second bonding layer may be hybrid bonded to the first bonding layer.

[0010] In the disclosed embodiments, the capacitor array and the access array may have corresponding sizes.

[0011] In some embodiments, the second structure may further include a plurality of transistors and a peripheral circuit block. The transistors may be arranged on the periphery of the access array. The peripheral circuit block may include a plurality of interconnects electrically connected to the transistors.

[0012] In other embodiments, the capacitor array may have a size corresponding to the size of the access array and the peripheral circuit blocks.

[0013] In the disclosed embodiment, the first structure may further include a plurality of micro capacitors disposed at a portion corresponding to the peripheral circuit block.

[0014] According to the disclosed embodiments, a stacked semiconductor memory device may be provided. The stacked semiconductor memory device may include a first substrate and a second substrate. The first substrate may include a plurality of cell capacitors. The second substrate may include a plurality of word lines, a plurality of bit lines, and access transistors. The bit lines may intersect with the word lines. The access transistors may be connected to the intersections between the word lines and the bit lines. At least one of the first substrate and the second substrate may include a plurality of hybrid bonding pads electrically connected between the cell capacitors and the access transistors to form a memory cell array.

[0015] In the disclosed embodiments, the second substrate may further include a plurality of transistors and peripheral circuit blocks. The transistors may be directly and indirectly connected to the word lines and the bit lines. The peripheral circuit blocks may include a plurality of interconnects. The peripheral circuit blocks may be located on the surface of the second substrate, on which the access transistors, the word lines, and the bit lines may be integrated with the peripheral circuit blocks.

[0016] In the disclosed embodiment, the first substrate may further include a plurality of micro capacitors arranged at a portion corresponding to the peripheral circuit block.

[0017] In the disclosed embodiment, the stacked semiconductor memory device may further include a first bonding layer and a second bonding layer. The first bonding layer may be formed on the unit capacitor and the microcapacitor of the first substrate. The second bonding layer may be formed on the surface of the second substrate facing the first substrate. The second bonding layer may be bonded to the first bonding layer. The first bonding layer and the second bonding layer may include a plurality of hybrid bonding pads.

[0018] According to the disclosed embodiments, a method for manufacturing a stacked semiconductor memory device is provided. In the method for manufacturing a stacked semiconductor memory device, a plurality of unit capacitors may be formed on one surface of a first substrate. A first bonding insulating layer may be formed on the capacitor. The first bonding insulating layer may include a plurality of first bonding pads electrically connected to the unit capacitors. A second bonding insulating layer may be formed on one surface of a second substrate. The second bonding insulating layer may include a plurality of second bonding pads. The first substrate may be hybrid bonded to the second substrate so that the first bonding pads are in contact with the second bonding pads. A plurality of access transistors may be formed in a region where an access array may be formed in another surface of the second substrate.

[0019] According to the disclosed embodiments, a capacitor formed by a high temperature process and a circuit element such as a transistor formed by a non-high temperature process can be integrated on different substrates, thereby preventing electrical changes in the circuit element caused by the high temperature process.

[0020] In addition, circuit elements such as transistors formed by a non-high temperature process can be formed after a medium temperature process operating substantially from 100° C. to 350° C. as a hybrid bonding process and a high temperature process operating substantially from 400° C. to 700° C. to form a capacitor. Therefore, the heat load that may change the electrical characteristics of the circuit elements can be reduced. As a result, the electrical characteristics of the stacked semiconductor device are improved.

[0021] Furthermore, circuit elements and capacitors may be formed on different substrates to increase the integration of the memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The above and other aspects, features and advantages of the subject matter of the present disclosure will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0023] Figure 1 is a block diagram illustrating a stacked semiconductor memory device according to an example embodiment of the present disclosure;

[0024] Figure 2 is a perspective view showing a memory cell array of a stacked semiconductor memory device according to an example embodiment of the present disclosure;

[0025] Figure 3 is a perspective view showing a storage unit according to an example embodiment of the present disclosure;

[0026] Figure 4 is a cross-sectional view showing a stacked semiconductor memory device according to an example embodiment of the present disclosure;

[0027] Figures 5 to 9 is a cross-sectional view illustrating a method of manufacturing a memory cell array of a stacked semiconductor memory device according to an example embodiment of the present disclosure;

[0028] Fig.10 is a cross-sectional view showing a stacked semiconductor memory device according to an example embodiment of the present disclosure;

[0029] Fig.11 is a perspective view showing a stacked semiconductor memory device according to an example embodiment of the present disclosure;

[0030] Fig.12 It is shown Fig.11 A three-dimensional diagram of a memory cell array of a stacked semiconductor memory device;

[0031] Fig.13 It is shown Fig.11 A cross-sectional view of a stacked semiconductor memory device;

[0032] Fig.14 is a perspective view showing a stacked semiconductor memory device according to an example embodiment of the present disclosure; and

[0033] Fig.15 It is shown Fig.14 A cross-sectional view of a stacked semiconductor memory device in FIG. DETAILED DESCRIPTION

[0034] Various embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. The accompanying drawings are schematic diagrams of various embodiments (and intermediate structures). Therefore, due to reasons such as manufacturing techniques and / or tolerances, variations in the illustrated configurations and shapes are to be expected. Therefore, the described embodiments should not be interpreted as limited to the specific configurations and shapes shown herein, but may include deviations in configurations and shapes that do not depart from the spirit and scope of the present disclosure as defined by the appended claims.

[0035] The present disclosure is described herein with reference to the cross-sectional views and / or plan views of the idealized embodiments of the present disclosure. However, the embodiments of the present disclosure should not be construed as limiting the inventive concept. Although some embodiments of the present disclosure will be shown and described, it will be understood by those of ordinary skill in the art that these embodiments may be changed without departing from the principles and spirit of the present disclosure.

[0036] As used herein, the term "configured" refers to the size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one device to facilitate operation of the one or more of the structure and device in a predetermined manner.

[0037] As used herein, the terms "vertical," "longitudinal," "horizontal," and "transverse" refer to a plane of a structure, not necessarily defined by the Earth's gravitational field. A "horizontal" or "transverse" direction is a direction substantially parallel to the plane of the structure, while a "vertical" or "longitudinal" direction is a direction substantially perpendicular to the plane of the structure. The plane of the structure is defined by a surface of the structure having a large area compared to other surfaces of the structure. With reference to the accompanying drawings, a "horizontal" or "transverse" direction may be perpendicular to the indicated "Z" axis, and may be parallel to the indicated "X" axis and / or parallel to the indicated "Y" axis; a "vertical" or "longitudinal" direction may be parallel to the indicated "Z" axis, may be perpendicular to the indicated "X" axis, and may be perpendicular to the indicated "Y" axis.

[0038] As used herein, features (e.g., regions, structures, devices) described as being "adjacent" to each other mean and include features of the disclosed identity (or identities) that are close to each other (e.g., closest). Additional features (e.g., additional regions, additional structures, additional devices) that do not match the disclosed identity (or identities) of the "adjacent" feature may be arranged between the "adjacent" features. In other words, the "adjacent" features may be positioned directly adjacent to each other so that no other features intervene between the "adjacent" features; or, the "adjacent" features may be positioned indirectly adjacent to each other so that at least one feature of an identity different from the identity associated with at least one "adjacent" feature is positioned between the "adjacent" features. Thus, features described as being "vertically adjacent" to each other mean and include features of the disclosed identity (or identities) that are close to each other in the vertical direction (e.g., closest in the vertical direction). In addition, features described as being "horizontally adjacent" to each other mean and include features of the disclosed identity (or identities) that are close to each other in the horizontal direction (e.g., closest in the horizontal direction).

[0039] As used herein, for ease of description, spatially related terms (e.g., "below," "below," "bottom," "above," "upper," "top," "front," "back," "left," "right," etc.) may be used to describe the relationship between an element or feature and another element or feature as shown. Unless otherwise indicated, spatially relative terms are intended to cover different orientations of materials in addition to the orientations depicted in the figures. For example, if the material in the figure is inverted, an element described as "below" or "below" or "under" or "on the bottom" of other elements or features will be oriented as "above" or "on the top" of other elements or features. Therefore, depending on the context in which the term "below" is used, the term can cover both the orientation of the top and the bottom, which is obvious to one of ordinary skill in the art. The material can be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped) and the spatially relative descriptors used herein are interpreted accordingly.

[0040] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0041] As used herein, the phrases "coupled to" and "connected to" refer to structures that are operatively connected to one another, such as by a direct ohmic connection or by an indirect electrical connection (eg, through another structure).

[0042] As used herein, the term "substantially" in reference to a given parameter, property, or condition means and includes the degree to which a given parameter, property, or condition is satisfied with a certain degree of difference (e.g., within an acceptable tolerance range) as would be understood by one of ordinary skill in the art. For example, depending on the particular parameter, property, or condition that is substantially satisfied, the parameter, property, or condition may be at least 90.0% satisfied, at least 95.0% satisfied, at least 99.0% satisfied, at least 99.9% satisfied, or even 100.0% satisfied.

[0043] In an example embodiment of the present disclosure, a device formed by a high temperature process and a device formed by a low temperature process may be coupled to different substrates. In addition, in order to reduce the thermal burden of the device formed by the low temperature process, the device formed by the low temperature process may be integrated after bonding the substrates to each other.

[0044] Figure 1 is a block diagram illustrating a stacked semiconductor memory device according to an embodiment of the present disclosure.

[0045] Reference Figure 1 , a stacked semiconductor memory device 100 according to an embodiment of the present disclosure may include a memory cell array 110 and a peripheral circuit block 190 .

[0046] The memory cell array 110 may include a plurality of memory cells MC. The memory cell array 110 may further include at least two stacked structures: a first structure 110a and a second structure 110b. In an embodiment of the present disclosure, the memory cell array 110 may include a plurality of word lines and a plurality of bit lines intersecting each other. The memory cell MC may be connected to the intersection between the word line and the bit line. The memory cell MC may be grouped and controlled as a memory cell unit. In addition, the memory cell MC in the memory cell may be grouped and controlled as a matrix unit. For example, the memory cell MC may include a dynamic random access memory (DRAM) cell. In an embodiment of the present disclosure, the DRAM cell may include a selection transistor and a capacitor. The memory cell array 110 may further include a DRAM cell, a memory interface 27, and the memory interface 27 is used to communicate based on any one of the following: double data rate (DDR), low power double data rate (LPDDR), graphic double data rate (GDDR), wide I / O, high bandwidth memory (HBM), and hybrid memory cube (HMC), etc.

[0047] The memory cell array 110 may be shown in more detail below.

[0048] The peripheral circuit block 190 may include a memory control logic 105 , an address register 120 , a bank control logic 130 , a row selection circuit 140 , a column selection circuit 160 , a sense amplification circuit 150 , an input / output gating circuit 170 , and a data input / output buffer 180 .

[0049] The row selection circuit 140 may select and control a word line in the memory cell array 110. The column selection circuit 160 may select and control a bit line in the memory cell array 110. The sense amplifier circuit 150 may include a plurality of sense amplifiers connected to the bit lines of the memory cell array 110.

[0050] The stacked semiconductor memory device 100 may receive a clock signal, address information ADDR based on the clock signal, and a command CMD from an external device such as a memory controller.

[0051] The address register 120 may receive address information ADDR from the memory controller to generate an internal address. The internal address may include a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR.

[0052] The bank control logic 130 may generate a bank control signal in response to the bank address BANK_ADDR The bank control signal may be input into the row selection circuit 140 and the column selection circuit 160 .

[0053] The row selection circuit 140 may receive a bank control signal and a row address ROW_ADDR to activate a selected row or a selected word line of a selected bank. The column selection circuit 160 may receive a bank control signal and a column address COL_ADDR to activate a selected column or a selected bit line of a selected bank. The column selection circuit 160 may activate a sense amplifier connected to a selected bank and a selected column or bit line through an input / output gating circuit 170.

[0054] The input / output gating circuit 170 may include at least one read data latch and at least one write driver. The read data latch may store data output from the input data masking logic and the memory cell array 110 using a circuit configured to gating input / output data. The write driver may register data into the memory cell array 110.

[0055] In an embodiment of the present disclosure, the sense amplifier circuit 150 may sense data DQ read from a selected memory cell MC of a selected memory bank. The data DQ may be stored in a read data latch of the input / output gating circuit 170. The data DQ in the read data latch may be provided to a memory controller through a data input / output buffer 180.

[0056] The data DQ written in the selected memory cell of the selected memory bank may be provided from the memory controller to the data input / output buffer 180. The data DQ in the data input / output buffer 180 may be stored in the selected memory cell of the selected memory bank through the write driver.

[0057] The memory control logic 105 may control the operation of the stacked semiconductor memory device 100. The memory control logic 105 may generate a control signal for performing an active operation of the stacked semiconductor memory device 100, such as a write operation or a read operation.

[0058] The peripheral circuit block 190 may include various circuits as well as the above-mentioned circuits.

[0059] Figure 2 is a perspective view showing a memory cell array of a stacked semiconductor memory device according to an embodiment of the present disclosure, Figure 3 is a perspective view showing a storage unit according to an embodiment of the present disclosure.

[0060] Reference Figures 1 to 3, the memory cell array 110 of the embodiment of the present disclosure may include a first structure 110a and a second structure 110b stacked in sequence. The first structure 110a and the second structure 110b may be bonded to each other. The first structure 110a and the second structure 110b may include a wafer, a substrate, a chip, a portion of a wafer having at least one chip, etc. The first structure 110a and the second structure 110b may correspond to a substrate generated for element integration.

[0061] The first structure 110a may include a capacitor array CPA. The capacitor array CPA may include a plurality of capacitors Cap arranged regularly.

[0062] The second structure 110b may be stacked and bonded on the first structure 110a. The access array ACA may be integrated on one surface of the second structure 110b that is not bonded to the first structure 110a.

[0063] The access array ACA may include a plurality of word lines WL0-WL3 and a plurality of bit lines BL0-BL3. The word lines WL0-WL3 may be arranged parallel to each other along a row direction D1. The bit lines BL0-BL3 may be arranged parallel to each other along a column direction D2. The row direction D1 may be substantially perpendicular to the column direction D2. The direction D3 may be a stacking direction. In an embodiment of the present disclosure, the word lines WL0-WL3 and the bit lines BL0-BL3 intersect with each other to define a plurality of memory cell array regions.

[0064] The access array ACA may include a plurality of access transistors TR. The access transistors TR may be connected to the intersections between the word lines WL0-LW3 and the bit lines BL0-BL3. Each access transistor TR may be located at a memory cell region. The access transistors TR may correspond to the capacitors Cap of the first structure 110a. Therefore, the size of the access array ACA may correspond to the size of the capacitor array CPA. The access transistors TR may be activated according to the selection of the word lines and the bit lines connected to the access transistors TR.

[0065] The capacitor Cap and the access transistor TR may be electrically connected to each other by a hybrid bonding portion HB provided to at least one of the first structure 110a and the second structure 110b. For example, the first structure 110a and the second structure 110b may include a hybrid bonding pad configured to electrically connect the capacitor Cap to the access transistor TR. Therefore, the memory cell array 110 of the embodiment of the present disclosure may be a combination of the first structure 110a and a portion of the second structure 110b stacked in a three-dimensional (3D) manner.

[0066] Figure 4 is a cross-sectional view showing a stacked semiconductor memory device according to an embodiment of the present disclosure.

[0067] Reference Figure 4 , the stacked semiconductor memory device 100 of the embodiment of the present disclosure may include a first structure 110 a and a second structure 110 b which are hybrid-bonded to each other through a hybrid bonding portion HB.

[0068] The first structure 110 a may include a first substrate Sub1 , a capacitor array CPA, and a first bonding layer BS1 .

[0069] The first substrate Sub1 may include a single crystal silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a polysilicon layer, a support layer having a semiconductor material, a silicon on insulator (SOI) substrate, etc., but is not limited thereto. The first substrate Sub1 may have an upper surface and a lower surface.

[0070] The capacitor array CPA may be integrated on one surface of the first substrate Sub1, for example, on the upper surface of the first substrate Sub1. The capacitor array CPA may include a plurality of capacitors Cap arranged regularly. For example, the capacitor Cap may include a plate electrode PL, a dielectric layer DE, and a storage electrode ST. The storage electrodes ST of the capacitor Cap may be electrically isolated from each other. The plate electrodes PL of the capacitor Cap may be connected to each other. The dielectric layer DE may be interposed between the plate electrode PL and the storage electrode ST. In an embodiment of the present disclosure, the storage electrode ST may have a cylindrical shape, but is not limited thereto. The regularity may be similar to Figure 2 and Figure 3 The arrangement rules of the memory cell area or access transistors in the memory cell are basically the same.

[0071] The first bonding layer BS1 may be formed on the first substrate Sub1 where the capacitor array CPA may be formed. The first bonding layer BS1 may include a plurality of first bonding pads BP1 and a first bonding insulating layer Bl1.

[0072] A portion of the first bonding pad BP1 may be electrically connected to the capacitor Cap. For example, the first bonding pad BP1 may be electrically connected to the storage electrode ST of the capacitor Cap. The first bonding insulating layer Bl1 may electrically insulate the first bonding pads BP1 from each other.

[0073] The second structure 110 b may include a second substrate Sub2 , an access array ACA, and a second bonding layer BS2 .

[0074] The second substrate Sub2 may include a silicon substrate, a single crystal silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, etc., but is not limited thereto. In addition, the second substrate Sub2 may include an intrinsic semiconductor material or a conductive impurity. The second substrate Sub2 may be substantially the same as or different from the first substrate Sub1. The second substrate Sub2 may have an upper surface and a lower surface.

[0075] The access array ACA may be integrated on a surface of the second substrate Sub2, for example, on the upper surface of the second substrate Sub2. The access array ACA may include a plurality of access transistors TR. Each access transistor TR may include a gate, a source, and a drain. The access transistors TR may have substantially the same structure. In an embodiment of the present disclosure, a channel between a source and a drain of the access transistor TR may have a horizontal channel structure substantially parallel to the surface of the second substrate Sub2, but is not limited thereto. For example, the channel may have a vertical channel structure substantially perpendicular to the surface of the second substrate Sub2, or a fin channel structure, etc.

[0076] The access array ACA may include a plurality of word lines WLa to WLd and a plurality of bit lines BL. The word lines WLa to WLd may be connected to the gate of the access transistor TR. The bit line BL may be connected to the drain of the access transistor TR. As described above, the word lines WLa to WLd may be arranged parallel to each other along the row direction D1. The bit lines BL may be arranged parallel to each other along the column direction D2 perpendicular to the row direction D1.

[0077] In an embodiment of the present disclosure, the gates of the access transistors TR in the same row may be electrically connected to the same word line, while the gates of the access transistors TR in different rows may be electrically connected to different word lines.

[0078] In addition, the drains of the access transistors TR in the same column may be electrically connected to the same bit line. The drains of the access transistors TR in different columns may be electrically connected to different bit lines. Figure 4 In the embodiment, a part of the access transistor TR can be connected to the same bit line BL and different word lines WLa to WLd.

[0079] The access array ACA may include a plurality of insulating interlayers ILD. The insulating interlayers ILD may be located between the upper surface of the second substrate Sub2 and the word lines WLa-WLd and between the word lines WLa-WLd and the bit lines BL. Therefore, the word lines WLa-WLd may be electrically isolated from the bit lines BL. In addition, the access transistors TR may be electrically isolated from each other.

[0080] The second bonding layer BS2 may be formed on another surface of the second substrate Sub2, for example, on the lower surface of the second substrate Sub2, so that the second bonding layer BS2 and the first bonding layer BS1 face each other. The second bonding layer BS2 may include a plurality of second bonding pads BP2 and a second bonding insulating layer Bl2.

[0081] At least one of the second bonding pads BP2 may be electrically connected to the access transistor TR, for example, a source of the access transistor TR. The second bonding insulating layer Bl2 may electrically insulate the second bonding pads BP2 from each other.

[0082] The second bonding layer BS2 may be hybrid-bonded to the first bonding layer BS1. For example, the second bonding insulating layer Bl2 of the second bonding layer BS2 may be directly bonded to the first bonding insulating layer Bl1 of the first bonding layer BS1. In addition, the second bonding pad BP2 of the second bonding layer BS2 may be directly bonded to the first bonding pad BP1 of the first bonding layer BS1.

[0083] By bonding the first bonding pad BP1 with the second bonding pad BP2 , the access array ACA of the first structure 110 a may be electrically combined with the capacitor array CPA of the second structure 110 b to form the memory cell array 110 including memory cells stacked in 3D.

[0084] Figures 5 to 9 is a cross-sectional view illustrating a method of manufacturing a memory cell array of a stacked semiconductor memory device according to an embodiment of the present disclosure.

[0085] Reference Figure 5 , a first conductive layer may be formed on the first substrate 210. The first conductive layer may be patterned to form a common electrode layer 222.

[0086] For example, the first substrate 210 may be a bare semiconductor substrate. When the first substrate 210 may include a semiconductor material, the insulating layer 215 may be interposed between the first substrate 210 and the common electrode layer 222. The insulating layer 215 may electrically isolate the first substrate 210 from the common electrode layer 222. Alternatively, the first substrate 210 may include an insulating material. When the first substrate 210 may include an insulating material, the common electrode layer 222 may be directly formed on the first substrate 210 without the insulating layer 215.

[0087] The second conductive layer may be formed on the common electrode layer 222. The second conductive layer may be patterned to form a plurality of plate patterns 225.

[0088] For example, the thickness of the second conductive layer may be thicker than the thickness of the first conductive layer. That is, the thickness of the plate pattern 225 may be thicker than the thickness of the common electrode layer 222. In addition, the common electrode layer 222 and the plate pattern 225 may include the same material or different materials. The plate pattern 225 may be formed to have the above-mentioned regular size and gap arrangement. The plate pattern 225 may be coupled to the common electrode layer 222 to form the plate electrode 220.

[0089] The dielectric layer 230 may be formed on the surface of the plate electrode 220, for example, on the surface of the common electrode layer 222 and the plate pattern 225. In an embodiment of the present disclosure, the dielectric layer 230 may have a uniform thickness. The dielectric layer 230 may include a metal oxide layer having a high dielectric constant. The metal oxide layer may include at least one of a hafnium oxide layer, a doped hafnium oxide layer, a hafnium zirconium oxide layer, a doped hafnium zirconium oxide layer, a tantalum oxide layer, a zirconium oxide layer, an aluminum oxide layer, and a titanium oxide layer. The dielectric layer 230 may be crystallized by annealing at a high temperature of substantially 400° C. to 700° C.

[0090] A third conductive layer having a uniform thickness may be formed on the dielectric layer 230. The third conductive layer may be etched to form a storage electrode 240. The storage electrode 240 may have a cylindrical shape configured to surround each plate pattern 225. Thus, a plurality of capacitors 250 may be formed on the first substrate 210.

[0091] In an embodiment of the present disclosure, the third conductive layer for the storage electrode 240 may have a thickness thinner than that of the plate pattern 225 , but is not limited thereto.

[0092] In an embodiment of the present disclosure, at least one of the common electrode layer 222 , the plate pattern 225 , and the storage electrode 240 may include iridium (Ir), ruthenium (Ru), platinum (Pt), or a new metal having a high work function, or the like.

[0093] In an embodiment of the present disclosure, at least one of the common electrode layer 222 , the plate pattern 225 , and the storage electrode 240 may include a metal nitride layer, such as a titanium nitride layer.

[0094] In an embodiment of the present disclosure, the crystallization process of the dielectric layer 230 may be performed after forming the dielectric layer 230 or after forming the storage electrode 240 .

[0095] Although the dielectric layer 230 may be crystallized at a high temperature, the capacitor 250 or the plate electrode 220 which may not have a thermal burden caused by the high temperature may be formed on the first substrate 210 so that an electrical problem caused by the crystallization process may not be generated.

[0096] The insulating interlayer 260 may be formed on the first substrate 210 having the capacitors 250. The insulating interlayer 260 may have a thickness for filling a space between the capacitors 250. The insulating interlayer 260 may include at least one insulating layer. The insulating layer may include a planarization material.

[0097] In an embodiment of the present disclosure, the insulating interlayer 260 may be planarized by a chemical mechanical polishing (CMP) process. The insulating interlayer 260 may be planarized until the surface of the storage electrode 240 is exposed.

[0098] The first bonding insulating layer 272 may be formed on the insulating interlayer 260. The first bonding insulating layer 272 may include at least one insulating layer. The insulating layer may include a silicon oxide layer, a silicon nitride layer, and the like.

[0099] Etching the first bonding insulating layer 272 may form a first pad region. The first pad region may expose a portion of the capacitor 250, for example, a portion of the storage electrode 240.

[0100] A first pad metal layer may be formed on the first bonding insulating layer 272 to fill the first pad region. The first pad metal layer may include copper. The first pad metal layer may be planarized until the first bonding insulating layer 272 may be exposed to form a first bonding pad 275 in the first pad region. The first bonding pad 275 may be directly and indirectly connected to the storage electrode 240. Alternatively, although not shown in the drawings, at least one interconnect may be interposed between the storage electrode 240 and the first bonding pad 275.

[0101] Reference numeral 270 may denote a first bonding layer including a first bonding insulating layer 272 and a first bonding pad 275. Reference numeral 200 may denote a combination of a first substrate 210 (hereinafter, referred to as a first structure) including a capacitor 250 and a first bonding layer 270 which are sequentially stacked.

[0102] Reference Figure 6 , a second substrate 310 may be prepared. The second substrate 310 may be bonded to the first structure 200. The second substrate 310 may include a bare semiconductor substrate. The second substrate 310 may have an upper surface and a lower surface.

[0103] The second bonding insulating layer 322 may be formed on any surface selected from the upper surface and the lower surface of the second substrate 310. The second bonding insulating layer 322 may include at least one insulating layer. The insulating layer may include a silicon oxide layer, a silicon nitride layer, etc. The second bonding insulating layer 322 may include a material and structure substantially the same as that of the first bonding insulating layer 272. Alternatively, the material and structure of the second bonding insulating layer 322 may be different from that of the first bonding insulating layer 272.

[0104] Etching the second bonding insulating layer 322 can form a second pad region. The second pad region can be configured to expose a selected portion of the second substrate 310. A pad metal layer can be formed on the second bonding insulating layer 322. The pad metal layer can have a thickness for filling the second pad region. The pad metal layer can be planarized until the surface of the second bonding insulating layer 322 can be exposed to form a second bonding pad 325 in the second pad region. Therefore, the second bonding layer 320 can be formed on the upper surface of the second substrate 310. The second bonding layer 320 may include a second bonding insulating layer 322 and a second bonding pad 325.

[0105] Reference Figure 7 , the second substrate 310 may be stacked on the first structure 200 such that the first bonding layer 270 of the first structure 200 and the second bonding layer 320 of the second substrate 310 face each other.

[0106] In an embodiment of the present disclosure, the first structure 200 and the second substrate 310 may be aligned with each other so that the first bonding pad 275 corresponds to the second bonding pad 325 .

[0107] The first bonding layer 270 may be hybrid-bonded to the second bonding layer 320. Specifically, the back surface of the second substrate 310 on the first structure 200 may be compressed to preliminarily bond the first bonding insulating layer 272 to the second bonding insulating layer 322. The annealing process may be performed at a temperature of substantially 100° C. to 350° C. to cause metal bonding by thermal expansion of the first bonding pad 275 and the second bonding pad 325.

[0108] In an embodiment of the present disclosure, the first structure 200 may include a capacitor 250 having a heat resistance of substantially 400° C. to 700° C. In contrast, any element other than the second bonding layer 320 may not be formed on the second substrate 310. Therefore, electrical characteristics of the first structure 200 and the second substrate 310 may not be changed by the annealing process of the metal bonding.

[0109] When the second substrate 310 is bonded to the first structure 200, the non-selected surface of the second substrate 310 may be exposed. The non-selected surface of the second substrate 310 may be ground to form a second substrate 310a having a thin thickness. In an embodiment of the present disclosure, the thickness of the second substrate 310a may be thinner than the thickness of the first substrate 210. Hereinafter, the ground non-selected surface of the second substrate 310a may be referred to as a device surface DS.

[0110] The isolation layer 330 may be formed in the second substrate 310a to define an area where a memory cell may be formed, such as an active area ACT. The isolation layer 330 may be formed by a shallow trench isolation (STI) process. The depth of the isolation layer 330 may be changed by a designer. First conductive type impurities may be implanted into the active area ACT to form a well region.

[0111] In an embodiment of the present disclosure, the active area ACT may correspond to the capacitor 250 of the first structure 200 .

[0112] Reference Figure 8 , the gate 342 may be formed on the active area ACT. The gate insulating layer 341 may be interposed between the gate 342 and the device surface DS of the second substrate 310a. The second conductive type impurities may be implanted into the active area ACT on both sides of the gate 342 to form a source 345a and a drain 345b. Therefore, the access transistor 340 may be integrated in each active area ACT of the second substrate 310a.

[0113] For example, each source 345 a may correspond to each second bonding pad 325 .

[0114] Furthermore, before, during, or after forming the access transistor 340 , an embedded electrode 315 may be formed in the second substrate 310 a to connect the source 345 a with the second bonding pad 325 .

[0115] For example, the embedded electrode 315 may be formed in a through silicon via (TSV). The embedded electrode 315 may include a multilayer interconnect. Alternatively, the embedded electrode 315 may include an impurity region such as a deep well. In an embodiment of the present disclosure, the embedded electrode 315 may be coupled to the bottom surface of the source 345a. Alternatively, the embedded electrode 315 may be formed through the source 345a. In addition, the embedded electrode 315 may be coupled to the side surface of the source 345a.

[0116] The embedded electrode 315 may be electrically isolated from the second substrate 310a. Although not shown in the drawings, an insulating layer may be interposed between a sidewall of the embedded electrode 315 and the second substrate 310a.

[0117] Reference Fig. 9 The first insulating interlayer 350 may be formed on the device surface DS of the second substrate 310a having the access transistor 340. The first insulating interlayer 350 may include at least one insulating layer. Alternatively, the first insulating interlayer 350 may include at least one planarization layer.

[0118] The first insulating interlayer 350 may be etched until the upper surface of the gate 342 may be exposed to form a word line contact hole. The word line contact hole may be filled with a conductive material to form a word line contact 352. A metal layer may be formed on the first insulating interlayer 350. The metal layer may be coupled to the word line contact 352. The metal layer may be patterned to form a first wiring 355. The first wiring 355 may be a word line or a portion of a word line.

[0119] A second insulating interlayer 360 may be formed on the first insulating interlayer 350. The second insulating interlayer 360 may include an insulating material that is substantially the same as or different from the insulating material of the first insulating interlayer 350. The second insulating interlayer 360 and the first insulating interlayer 350 may be etched until the drain 345b of the access transistor 340 may be exposed to form a bit line contact hole. The bit line contact hole may be filled with a conductive material to form a bit line contact 365. A metal layer may be formed on the second insulating interlayer 360. The metal layer may be coupled to the bit line contact 365. The metal layer may be patterned to form a second wiring 370. The second wiring 370 may be a bit line or a portion of a bit line.

[0120] Reference numeral 300 may denote a combination of a second substrate 310 a and an access transistor 340 , a word line, and a bit line, ie, a second structure.

[0121] According to an embodiment of the present disclosure, a capacitor formed by a high temperature process and an access transistor formed by a low temperature process can be integrated on different substrates. Specifically, after the capacitor is formed by a high temperature process, the access transistor can then be formed, so that the thermal burden on the access transistor can be reduced.

[0122] Furthermore, the access transistor can be integrated on the hybrid bonded substrate, so that the additional thermal burden in the hybrid bonding process can also be reduced.

[0123] Furthermore, an access transistor and a capacitor may be formed on different substrates, so that the capacitor may have increased capacitance by securing an area, or a memory cell may have increased integration.

[0124] Furthermore, the access transistor and the capacitor may be directly connected to the hybrid bonding portion HB (eg, bonding pad) not through an interconnection, so that a connection path may be reduced to reduce a signal delay.

[0125] Fig.10 is a cross-sectional view showing a stacked semiconductor memory device according to an embodiment of the present disclosure.

[0126] Reference Fig.10, the access transistor 340 , the first wiring 355 , the second wiring 370 , and the second bonding layer 320 may be separately formed on the second substrate 310 a to form the second structure 300 , and the second substrate 310 a may not be bonded to the first structure 200 .

[0127] The first bonding layer 270 of the first structure 200 may be hybrid-bonded with the second bonding layer 320 of the second structure 300 to complete a stacked semiconductor memory device.

[0128] Fig.11 is a perspective view showing a stacked semiconductor memory device according to an embodiment of the present disclosure, Fig.12 It is shown Fig.11 A three-dimensional diagram of a memory cell array of a stacked semiconductor memory device, Fig.13 It is shown Fig.11 A cross-sectional view of a stacked semiconductor memory device in FIG.

[0129] Reference Figures 11 to 13 , the stacked semiconductor memory device 100 a of the embodiment of the present disclosure may include a first structure 111 a and a second structure 111 b hybrid-bonded to the first structure 111 a .

[0130] The first structure 111a may include a first substrate Sub1 on which a capacitor array CPA1 may be integrated. The capacitor array CPA1 may include a plurality of capacitors cap1. The first structure 111a may also include a first bonding layer BS1 on the capacitor array CPA1. The first bonding layer BS1 may include first bonding pads BP1 and a first bonding insulating layer Bl1. The first bonding pads BP1 may be connected to the capacitors cap1, respectively. The first bonding insulating layer Bl1 may electrically isolate the first bonding pads BP1 from each other. For example, the first bonding pads BP1 may be located at a region corresponding to the capacitor cap1. The first bonding pads BP1 may be electrically connected to the storage electrode ST of the capacitor cap1.

[0131] The second structure 111b may include a second substrate Sub2. A second bonding layer BS2 may be formed on a lower surface of the second substrate Sub2. The second bonding layer BS2 may be bonded to the first bonding layer BS1. The second bonding layer BS2 may include a second bonding pad BP2 and a second bonding insulating layer Bl2. The second bonding pad BP2 may correspond to the first bonding pad BP1. The second bonding insulating layer Bl2 may electrically isolate the second bonding pads BP2 from each other.

[0132] The access array ACA1 and the peripheral circuit block PB may be integrated on the upper surface of the second substrate Sub2. Figure 2The access array ACA1 may include a plurality of access transistors TRa, a plurality of word lines WL0-WL3, and a plurality of bit lines BL0-BL3. The peripheral circuit block PB may be arranged on the periphery of the access array ACA1. The peripheral circuit block PB may include Figure 1 The peripheral circuit block PB may include a plurality of transistors TRb (hereinafter, referred to as peripheral transistors) and a multi-layer interconnect ICS. The peripheral transistors TRb may form a memory control logic 105, an address register 120, a memory bank control logic 130, a row selection circuit 140, a column selection circuit 160, a sense amplifier circuit 150, an input / output gating circuit 170, and a data input / output buffer 180.

[0133] In an embodiment of the present disclosure, the access transistor TRa and the peripheral transistor TRb can be formed on the same surface of the same substrate by the same process. The access transistor TRa and the peripheral transistor TRb can have different sizes, that is, different channel lengths. In addition, the peripheral transistor TRb can have a variety of channel lengths suitable for circuit characteristics.

[0134] Although not shown in the drawings, a portion of the peripheral transistor TRb may be directly and indirectly connected to the word lines WL0WL3 of the access array ACA1 through the interconnect ICS. Another portion of the peripheral transistor TRb may be directly and indirectly connected to the bit lines BL of the access array ACA1 through the interconnect ICS.

[0135] In an embodiment of the present disclosure, the capacitor array CPA1 may face the peripheral circuit block PB and the access array ACA1. The occupied area of ​​the capacitor cap1 may be substantially larger than the area of ​​the unit memory cell area UA, so that the semiconductor memory device has increased capacitance.

[0136] For example, the size of the capacitor cap1 in the embodiment of the present disclosure may be larger than Figure 4 Because the first bonding pad BP1 and the second bonding pad BP2 may be arranged to correspond to the capacitor cap1, the access transistor TRa that may be integrated in a small area may not face the second bonding pad BP2.

[0137] In this case, in order to electrically connect the second bonding pad BP2 to the access transistor TRa (particularly, the source S of the access transistor TRa), at least one embedded electrode EM and at least one wiring line RL may be formed in the second substrate Sub2. The structure of the embedded electrode EM and the wiring line RL may change the connection path between the second bonding pad BP2 and the access transistor TRa.

[0138] Furthermore, although not shown in the drawings, when the second substrate Sub2 may include a semiconductor material layer and at least one insulating layer, the embedded electrode EM and the wiring line RL may be formed between the semiconductor material layer and the insulating layer or between the insulating layers.

[0139] The access array ACA1 and the peripheral circuit block PB may be formed after forming the capacitor cap1 and hybrid bonding the first bonding layer BS1 to the second bonding layer BS2 through the hybrid bonding portion HB. Therefore, the access transistors TRa, the wirings WL and BL, and the interconnections (not shown) in the access array ACA1 and the peripheral circuit block PB may not be affected by the high temperature process and the thermal process of the hybrid bonding. As a result, the transistors TRa and TRb, the wirings WL and BL, and the interconnections ICS in the access array ACA1 and the peripheral circuit block PB may increase electrical reliability.

[0140] In addition, the area CA of the capacitor cap1 may be increased to ensure the capacitance of the memory device.

[0141] Fig.14 is a perspective view showing a stacked semiconductor memory device according to an embodiment of the present disclosure, Fig.15 It is shown Fig.14 A cross-sectional view of a stacked semiconductor memory device in FIG.

[0142] Reference Fig.14 and Fig.15 , the stacked semiconductor memory device 100 b of the embodiment of the present disclosure may include a first structure 112 a and a second structure 112 b hybrid-bonded to the first structure 112 a .

[0143] The first structure 112a may include a first substrate Sub1. The first capacitor array CPA2 and the second capacitor array CPA3 may be integrated on the first substrate Sub1.

[0144] The first capacitor array CPA2 may include a plurality of unit capacitors cap2. Figure 2 As shown, the cell capacitor cap2 may have a size corresponding to the size of a region where memory cells may be formed or the size of the unit memory cell area UA.

[0145] The second capacitor array CPA3 may be located on the periphery of the first capacitor array CPA2. The second capacitor array CPA3 may include a plurality of miniature capacitors cap3. The miniature capacitors cap3 may have substantially the same size or different sizes. The miniature capacitors cap3 may stabilize the power supply voltage. For example, the size of the miniature capacitors cap3 may be substantially equal to or different from the size of the unit capacitors cap2. In addition, the size of the miniature capacitors cap3 may be changed according to the integrated position and the connected circuit.

[0146] In an embodiment of the present disclosure, the unit capacitor cap2 and the micro capacitor cap3 may be formed on the same plane through the same process.

[0147] For example, each of the micro-capacitors cap3 may have a capacitance substantially the same as that of each of the unit capacitors cap2. The capacitance of at least one of the micro-capacitors cap3 may be different from the capacitance of the unit capacitor cap2. In addition, the micro-capacitor cap3 may have a capacitance different from the capacitance of the unit capacitor cap2. A portion of the micro-capacitors cap3 may have a capacitance substantially the same as that of the unit capacitor cap2, and the remaining micro-capacitors cap3 may have a capacitance different from that of the unit capacitor cap2.

[0148] The first structure 112a may further include a first bonding layer BS1 on the first capacitor array CPA2 and the second capacitor array CPA3. For example, the first bonding layer BS1 may include a plurality of first bonding pads BP1 and a first bonding insulating layer Bl1. The first bonding insulating layer Bl1 may electrically isolate the first bonding pads BP1 from each other.

[0149] A portion of the first bonding pad BP1 may be formed at a region corresponding to the cell capacitor cap2. A portion of the first bonding pad BP1 may be electrically connected to the storage electrode ST of the cell capacitor cap2. Another portion of the first bonding pad BP1 may be electrically connected to the micro capacitor cap3.

[0150] The second structure 112b may include a second substrate Sub2. A second bonding layer BS2 may be formed on a lower surface of the second substrate Sub2. The second bonding layer BS2 may be bonded to the first bonding layer BS1 of the first structure 112a. The second bonding layer BS2 may include a plurality of second bonding pads BP2 and a second bonding insulating layer Bl2. The second bonding pads BP2 may correspond to the first bonding pads BP1. The second bonding insulating layer Bl2 may electrically isolate the second bonding pads BP2 from each other.

[0151] The access array ACA2 and the peripheral circuit block PB may be integrated on the upper surface of the second substrate Sub2. Fig.11 The access array ACA1 of the present invention may include a plurality of access transistors TRa, a plurality of word lines WL0 to WL3, and a plurality of bit lines BL0 to BL3. The peripheral circuit block PB may be arranged on the periphery of the access array ACA2. The peripheral circuit block PB may have the same Fig.11 The configuration of the peripheral circuit block PB in is basically the same as the configuration.

[0152] In an embodiment of the present disclosure, the region where the access array ACA2 and the access transistor TRa are located may face the region where the cell capacitor cap2 is located. For example, the access transistor TRa may correspond to the cell capacitor cap2. Therefore, the source S of the access transistor TRa may be electrically connected to a portion of the second bonding pad BP2 facing the first bonding pad BP1 through an embedded electrode without a wiring line. In addition, another portion of the second bonding pad BP2 may be electrically connected to an electrical component of the peripheral circuit block PB.

[0153] The peripheral circuit block PB may further include a through electrode T formed through the second structure 112b. The through electrode T may be electrically connected to the second bonding pad BP2. In an embodiment of the present disclosure, the through electrode T may include a multilayer wiring structure. The through electrode T may be directly and indirectly connected to a circuit block configured to receive a power supply voltage. Therefore, the through electrode T may be electrically connected to the micro capacitor cap3 of the first structure 112a.

[0154] The access array ACA2 and the peripheral circuit block PB may be formed after forming the unit capacitor cap2 and the micro capacitor cap3 and hybrid bonding the first bonding layer BS1 to the second bonding layer BS2. Therefore, the access transistors TRa, the wirings WL and BL, and the interconnection ICS in the access array ACA2 and the peripheral circuit block PB may not be affected by the high temperature process of forming the unit capacitor cap2 and the micro capacitor cap3 and the thermal process of hybrid bonding. As a result, the transistors TRa and TRb, the wirings WL and BL, and the interconnection ICS in the access array ACA1 and the peripheral circuit block PB may have increased electrical reliability.

[0155] Furthermore, the micro capacitor cap3 may be integrated on the first structure 112a together with the unit capacitor cap2 so that the power supply voltage may be stably supplied to the access array ACA2 and the peripheral circuit block PB.

[0156] According to an embodiment of the present disclosure, a capacitor formed by a high temperature process and a circuit element such as a transistor formed by a non-high temperature process can be integrated on different substrates, thereby preventing electrical changes in the circuit element caused by the high temperature process.

[0157] In addition, circuit elements such as transistors formed by non-high temperature processes can be formed after the high temperature process and hybrid bonding process for forming capacitors. Therefore, the thermal burden that may change the electrical characteristics of the circuit elements can be reduced. As a result, the stacked semiconductor device can have improved electrical characteristics. In addition, circuit elements and capacitors can be formed on different substrates to increase the integration of the storage device.

[0158] In the embodiments of the present disclosure, two substrates or two structures may be exemplarily shown, but are not limited thereto.

[0159] The above embodiments of the present disclosure are intended to illustrate rather than limit the present disclosure. A variety of alternatives and equivalents are possible. The present disclosure is not limited to the embodiments described herein. The present disclosure is also not limited to any particular type of semiconductor device. In view of the present disclosure, other additions, reductions or modifications are obvious and are intended to fall within the scope of the appended claims.

Claims

1. A stacked semiconductor memory device, comprising: A first structure comprising a first substrate, a capacitor array and a first bonding layer, the first substrate having an upper surface and a lower surface, the capacitor array having a plurality of capacitors integrated on the upper surface of the first substrate, and the first bonding layer formed on the capacitor array; as well as The second structure includes a second substrate, an access array and a second bonding layer, wherein the second substrate has an upper surface and a lower surface, the access array has a plurality of access transistors integrated on the upper surface of the second substrate, and the second bonding layer is formed on the lower surface of the second substrate and bonded to the first bonding layer.

2. The stacked semiconductor memory device according to claim 1, wherein: The first bonding layer comprises: a plurality of first bonding pads electrically connected to the plurality of capacitors, respectively; and A first bonding insulation layer electrically isolates the first bonding pads from each other.

3. The stacked semiconductor memory device according to claim 2, wherein: The second bonding layer comprises: a plurality of second bonding pads hybrid-bonded to the first bonding pad and electrically connected to the plurality of access transistors, respectively; and A second bonding insulating layer is hybrid-bonded to the first bonding insulating layer and electrically isolates the second bonding pads from each other.

4. The stacked semiconductor memory device according to claim 3, wherein: The capacitor array has a size corresponding to a size of the access array.

5. The stacked semiconductor memory device according to claim 4, wherein: The second structure also includes an embedded electrode in the second substrate to connect the access transistor to the second bonding pad.

6. The stacked semiconductor memory device according to claim 3, wherein: The second structure also includes: a plurality of transistors arranged on the periphery of the access array; and A peripheral circuit block includes a plurality of interconnects electrically connected to the transistor.

7. The stacked semiconductor memory device according to claim 6, wherein: The capacitor array has a size corresponding to the size of the access array and the peripheral circuit block.

8. The stacked semiconductor memory device according to claim 7, wherein: The second structure also includes: a plurality of embedded electrodes disposed in the second substrate to be coupled to the access transistor; and A plurality of wiring lines are connected between the embedded electrode and the second bonding pad.

9. The stacked semiconductor memory device according to claim 6, wherein: The first structure also includes a plurality of micro-capacitors, Wherein, the plurality of micro capacitors are arranged to face the peripheral circuit block of the second structure.

10. The stacked semiconductor memory device according to claim 9, wherein: The plurality of micro capacitors are formed at the same plane as the capacitor, and a shape of the micro capacitors is the same as or different from a shape of the capacitor.

11. A stacked semiconductor memory device, comprising: A first substrate including a plurality of unit capacitors; as well as a second substrate including a plurality of word lines, a plurality of bit lines, and access transistors, the plurality of bit lines intersecting the plurality of word lines, and the access transistors connected to intersections between the word lines and the bit lines, At least one of the first substrate and the second substrate includes a plurality of hybrid bonding pads, and the plurality of hybrid bonding pads are connected between the cell capacitor and the access transistor to form a memory cell array.

12. The stacked semiconductor memory device according to claim 11, in, the second substrate includes a peripheral circuit block including a plurality of interconnects and a plurality of transistors connected to the word lines and the bit lines, The peripheral circuit block is integrated on the second substrate, and the access transistor, the word line and the bit line are integrated on the second substrate.

13. The stacked semiconductor memory device according to claim 12, wherein: The first substrate further includes a plurality of micro capacitors arranged at a region corresponding to the peripheral circuit block.

14. The stacked semiconductor memory device according to claim 13, further comprising: a first bonding layer formed on the unit capacitor and the micro-capacitor of the first substrate; as well as a second bonding layer formed on the second substrate facing the first substrate to be bonded to the first bonding layer, Wherein, the first bonding layer and the second bonding layer include the plurality of hybrid bonding pads.

15. The stacked semiconductor memory device according to claim 13, wherein: The capacitance of each of the micro-capacitors is substantially equal to the capacitance of each of the unit capacitors.

16. The stacked semiconductor memory device according to claim 13, wherein: A capacitance of at least one of the micro-capacitors is different from a capacitance of the unit capacitor.

17. A method for manufacturing a stacked semiconductor memory device, the method comprising: forming a plurality of unit capacitors on a surface of a first substrate; forming a first bonding insulating layer on the unit capacitor, the first bonding insulating layer comprising a plurality of first bonding pads electrically connected to the unit capacitor; forming a second bonding insulating layer on a surface of the second substrate, wherein the second bonding insulating layer includes a plurality of second bonding pads; hybrid bonding the first substrate to the second substrate so that the first bonding pad contacts the second bonding pad; as well as A plurality of access transistors are formed on the other surface of the second substrate, and the access transistors are electrically connected to the second bonding pads.

18. The method according to claim 17, wherein: Forming the unit capacitor includes: forming a plate electrode on the first substrate; forming a dielectric layer on the plate electrode; forming a storage electrode on the dielectric layer; and The dielectric layer is crystallized at a first temperature.

19. The method according to claim 17, wherein: Hybrid bonding the first substrate and the second substrate comprises: bonding the first bonding insulating layer to the second bonding insulating layer; and The first bonding pad and the second bonding pad are heat-treated to expand the first bonding pad and the second bonding pad.

20. The method of claim 17, further comprising: Before forming the access transistor, an embedded electrode is formed in the second substrate to electrically connect the access transistor to the second bonding pad.

21. The method of claim 17, further comprising: Simultaneously with the formation of the access transistor, a plurality of transistors for peripheral circuit blocks are formed on the other surface of the second substrate.

22. The method according to claim 21, further comprising: while forming the unit capacitor, forming a plurality of micro capacitors on the one surface of the first substrate, Wherein, the micro capacitor is formed at a region corresponding to the transistor of the peripheral circuit block.

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