Payment circuit, chip and payment device

Abstract

The invention provides a payment circuit, a chip and payment equipment, and relates to the technical field of intelligent equipment. The circuit comprises an expansion circuit, a first switch, a second switch, a third switch, a first system circuit, a second system circuit and a first external interface. By controlling the opening and closing of each switch and cooperating with one expansion circuit, a first access between the first external interface and the first system circuit and a second access between the first external interface and the second system circuit are formed, and the host equipment can upgrade firmware in the first system circuit and firmware in the second system circuit at the same time, so that the firmware upgrading efficiency is improved. A third path is also formed between the first external interface and the first system circuit, and the first system circuit can interact with the OTG device. Corresponding functions are realized through cooperation of the switches, the number of expansion circuits is reduced, the cost is reduced, the wiring area of the payment circuit is effectively reduced, and the design requirements of high-integration-level and miniaturized electronic products are met.

Description

Technical Field

[0001] The present application relates to the technical field of smart devices, and in particular to a payment circuit, a chip and a payment device. Background Art

[0002] Current smart devices often contain multiple subsystems. For example, in payment devices, there are Android systems and payment systems. The Android system is mainly used to provide an operating system platform to support various payment-related applications and functions, and the payment system is mainly used to implement payment functions. In order to meet user needs and the product's universal serial bus (USB) functional requirements, it is usually necessary to connect various external devices to the payment device, such as a cash box, mouse, keyboard, barcode scanner, and printer. In addition, it is also necessary to upgrade the firmware of each subsystem of the payment device to ensure that it can optimize performance, add new functions, and fix errors and vulnerabilities.

[0003] In the related art, the payment device includes multiple hub integrated circuits (HUB ICs), each HUB IC is connected to a chip corresponding to a subsystem, so that an external device can be connected to the chip corresponding to the subsystem connected to the HUB IC through the HUB IC to implement the corresponding USB function. An external personal computer (PC) can also be connected to the subsystem connected to the HUB IC through the HUB IC to upgrade the firmware corresponding to the subsystem.

[0004] However, the demand for high integration and miniaturization of devices is increasing. The price of HUB IC is high, which leads to high cost of payment tablets. In addition, the area of ​​HUB IC is large, which occupies more wiring area, thus failing to meet the current demand for high integration and miniaturization of devices. Summary of the invention

[0005] The present application provides a payment circuit, a chip and a payment device to solve the problem that the HUB IC is expensive, resulting in a high cost of the payment device, and the HUB IC has a large area, resulting in a large wiring area, thereby failing to meet the current high integration and miniaturization requirements. While meeting the various functions of the payment device, it is possible to save components, reduce the cost of the payment device, reduce the wiring area, and meet the high integration and miniaturization requirements of the device.

[0006] In a first aspect, the present application provides a payment circuit, the payment circuit comprising: an expansion circuit, a first switch, a second switch, a third switch, a first system circuit, a second system circuit and a first external interface, the expansion circuit comprising an upstream interface, a first downstream interface and a second downstream interface, the first system circuit comprising a first serial interface, the first system circuit having a first firmware written therein, the first system circuit being used to carry an operating system, the second system circuit comprising a second serial interface, the second system circuit having a second firmware written therein, the second system circuit being used to carry a payment system, and the first external interface being used to connect to a host device or a plug-and-play OTG device;

[0007] The first end of the first switch is connected to the first external interface, the second end of the first switch is connected to the first end of the second switch, the third end of the first switch is connected to the third end of the third switch, the second end of the second switch is connected to the uplink interface, the first end of the third switch is connected to the first downlink interface, the second end of the third switch is connected to the first serial interface, and the second downlink interface is connected to the second serial interface;

[0008] When the payment circuit is in a closed state, the first end of the first switch is connected to the second end of the first switch, the first end of the second switch is connected to the second end of the second switch, the first end of the third switch is connected to the second end of the third switch, the first external interface, the first switch, the second switch, the uplink interface, the first downlink interface, the third switch and the first serial interface form a first path, and the first external interface, the first switch, the second switch, the uplink interface, the second downlink interface and the second serial interface form a second path, so that the host device can simultaneously perform firmware upgrade on the first firmware through the first path and on the second firmware through the second path;

[0009] When the payment circuit is in working state, the first system circuit is used to control the first end of the first switch to be connected with the third end of the first switch, and the third end of the third switch to be connected with the second end of the third switch, and the first external interface, the first switch, the third switch and the first serial interface form a third path, so that the first system circuit can interact with the OTG device through the third path, or so that the host device can debug the operating system through the third path.

[0010] The payment circuit provided in the first aspect controls the opening and closing of the first switch, the second switch and the third switch, and cooperates with an expansion circuit, so that the payment circuit forms a first path between the first external interface and the first system circuit, and a second path between the first external interface and the second system circuit in the closed state, so that the host device can simultaneously upgrade the first firmware in the first system circuit and the second firmware in the second system circuit through the first external interface. The payment circuit forms a third path between the first external interface and the first system circuit in the working state, so that the first system circuit can interact with the OTG device through the third path, or the host device can debug the operating system carried in the first system circuit through the third path. The circuit saves the HUB IC with a high price and a large occupied area by adding a low-cost and small-area analog switch, and while ensuring the host device's requirements for firmware upgrades for the first firmware in the first system circuit and the second firmware in the second system circuit at the same time, and the corresponding USB function of the payment circuit, it achieves cost reduction, effectively reduces the wiring area of ​​the payment circuit, and meets the design requirements of highly integrated and miniaturized electronic products.

[0011] In one possible design, the first system circuit further includes: a third serial interface, the first external interface being connected to the third serial interface;

[0012] The first external interface and the third serial interface form a fourth path, so that the host device can upgrade the first firmware through the fourth path when the payment circuit is in a closed state; or,

[0013] so that the host device can debug the operating system through the fourth path when the payment circuit is in working state; or

[0014] So that the first system circuit interacts with the OTG device through the fourth path when the payment circuit is in working state.

[0015] In one possible design, the payment circuit also includes: a signal conditioning circuit, a first end of the signal conditioning circuit is connected to the first external interface, a second end of the signal conditioning circuit is connected to the third serial interface, and the first external interface, the signal conditioning circuit and the third serial interface form the fourth path.

[0016] In one possible design, the payment circuit further includes: a second external interface, the second external interface is used to connect to the OTG device, the expansion circuit further includes: a third downstream interface, the first system circuit further includes: a fourth serial interface, the second external interface is connected to the third downstream interface, and the fourth serial interface is connected to the third end of the second switch;

[0017] When the payment circuit is in a working state, the first system circuit is also used to control the second end of the second switch and the third end of the second switch to be connected, and the fourth serial interface, the second switch, the upstream interface, the third downstream interface and the second external interface form a fifth path, so that the first system circuit interacts with the OTG device through the fifth path.

[0018] In one possible design, the payment circuit further includes: a third external interface, the third external interface is used to connect to the OTG device, and the expansion circuit further includes: a fourth downstream interface, the third external interface is connected to the fourth downstream interface;

[0019] When the payment circuit is in working state, the fourth serial interface, the second switch, the upstream interface, the fourth downstream interface and the third external interface form a sixth path, so that the first system circuit interacts with the OTG device through the sixth path.

[0020] In one possible design, the first external interface is a Universal Serial Bus Type-C USB TYPE-C interface.

[0021] In a possible design, the second external interface and the third external interface are pogo pin interfaces, and the second external interface, the third external interface and the fourth serial interface support Universal Serial Bus 2.0 USB2.0.

[0022] In one possible design, the first switch, the second switch, the third switch, the first serial interface and the second serial interface support Universal Serial Bus 2.0 USB2.0, and the third serial interface supports Universal Serial Bus 3.1 USB3.1.

[0023] In a second aspect, the present application provides a payment chip, comprising: the payment circuit in the first aspect and any possible design of the first aspect.

[0024] In a third aspect, the present application provides a payment device, comprising: the payment circuit in the first aspect and any possible design of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0026] Figure 1 A schematic diagram of the structure of a payment device provided in an embodiment of the present application.

[0027] Figure 2 A schematic diagram of the structure of a payment circuit provided in one embodiment of the present application.

[0028] Figure 3 A schematic diagram of the structure of a payment circuit provided in one embodiment of the present application.

[0029] Figure 4 A schematic diagram of the structure of a payment circuit provided in one embodiment of the present application.

[0030] Figure 5 A schematic diagram of the structure of a payment circuit provided in one embodiment of the present application.

[0031] Figure 6 A schematic diagram of the structure of a payment circuit provided in one embodiment of the present application.

[0032] Figure 7 A schematic diagram of the structure of a payment circuit provided in one embodiment of the present application. DETAILED DESCRIPTION

[0033] In this application, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c alone can represent: a, b, c, a and b, a and c, or a, b, and c, where a, b, and c can be single or multiple. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0034] The directions or positional relationships indicated by terms such as "center", "longitudinal", "lateral", "up", "down", "left", "right", "front", and "back" are based on the directions or positional relationships shown in the accompanying drawings and are only for the convenience of describing the present application and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present application.

[0035] The terms "connected" and "connected" should be understood in a broad sense. For example, the "connected" or "connected" of a circuit structure can refer to not only physical connection, but also electrical connection or signal connection. For example, it can be directly connected, that is, physically connected, or indirectly connected through at least one intermediate element, as long as the circuit is connected, or it can be the internal connection of two elements; signal connection can refer to signal connection through a circuit or through a media medium, such as radio waves. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0036] In related technologies, such as Figure 1 As shown, the payment device includes an Android chip, a payment chip, HUB IC 1, HUB IC2, a switch S1, a switch S2, an external interface A, an external interface B, and an external interface C. The Android chip is equipped with an Android system, which is used to provide an operating system platform and support various payment-related applications and functions.

[0037] Among them, the payment chip is used to carry the payment system, and the payment system is used to realize the payment function.

[0038] Among them, Android firmware is written into the Android chip, and payment firmware is written into the payment system. The firmware is used to directly drive and call the Android chip or payment chip hardware to ensure the normal operation of the Android system or payment system.

[0039] Among them, HUB IC 1 has two downstream interfaces: interface 11 and interface 12, interface 11 is connected to external interface A, interface 12 is connected to external interface B, the upstream interface of HUB IC 1 is connected to one end of the Android chip, the other end of the Android chip is connected to the first end of switch S2, one downstream interface of HUB IC 2: interface 21 is connected to the second end of switch S2, and another downstream interface of HUB IC 2: interface 22 is connected to the payment chip. The upstream interface of HUB IC 2 is connected to the first end of switch S1, and the second end of switch S1 is connected to external interface C. The third end of switch S2 is connected to the third end of switch S1.

[0040] It should be noted that Figure 1The states of the switch S1 and the switch S2 in the payment device shown are the states when the payment device is in the default state or the shutdown state. When the payment device is in the default state, or when the payment device is in the shutdown state, the first end of the switch S1 and the second end of the switch S1 are conductive, and the first end of the switch S2 and the second end of the switch S2 are conductive.

[0041] Based on this, when the payment device is in the default state, or when the payment device is in the shutdown state, the external PC can be connected to the Android chip through the external interface A or the external interface B, and the HUB IC 1, so as to upgrade the Android firmware. At the same time, the external PC can be connected to the payment chip through the external interface C, the switch S1, and the HUB IC 2, so as to upgrade the payment firmware.

[0042] When the payment device is in working state, the Android chip controls the first end of switch S2 and the third end of switch S2 to be turned on, and controls the second end of switch S1 and the third end of switch S1 to be turned on, forming a path from external interface C, switch S1, switch S2 to the Android chip. External devices such as a money box, mouse, keyboard, barcode scanner and printer can be connected to the Android chip through external interface A, external interface B or external interface C at the same time, thereby realizing the corresponding USB function.

[0043] However, in Figure 1 For Android chips and payment chips, two HUB ICs and three external interfaces are needed to work together to realize multiple USB functions and firmware upgrades. However, the HUB IC is expensive, which leads to a high cost for the payment tablet. In addition, the HUB IC has a large area, which occupies a large wiring area and cannot meet the current demand for high integration and miniaturization of equipment.

[0044] Exemplarily, the present application provides a payment circuit, chip and payment device, which adds a low-cost and small-area analog switch in the payment circuit, eliminating a HUB IC. Through the cooperation of three analog switches and a HUB IC, when the payment circuit is in the closed state, the firmware upgrade of the payment firmware and the Android firmware is realized at the same time, and when the payment circuit is in the working state, the external device is connected to the Android system from the external interface, while meeting the various functions of the payment device, saving components, reducing the cost of the payment device, reducing the wiring area, and meeting the requirements of high integration and miniaturization of the device.

[0045] Next, combine Figures 2 to 7 , a detailed description of the payment circuit provided in this application is given.

[0046] See also Figure 2 , Figure 2 This is a schematic diagram of a payment circuit provided in one embodiment of the present application. Figure 2As shown, the payment circuit 1 includes: an expansion circuit 10 , a first switch 20 , a second switch 30 , a third switch 40 , a first system circuit 50 , a second system circuit 60 and a first external interface 70 .

[0047] The expansion circuit 10 includes an uplink interface 11 , a first downlink interface 12 and a second downlink interface 13 .

[0048] The expansion circuit 10 is used to expand the USB interface, and can expand the USB interface connected to the upstream interface 11 into multiple interfaces. It should be noted that the present application does not limit the number of downstream interfaces of the expansion circuit 10. Figure 2 The expansion circuit 10 shown is an expansion circuit with one upstream interface and two downstream interfaces, that is, the input of one upstream interface 11 can be expanded to two downstream interfaces: a first downstream interface 12 and a second downstream interface 13. Of course, the expansion circuit 10 can also be an expansion circuit with one upstream interface and three downstream interfaces, or one upstream interface and four downstream interfaces.

[0049] The expansion circuit 10 may support USB 1.1, USB 2.0, USB 3.0, USB 3.1 Gen 1 or USB 3.1 Gen 2.

[0050] In some examples, the model of the expansion circuit 10 may be USB2514B. USB2514B is a low-power, high-performance hub, and has a small footprint, which can reduce the wiring area of ​​the payment circuit 1 and improve the performance of the payment circuit 1.

[0051] Among them, the first switch 20, the second switch 30, and the third switch 40 are all dual-channel analog switches. Figure 2 The first switch 20, the second switch 30, and the third switch 40 shown are states when the payment circuit 1 is in a closed state. The solid lines in the first switch 20, the second switch 30, and the third switch 40 represent a connected state, and the dotted lines represent a disconnected state.

[0052] The payment circuit 1 being in the off state can also be understood as the payment circuit 1 being in the default state or the shutdown state. When the payment circuit 1 is in the off state, it can be controlled by other host devices as a slave device. When the payment circuit 1 is in the off state, the default connection state of the first switch 20, the second switch 30, and the third switch 40 is Figure 2 In addition, the payment circuit 1 being in a working state can also be understood as the payment circuit 1 being in an on state or a powered-on state. When the payment circuit 1 is in a working state, it can be controlled by other host devices as a slave device, or it can be controlled by other devices as a host device.

[0053] The first system circuit 50 includes a first serial interface 51 , and the first system circuit 50 is used to carry an operating system, so that the first system circuit 50 can provide an operating system that is convenient for users to operate.

[0054] The first system circuit 50 may be a central processing unit (CPU), such as a Snapdragon series processor, a Dimensity series processor, an Apple series processor, or an Intel processor.

[0055] The operating system can be Android system, Windows system, Hongmeng system, Mac OS system, Unix system or Linux system, etc.

[0056] The first system circuit 50 also includes a non-volatile memory, in which the first firmware is written, and the first firmware provides the lowest level of control logic for the first system circuit 50. The first firmware is usually not directly accessible or modifiable by the user. The first firmware is mainly used to directly drive and call the hardware in the first system circuit 50 to ensure the normal operation of the first system circuit 50.

[0057] The first serial interface 51 is a USB interface, and the first serial interface 51 supports USB 2.0.

[0058] The second system circuit 60 includes a second serial interface 61 , and the second system circuit 60 is used to carry a payment system, so that the second system circuit 60 can realize a payment function.

[0059] The second system circuit 60 may be, for example, a UNISOC 7861 chip.

[0060] The second system circuit 60 also includes a non-volatile memory, in which a second firmware is written, and the second firmware provides the lowest level of control logic for the second system circuit 60. The second firmware is usually not directly accessible or modifiable by the user. The second firmware is mainly used to directly drive and call the hardware in the second system circuit 60 to ensure the normal operation of the second system circuit 60.

[0061] The second serial interface 61 is a USB interface, and the second serial interface 61 supports USB 2.0.

[0062] The first external interface 70 is used to connect to a host device or an On-The-Go (OTG) device.

[0063] The host device is, for example, a PC. The OTG device is, for example, a cash box, a mouse, a keyboard, a barcode scanner, a printer, etc.

[0064] When the first external interface 70 is connected to a host device, the payment circuit 1 can be used as a slave device to implement corresponding functions. For example, when the first firmware and the second firmware in the payment circuit 1 are upgraded through an external PC, the external PC acts as a host device and the payment circuit 1 acts as a slave device. It should be noted that when the payment circuit 1 acts as a slave device, the payment circuit 1 can be in a working state or in a closed state.

[0065] When the first external interface 70 is connected to an OTG device, the payment circuit 1 can be used as a host device to implement corresponding functions. For example, when a keyboard is connected to the payment circuit 1 to implement the function of inputting user instructions, the keyboard is used as a slave device and the payment circuit 1 is used as a host device. It should be noted that when the payment circuit 1 is used as a host device, it is necessary to ensure that the payment circuit 1 is in a working state.

[0066] The following describes the connection relationship between the various parts.

[0067] Among them, the first end of the first switch 20 is connected to the first external interface 70, the second end of the first switch 20 is connected to the first end of the second switch 30, the third end of the first switch 20 is connected to the third end of the third switch 40, the second end of the second switch 30 is connected to the upstream interface 11, the first end of the third switch 40 is connected to the first downstream interface 12, the second end of the third switch 40 is connected to the first serial interface 51, and the second downstream interface 13 is connected to the second serial interface 61.

[0068] When the payment circuit is in the closed state, the first end of the first switch 20 is connected to the second end of the first switch 20 , the first end of the second switch 30 is connected to the second end of the second switch 30 , and the first end of the third switch 40 is connected to the second end of the third switch 40 .

[0069] Based on this, the first external interface 70, the first switch 20, the second switch 30, the upstream interface 11, the first downstream interface 12, the third switch 40 and the first serial interface 51 form a first path, and the first external interface 70, the first switch 20, the second switch 30, the upstream interface 11, the second downstream interface 13 and the second serial interface 61 form a second path.

[0070] If the host device is connected to the first external interface 70 and the payment circuit 1 serves as a slave device, the host device can simultaneously upgrade the first firmware through the first path and the second firmware through the second path, thereby improving the efficiency of the firmware upgrade.

[0071] Specifically, the host device is connected to the first external interface 70. Before the host device performs a firmware upgrade, the host device shakes hands with the first system circuit 50 through the first path and shakes hands with the second system circuit 50 through the second path to ensure that the first path and the second path can be used for firmware upgrade. The host device sends a first firmware upgrade signal and a second firmware upgrade signal. When the first firmware upgrade signal and the second firmware upgrade signal are transmitted to the upstream interface 11, the expansion circuit 10 can identify the first firmware upgrade signal and the second firmware upgrade signal, and output the signal for the first firmware upgrade through the first downstream interface 12, and output the signal for the second firmware upgrade through the second downstream interface 13, so that the first firmware and the second firmware can be upgraded.

[0072] Among them, by adding the target address in the first firmware upgrade signal and the second firmware upgrade signal in advance, the expansion circuit 10 can identify the signal according to the target address, ensuring that the expansion circuit 10 can transmit the correct signal to the corresponding downlink interface.

[0073] When the payment circuit is in working state, the first system circuit 50 can control the first end of the first switch 20 to be connected to the third end of the first switch 20, and the third end of the third switch 40 to be connected to the second end of the third switch 40. When the payment circuit is in working state, the states of the first switch 20, the second switch 30, and the third switch 40 can be as follows: Figure 3 As shown, Figure 3 The solid lines in the first switch 20, the second switch 30, and the third switch 40 represent conduction, and the dotted lines represent disconnection.

[0074] Based on this, the first external interface 70, the first switch 20, the third switch 40 and the first serial interface form a third path.

[0075] Accordingly, the first path and the second path are disconnected.

[0076] In some examples, the first system circuit 50 is also connected to the control end of the first switch 20 , the control end of the second switch 30 , and the control end of the third switch 40 , so as to control the opening and closing of the first switch 20 , the second switch 30 , and the third switch 40 .

[0077] When the payment circuit is in operation, the second path is disconnected, which can ensure that the payment system is disconnected from the outside, thereby ensuring the security of the payment system.

[0078] If the host device is connected to the first external interface 70 and the payment circuit 1 serves as a slave device, the host device can debug the operating system through the third path.

[0079] If the OTG device is connected to the first external interface 70 and the payment circuit 1 serves as a host device, the first system circuit 50 can interact with the OTG device through the third path.

[0080] In the embodiment of the present application, by controlling the opening and closing of the first switch, the second switch and the third switch, in cooperation with an expansion circuit, the payment circuit forms a first path between the first external interface and the first system circuit, and a second path between the first external interface and the second system circuit in the closed state, so that the host device can simultaneously upgrade the first firmware in the first system circuit and the second firmware in the second system circuit through the first external interface. The payment circuit forms a third path between the first external interface and the first system circuit in the working state, so that the first system circuit can interact with the OTG device through the third path, or the host device can debug the operating system carried in the first system circuit through the third path. The circuit saves the HUB IC with a high price and a large occupied area by adding a low-cost and small-area analog switch, and while ensuring the host device's requirements for firmware upgrades for the first firmware in the first system circuit and the second firmware in the second system circuit at the same time, and the corresponding USB function of the payment circuit, it achieves cost reduction, effectively reduces the wiring area of ​​the payment circuit, and meets the design requirements of highly integrated and miniaturized electronic products.

[0081] Based on the above exemplary description, Figure 4 This is a schematic diagram of a payment circuit provided in one embodiment of the present application. Figure 4 As shown, the first system circuit 50 further includes: a third serial interface 52 , and the first external interface 70 is connected to the third serial interface 52 .

[0082] When the payment circuit 1 is in a closed state or in a working state, the first external interface 70 and the third serial interface 52 can both form a fourth path.

[0083] The host device can upgrade the first firmware through the fourth path when the payment circuit 1 is in the closed state. For specific methods of upgrading the firmware, please refer to Figure 2 The relevant description in the embodiments will not be repeated here.

[0084] Of course, the host device can also debug the operating system through the fourth path when the payment circuit 1 is in working state.

[0085] In addition, the first system circuit 50 can directly interact with the OTG device through the fourth path when the payment circuit 1 is in the working state.

[0086] Based on this, when the first firmware in the first system circuit 50 is upgraded, it can be upgraded not only through the first path, but also directly through the fourth path. When interacting with an external OTG device, the first system circuit 50 can also choose between the third path or the fourth path, thereby improving the flexibility of the payment circuit.

[0087] In some examples, the third serial interface 52 supports USB 3.1. Therefore, the fourth path is a path supporting USB 3.1, which has a high speed, thereby increasing the speed of firmware upgrade or device interaction.

[0088] Based on the above exemplary description, Figure 5 This is a schematic diagram of a payment circuit provided in one embodiment of the present application. Figure 5 As shown, the payment circuit 1 also includes: a signal conditioning circuit 80.

[0089] The first end of the signal conditioning circuit 80 is connected to the first external interface 70 , the second end of the signal conditioning circuit 80 is connected to the third serial interface 52 , and the first external interface 70 , the signal conditioning circuit 80 and the third serial interface 52 form a fourth path.

[0090] Among them, the signal conditioning circuit 80 is used to improve the quality of the signal passing through the fourth path, ensuring that the signal smoothly reaches the third serial interface 52 or the first external interface 70, thereby improving the quality of interaction between the payment circuit 1 and the external OTG device, and the stability of the host device performing firmware upgrades on the first firmware.

[0091] The signal conditioning circuit 80 may be TUSB211A or the like.

[0092] Based on the above exemplary description, Figure 6 This is a schematic diagram of a payment circuit provided in one embodiment of the present application. Figure 6 As shown, the payment circuit 1 further includes: a second external interface 90. The expansion circuit 10 further includes: a third downlink interface 14, and the first system circuit 50 further includes: a fourth serial interface 53. It should be noted that: Figure 6 The structure shown is in Figure 5 Based on the example, of course, Figure 6 The structure can also be Figure 2 or Figure 4 An example is given based on .

[0093] The second external interface 90 is connected to the third downlink interface 14 , and the fourth serial interface 53 is connected to the third end of the second switch 30 .

[0094] The second external interface 90 is used to connect to an On-The-Go (OTG) device.

[0095] The fourth serial interface 53 is a USB interface, and the fourth serial interface 53 supports USB 2.0.

[0096] When the payment circuit is in working state, the first system circuit is also used to control the second end of the second switch 30 and the third end of the second switch 30 to be turned on.

[0097] Based on this, the fourth serial interface 53, the second switch 30, the uplink interface 11, the third downlink interface 14 and the second external interface 90 form a fifth path.

[0098] Thus, the first system circuit 50 can interact with the OTG device through the fifth path.

[0099] In addition, when the payment circuit is in the closed state, the fifth path is disconnected.

[0100] Based on this, another path can be added to the payment circuit 1, so that more OTG devices can be connected to the payment circuit 1 to work, thereby realizing more extended functions and improving the flexibility of the payment circuit 1.

[0101] Based on the above exemplary description, Figure 7 This is a schematic diagram of a payment circuit provided in one embodiment of the present application. Figure 7 As shown, the payment circuit 1 further includes: a third external interface 110. The expansion circuit 10 further includes: a fourth downstream interface 15.

[0102] The third external interface 110 is used to connect to an OTG device.

[0103] When the payment circuit is in working state, the fourth serial interface, the second switch, the upstream interface, the fourth downstream interface and the third external interface form a sixth path.

[0104] Based on this, the first system circuit 50 can interact with the OTG device through the sixth path.

[0105] In addition, when the payment circuit is in the closed state, the sixth path is disconnected.

[0106] Based on this, another path can be added to the payment circuit 1, so that more OTG devices can be connected to the payment circuit 1 to work, thereby realizing more extended functions and improving the flexibility of the payment circuit 1.

[0107] Based on the above exemplary description, the first external interface 70 is a USB TYPE-C interface. Therefore, through the first external interface 70, a path supporting USB 2.0 can be established, and a path supporting USB 3.1 can also be established, which improves the flexibility of the payment circuit 1.

[0108] Based on the above exemplary description, the second external interface 90 and the third external interface 110 are POGO pin interfaces. The second external interface 90, the third external interface 110 and the fourth serial interface 53 support USB 2.0.

[0109] Based on the above exemplary description, the first switch 20 , the second switch 30 , the third switch 30 , the first serial interface 51 and the second serial interface 61 support USB 2.0, and the third serial interface 52 supports USB 3.1.

[0110] It should be noted that when the payment circuit 1 is in the off state, the payment circuit 1 defaults to a slave device, and when the payment circuit 1 is in the working state, the payment circuit 1 defaults to a slave device. If an external device is connected to the first external interface 70, the second external interface 90 or the third external interface 110, the payment circuit 1 can be converted into a host device or remain a slave device unchanged according to the type of the connected external device.

[0111] Based on this, through the payment circuit 1, a total of one USB3.1 channel for upgrading the first firmware can be established: the fourth channel when the payment circuit is in the closed state; one USB3.1 channel for interacting with the OTG device or for debugging the host device: the fourth channel when the payment circuit is in the working state; one USB2.0 channel for upgrading the first firmware: the first channel when the payment circuit is in the closed state; one USB2.0 channel for upgrading the second firmware: the second channel when the payment circuit is in the closed state; one USB2.0 channel for interacting with the OTG device or for debugging the host device: the third channel when the payment circuit is in the working state; one USB2.0 channel for interacting with the OTG device: the fifth channel when the payment circuit is in the working state; one USB2.0 channel for interacting with the OTG device: the sixth channel when the payment circuit is in the working state. Therefore, the payment circuit 1 can not only realize the upgrade of the first firmware and the second firmware at the same time in the closed state, but also realize the function of multiple OTG devices working at the same time.

[0112] Illustratively, the present application also provides a payment chip that integrates the payment circuit provided by any of the above embodiments.

[0113] Exemplarily, an embodiment of the present application further provides a payment device, comprising: the payment circuit provided in the aforementioned embodiment.

[0114] It should be noted that the payment device of the embodiment of the present application can be used to implement the technical solution of the above-mentioned payment circuit embodiment, and its implementation principle and technical effect are similar, which will not be repeated here.

[0115] In the several embodiments provided in this application, it should be understood that the disclosed circuits, modules, and devices can be implemented in other ways. For example, the circuit embodiments described above are only schematic, for example, the division of modules or units is only a logical function division, and there may be other division methods in actual implementation, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed.

[0116] Those skilled in the art will appreciate that, although some embodiments herein include certain features included in other embodiments, the combination of features of different embodiments is meant to be within the scope of the present application and form different embodiments. For example, in the claims, any one of the claimed embodiments may be used in any combination.

[0117] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A payment circuit, characterized in that: The payment circuit includes: an expansion circuit, a first switch, a second switch, a third switch, a first system circuit, a second system circuit and a first external interface, the expansion circuit includes an upstream interface, a first downstream interface and a second downstream interface, the first system circuit includes a first serial interface, the first system circuit is written with a first firmware, the first system circuit is used to carry an operating system, the second system circuit includes a second serial interface, the second system circuit is written with a second firmware, the second system circuit is used to carry a payment system, and the first external interface is used to connect to a host device or a plug-and-play OTG device; The first end of the first switch is connected to the first external interface, the second end of the first switch is connected to the first end of the second switch, the third end of the first switch is connected to the third end of the third switch, the second end of the second switch is connected to the uplink interface, the first end of the third switch is connected to the first downlink interface, the second end of the third switch is connected to the first serial interface, and the second downlink interface is connected to the second serial interface; When the payment circuit is in a closed state, the first end of the first switch is connected to the second end of the first switch, the first end of the second switch is connected to the second end of the second switch, the first end of the third switch is connected to the second end of the third switch, the first external interface, the first switch, the second switch, the uplink interface, the first downlink interface, the third switch and the first serial interface form a first path, and the first external interface, the first switch, the second switch, the uplink interface, the second downlink interface and the second serial interface form a second path, so that the host device can simultaneously perform firmware upgrade on the first firmware through the first path and on the second firmware through the second path; When the payment circuit is in working state, the first system circuit is used to control the first end of the first switch to be connected with the third end of the first switch, and the third end of the third switch to be connected with the second end of the third switch, and the first external interface, the first switch, the third switch and the first serial interface form a third path, so that the first system circuit can interact with the OTG device through the third path, or so that the host device can debug the operating system through the third path.

2. The circuit according to claim 1, characterized in that The first system circuit further includes: a third serial interface, the first external interface being connected to the third serial interface; The first external interface and the third serial interface form a fourth path, so that the host device can upgrade the first firmware through the fourth path when the payment circuit is in a closed state; or, so that the host device can debug the operating system through the fourth path when the payment circuit is in working state; or So that the first system circuit interacts with the OTG device through the fourth path when the payment circuit is in working state.

3. The circuit according to claim 2, characterized in that The payment circuit also includes: a signal conditioning circuit, a first end of the signal conditioning circuit is connected to the first external interface, a second end of the signal conditioning circuit is connected to the third serial interface, and the first external interface, the signal conditioning circuit and the third serial interface form the fourth path.

4. The circuit according to any one of claims 1 to 3, characterized in that: The payment circuit further includes: a second external interface, the second external interface is used to connect to the OTG device, the expansion circuit further includes: a third downstream interface, the first system circuit further includes: a fourth serial interface, the second external interface is connected to the third downstream interface, and the fourth serial interface is connected to the third end of the second switch; When the payment circuit is in a working state, the first system circuit is also used to control the second end of the second switch and the third end of the second switch to be connected, and the fourth serial interface, the second switch, the upstream interface, the third downstream interface and the second external interface form a fifth path, so that the first system circuit interacts with the OTG device through the fifth path.

5. The circuit according to claim 4, characterized in that The payment circuit further includes: a third external interface, the third external interface is used to connect to the OTG device, and the expansion circuit further includes: a fourth downstream interface, the third external interface is connected to the fourth downstream interface; When the payment circuit is in working state, the fourth serial interface, the second switch, the upstream interface, the fourth downstream interface and the third external interface form a sixth path, so that the first system circuit interacts with the OTG device through the sixth path.

6. The circuit according to any one of claims 1 to 3, characterized in that: The first external interface is a Universal Serial Bus Type-C USB TYPE-C interface.

7. The circuit according to claim 5, characterized in that The second external interface and the third external interface are pogo pin interfaces, and the second external interface, the third external interface and the fourth serial interface support Universal Serial Bus 2.0 USB2.

0.

8. The circuit according to claim 2 or 3, characterized in that: The first switch, the second switch, the third switch, the first serial interface and the second serial interface support Universal Serial Bus 2.0 USB 2.0, and the third serial interface supports Universal Serial Bus 3.1 USB 3.

1.

9. A payment chip, characterized in that: include: A payment circuit as claimed in any one of claims 1 to 7.

10. A payment device, characterized in that: include: A payment circuit as claimed in any one of claims 1 to 7.

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