Flash memory structure

Abstract

A flash memory structure includes an active region and a shallow trench isolation structure, in which the active region includes a source line doped region extending in a first direction and a plurality of branch doped regions extending in a second direction, located on both sides of the source line doped region and arranged alternately along the first direction. The branch doped regions are separated by the shallow trench isolation structures. An erase gate is located on the source line doped region and extends towards the first direction, a plurality of floating gates are located on the branch doped regions on the two sides of the erase gate, and two word lines are located on the outer sides of the two floating gates respectively and extend towards the first direction to pass through the branch doped regions.

Description

Technical Field

[0001] The present invention relates to a flash memory structure, and more particularly to a flash memory structure with branch doping regions arranged alternately. Background Art

[0002] Flash memory is a non-volatile electronic storage medium that can be erased and reprogrammed. It is widely used in a variety of commercial or military electronic devices or equipment. In order to store data, flash memory has an addressable memory cell array, which is generally composed of floating gate transistors. Common flash memory cells include stacked gate memory cell design or split gate memory cell design, such as the 3rd generation embedded super flash (ESF3). The split gate memory cell design has many advantages over the stacked gate memory cell design, such as low energy consumption, high injection efficiency, and is not susceptible to short channel effects and over-erasure.

[0003] Nowadays, the scale of semiconductor components is constantly shrinking, especially in memory components, to provide larger storage capacity under the unit layout area. As the size shrinks, the distance between adjacent floating gates in flash memory is getting smaller and smaller, and the tolerance space of related manufacturing processes is also getting smaller and smaller. In this case, the shallow trench isolation structure responsible for isolation is prone to not achieve its due isolation effect due to the variation of the manufacturing process, so that adjacent floating gates are connected to each other and short-circuited. Therefore, technical personnel in this field must improve the existing flash memory structure and manufacturing process in order to solve the above problems. Summary of the invention

[0004] In view of the above-mentioned needs, the present invention proposes a novel flash memory structure, which is characterized by having branch doping regions alternately arranged on both sides of the source line, so as to avoid existing problems such as adjacent floating gate short circuits or relative shallow trench isolation structure bridging, while increasing the manufacturing process tolerance and reducing the area required for the storage unit.

[0005] One object of the present invention is to provide a flash memory structure, which includes a semiconductor substrate, an active region and a shallow trench isolation structure, wherein the active region includes a source line doping region extending in a first direction and a plurality of branch doping regions extending in a second direction, which are located on both sides of the source line doping region and are alternately arranged along the first direction, and the branch doping regions are separated by the shallow trench isolation structures. An erase gate is located on the source line doping region and extends in the first direction. A plurality of floating gates are located on the branch doping regions on both sides of the erase gate, and two word lines are respectively located outside the two floating gates and extend in the first direction through the plurality of branch doping regions.

[0006] Another object of the present invention is to provide a flash memory structure, which includes a semiconductor substrate, an active region and a shallow trench isolation structure, wherein the active region includes a source line doping region extending in a first direction and a plurality of branch doping regions extending in a second direction and located on both sides of the source line doping region, and the branch doping regions are separated by the shallow trench isolation structures. An erase gate is located on the source line doping region and extends in the first direction, a plurality of floating gates are located on the branch doping regions on both sides of the erase gate, two word lines are respectively located outside the two floating gates and extend in the first direction through the plurality of branch doping regions, and a first metal layer is located on the semiconductor substrate, the first metal layer has a plurality of metal line patterns, wherein each of the metal line patterns has a bending portion located directly above the source line doping region and two straight portions respectively connected to both ends of the bending portion and directly above the two branch doping regions located on both sides of the source line doping region and extending in the second direction.

[0007] These and other objects of the present invention will become more apparent to the reader after reading the following detailed description of the preferred embodiment which is described in various figures and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A schematic diagram of a layout pattern of a storage unit block of a flash memory in a preferred embodiment of the present invention;

[0009] Figure 2 A cross-sectional schematic diagram of a flash memory structure in a preferred embodiment of the present invention;

[0010] Figure 3 A three-dimensional schematic diagram of a flash memory structure in a preferred embodiment of the present invention;

[0011] Figure 4 A schematic diagram of the layout pattern of each zone of a flash memory in a preferred embodiment of the present invention;

[0012] Figure 5 A schematic diagram of the global layout of a flash memory storage block in a preferred embodiment of the present invention; and

[0013] Figure 6 Schematic diagram of the layout pattern of the first metal layer and the second metal layer of each zone of a flash memory in a preferred embodiment of the present invention.

[0014] Please note that all illustrations in this manual are of a legend nature. For the sake of clarity and convenience of illustration, the components in the illustrations may be exaggerated or reduced in size and proportion. Generally speaking, the same reference symbols in the figures will be used to indicate corresponding or similar component features after modification or in different embodiments.

[0015] Explanation of symbols

[0016] 10 Storage Cell Blocks

[0017] 20-line zone

[0018] 30 Erase gate band

[0019] 40 Source Line Zone

[0020] 50 Control grid zone

[0021] 100 Semiconductor substrate

[0022] 102 Active area

[0023] 102a Source line doping region

[0024] 102b Branch doping region

[0025] 102c Branch doping region

[0026] 104 Shallow Trench Isolation Structure

[0027] 106 bit line contacts

[0028] C1 storage unit

[0029] C2 Storage Unit

[0030] 108 interlayer dielectric layer

[0031] 112 Source Line Contact

[0032] 114 Word line contacts

[0033] 115 Opening

[0034] 116 Erase gate contact

[0035] 118 protrusion

[0036] 120 Control gate contact

[0037] BL bit line

[0038] CG Control Grid

[0039] D Drain

[0040] D1 First direction

[0041] D2 Second direction

[0042] EG Erase Gate

[0043] FG Floating Gate

[0044] M1 First Metal Layer

[0045] M1a bend

[0046] M1b Straight part

[0047] M2 Second Metal Layer

[0048] S Source

[0049] SL Source Line Contact Area

[0050] WL Word Line DETAILED DESCRIPTION

[0051] Now, the exemplary embodiments of the present invention will be described in detail below, and the features described will be shown with reference to the accompanying drawings so that the reader can understand and achieve the technical effects. The reader will understand that the description in the text is only by way of example and is not intended to limit the present invention. The various embodiments of the present invention and the various features that do not conflict with each other in the embodiments can be combined or reset in various ways. Without departing from the spirit and scope of the present invention, modifications, equivalents or improvements to the present invention are understandable to those skilled in the art and are intended to be included in the scope of the present invention.

[0052] Readers should be able to easily understand that the meanings of "on", "over" and "above" in this case should be interpreted in a broad manner, so that "on" not only means "directly on" something but also includes the meaning of being "on" something with an intervening feature or layer, and "on" or "above" not only means "on" or "above" something but also includes the meaning of being "on" or "above" something with no intervening features or layers (i.e., directly on something). In addition, spatially related terms such as "under", "below", "lower", "over", "upper", etc. may be used herein for convenience of description to describe the relationship between one element or feature and another or more elements or features, as shown in the accompanying drawings.

[0053] As used herein, the term "substrate" refers to a material onto which subsequent materials are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0054] As used herein, the term "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent that is less than the extent of a lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness that is less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any horizontal faces at the top and bottom surfaces. A layer may extend horizontally, vertically and / or along an inclined surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers thereon, above and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductors and contact layers (where contacts, interconnects and / or vias are formed) and one or more dielectric layers.

[0055] The reader can generally understand the term at least in part from the usage in the context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as "a", "an", "the", or "said" can also be understood to convey singular usage or to convey plural usage. In addition, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, but can allow for the presence of additional factors that are not necessarily explicitly described, which also depends at least in part on the context.

[0056] The reader can further understand that when the words "include" and / or "contain" are used in this specification, they specify the existence of the stated features, regions, wholes, steps, operations, elements and / or parts, but do not exclude the possibility of the existence or addition of one or more other features, regions, wholes, steps, operations, elements, parts and / or their combinations.

[0057] Please refer to Figure 1, which is a schematic diagram of the layout pattern of a memory cell block 10 of a flash memory according to a preferred embodiment of the present invention, wherein the layout settings of the flash memory structure proposed by the present invention at the semiconductor front-end-of-line (FEOL) level, such as the active area, erase gate, control gate, word line, etc. Figure 1 As shown, the flash memory structure of the present invention has an active region 102 and shallow trench isolation structures 104 formed in a semiconductor substrate, wherein the active region 102 includes a source line doping region 102a extending in a first direction D1 as a main axis, and a plurality of branch doping regions 102b extending in a second direction D2 and connected to the source line doping region 102a, wherein the first direction D1 is preferably orthogonal to the second direction D2. The branch doping regions 102b are located on both sides of the source line doping region 102a and are alternately arranged along the first direction D1, and the branch doping regions 102b located on the same side and adjacent to each other are separated by the shallow trench isolation structures 104. Thus, each branch doping region 102b located on one side of the source line doping region 102a is opposite to a shallow trench isolation structure 104 located on the other side of the source line doping region 102a. In this preferred embodiment, the width of the branch doping region 102b and the shallow trench isolation structure 104 in the first direction D1 is the same, but not limited thereto.

[0058] Re-reference Figure 1 In the embodiment of the present invention, the semiconductor front-end layer also has structures such as an erase gate EG, a control gate CG, and a word line WL. Figure 1 As shown, an erase gate EG is located above the source line doping region 102a and extends in the first direction D1. The erase gate EG is preferably aligned with the long axis center line of the source line doping region 102a, and extends in the second direction D2 to cover part of the branch doping region 102b. Two control gates CG are respectively located on both sides of the erase gate EG and extend in the first direction D1 through multiple branch doping regions 102b. Two word lines WL are respectively located outside the two control gates CG and extend in the first direction D1 through multiple branch doping regions 102b. In addition, a bit line contact 106 is also provided on each branch doping region 102b outside the two word lines WL, which electrically connects each branch doping region 102b to the bit line above. In an embodiment of the present invention, a branch doping region 102b, including the erase gate EG, the control gate CG and the word line WL thereon, corresponds to a storage unit (bitcell), such as C1 and C2 shown in the figure. It can be seen that in the embodiment of the present invention, since the relative branch doping regions 102 b are staggered, the relative memory cells C1 , C2 are also staggered.

[0059] Now please refer to Figure 2 , which is a cross-sectional schematic diagram of a flash memory structure according to a preferred embodiment of the present invention, which allows readers to more clearly understand the component arrangement and relative positions of the flash memory structure of the present invention in a direction perpendicular to the substrate. Figure 2 So Figure 1 The cross-sectional view taken along the line AA' in FIG. 1 covers two opposite memory cells C1 and C2. Figure 2 As shown in FIG. 1 , the flash memory structure of the present invention is disposed on a semiconductor substrate 100. The semiconductor substrate 100 may be an N-type or P-type semiconductor substrate, such as a silicon bulk substrate or a silicon-on-insulator (SOI) substrate, but is not limited thereto. The semiconductor substrate 100 shown in FIG. 1 corresponds to Figure 1 The active region 102 in the memory structure includes two opposite and staggered branch doping regions 102b and a source line doping region 102a connecting the two branch doping regions 102b. The semiconductor substrate 102 is formed by ion implantation to form doping regions, such as a source S (i.e., source line sourceline) located in the center of the entire memory structure and a drain D located on both sides of the memory structure.

[0060] Re-reference Figure 2 In the embodiment of the present invention, the erase gate EG is located directly above the source S, and a floating gate FG and a control gate CG are provided on both sides of the erase gate EG in the second direction D2, wherein the floating gate FG is located above the semiconductor substrate 100, and the control gate CG is located above the floating gate FG. A word line WL is also provided outside the floating gate FG and the control gate CG. In the embodiment of the present invention, the erase gate EG, the source S (i.e., the source line), the control gate CG, and the word line WL all extend in the first direction D1 through a plurality of branch doping regions 102b, such as Figure 1 The floating gate FG is only located on the branch doping region 102b, as shown in FIG. Figure 3 As shown. The above components are isolated from each other by dielectric layers or films (such as silicon oxide, not numbered). In an embodiment of the present invention, the erase gate EG and the word line WL may be made of conductive metal or polysilicon, the floating gate FG and the control gate CG may be made of polysilicon, the dielectric layer between the floating gate FG and the control gate CG may be a silicon oxide-silicon nitride-silicon oxide multilayer structure (ONO), and the hard mask layer (not numbered) on the control gate CG may be a silicon nitride-silicon oxide-silicon nitride multilayer structure (NON). In addition, the drain D is arranged on the outside of the word line WL, and is connected to the upper bit line BL through a bit line contact 106. The entire memory structure is covered by an interlayer dielectric layer 108. It should be noted that although a control gate CG is provided in the memory structure of the present invention, a control gate is not provided in the design of some memory structures, and the present invention is not limited thereto.

[0061] Now please refer to Figure 3 , which is a three-dimensional schematic diagram of a flash memory structure according to a preferred embodiment of the present invention. It should be noted that in order to reveal the important components to be described in the figure, the erase gate EG and the word line WL in the structure are Figure 3 is omitted. Figure 3 As shown, in the embodiment of the present invention, the structures on both sides of the source line doping region 102a in the second direction D2 are basically the same, and the only difference is that the branch doping regions 102b on both sides are not arranged oppositely (opposite) but staggered (alternate), so that the branch doping region 102b on one side will be opposite to the shallow trench isolation structure 104 on the other side. The control gate CG will extend in the first direction D1 through multiple branch doping regions 102b and the floating gates FG located thereon. In the prior art, if the shallow trench isolation structure 104 between adjacent floating gates FG is not protruding enough toward the source line doping region 102a in the second direction D2 due to manufacturing process variation, it may not be able to achieve the effect of isolating the floating gates, resulting in the adjacent floating gates FG on the same side being connected to each other and short-circuited. On the other hand, if the problem is solved by reducing the width of the source line doping region 102a (i.e., making the shallow trench isolation structure 104 protrude toward the source line doping region 102a), the shallow trench isolation structure 104 may bridge with the shallow trench isolation structure 104 opposite to it and cut off the source line doping region 102a, causing component failure.

[0062] The advantage of the staggered design of the branch doping region 102b of the present invention is that the branch doping region 102b located on one side of the source line doping region 102a will be opposite to the shallow trench isolation structure 104 on the other side. In this way, even if the width of the source line doping region 102a is reduced, the shallow trench isolation structures 104 located on both sides of the source line doping region 102a will not bridge each other due to the misaligned positions, thereby solving the problems of floating gate short circuit and shallow trench isolation structure bridging at the same time. In addition, since the staggered design can improve the tolerance space of the manufacturing process, the width of the source line doping region 102a in the second direction D2 can be further reduced, or the neck length from the control gate CG to the source line doping region 102a can be increased, thereby reducing the required storage unit (such as Figure 1 The area C1, C2) shown is another great advantage of the present invention.

[0063] Now please refer to Figure 4 , which is a schematic diagram of the layout pattern of each zone of the flash memory at the semiconductor front-end level according to a preferred embodiment of the present invention. Figure 1 The layout pattern shown is mainly for the memory cell block 10 of the flash memory, and its layout pattern is composed of repeated, staggered, and branch doping regions 102b of the same length / width. Figure 4 The layout pattern of the word line zone 20, the erase gate zone 30, the source line zone 40 and the control gate zone 50 is similar to that of the Figure 1 The layout pattern of the memory cell block 10 shown is different.

[0064] First, in the word line zone 20. In the embodiment of the present invention, the word line zone 20 is designed to set the word line contact 114 and the source line contact 112. The word line WL position in the word line zone 20 will have a word line contact 114, which can electrically connect the word line WL to the first metal layer (not shown) above. The word line WL portion where the word line contact 114 is set can have a larger width in the second direction D2 to provide for the setting of the word line contact 114. The center of the word line zone 20 will have a source line contact region SL formed in the semiconductor substrate and connected to the source line doping region 102a and the branch doping region 102c on both sides. The width of the source line contact region SL in the second direction D2 will be greater than the source line doping region 102a to provide a larger landing area for the source line contact 112. The branch doping region 102c connected to the source line contact region SL will also have a misalignment feature, and its length in the second direction D2 will be shorter than the normal branch doping region 102b, and it will not be connected to the bit line contact 106, and is not used as a storage unit. The shorter branch doping region 102c can be regarded as a dummy pattern in the present invention. The source line contact region SL will be exposed from the opening 115 of the erase gate EG, and will have a source line contact 112 thereon to electrically connect the source line contact region SL to the first metal layer (not shown) above. The layout of the storage cell block 10 on both sides of the word line zone 20 has been described in detail. Figure 1 This has been explained in detail and I will not elaborate on it here.

[0065] Re-reference Figure 4 . The erase gate zone 30 is designed to be provided with an erase gate contact 116. The erase gate EG in the erase gate zone 30 has an erase gate contact 116, which can electrically connect the erase gate EG to the first metal layer (not shown) above. The source line doping region 102a in the erase gate zone 30 is the same as the memory cell region, and the branch doping region 102c therein also has a misalignment feature, and its length in the second direction D2 is smaller than that of a normal branch doping region 102b, and the bit line contact 106 is not connected thereto, and it is not used as a memory cell.

[0066] Re-reference Figure 4Regarding the source line zone 40, it is designed to be provided with a source line contact 112. The design of the source line zone 40 is basically the same as that of the word line zone 20, except that the source line zone 40 is not provided with a word line contact 114, and only has a source line contact region SL exposed from the opening 115 of the erase gate EG, on which a source line contact 112 is provided to electrically connect the source line contact region SL to the first metal layer (not shown) above.

[0067] Re-reference Figure 4 . Regarding the control gate zone 50, it is designed to set the control gate contact 120 and the source line contact 112. The control gate CG in the control gate zone 50 will have a protrusion 118 extending outward in the second direction D2, which can provide a larger landing area for the control gate contact 120. The control gate contact 120 can electrically connect the control gate CG to the first metal layer (not shown) above. The center of the control gate zone 50 will have a source line contact area SL formed in the semiconductor substrate and connected to the source line doping regions 102a on both sides, but basically will not be connected to any branch doping region. The width of the source line contact area SL in the second direction D2 will be greater than the source line doping region 102a to provide a larger landing area for the source line contact 112. The source line contact area SL will be exposed from the opening 115 of the erase gate EG, and will have a source line contact 112 thereon to electrically connect the source line contact area SL to the first metal layer (not shown) above. In this embodiment, the branch doping region 102 b located at one side of the control gate zone 50 is used as a normal memory cell, and the branch doping region 102 c located at the other side of the control gate zone 50 is a dummy pattern.

[0068] Now please refer to Figure 5 , which is a schematic diagram of the global layout of a flash memory storage block according to a preferred embodiment of the present invention. Figure 5 The layout pattern can be obtained from the above Figure 4The various zones shown are composed of a memory cell block 10, a word line zone 20, an erase gate zone 30, a control gate zone 50, etc., wherein the erase gate zone 30 is preferably located in the middle of the memory cell block 10, and the two ends of the memory cell block 10 are the word line zone 20 and the control gate zone 50 respectively. The number of branch doping regions 102b in the memory cell block 10 is not particularly limited, and depends on the capacity of the memory and the design of the invention. The bit line contact 106 on the memory cell block 10 can be shared with the branch doping regions (not shown) in other memory blocks adjacent in the second direction D2. The word line WL can be segmented by the protrusion 118 of the control gate CG, and the erase gate EG can be segmented by the openings located in the word line zone 20 and the control gate zone 50. The source line contact region SL in the word line zone 20 can be shared by the memory cell blocks 10 on both sides in the first direction D1, while the source line contact region SL in the control gate zone 50 is only used by the memory cell block 10 on one side in the first direction D1, and the other side is a dummy pattern, but not limited thereto. It should be noted that in the case where the memory structure does not have a control gate, the layout pattern of the control gate zone 50 will be changed or replaced by other zones.

[0069] Now please refer to Figure 6 , which is a schematic diagram of the layout pattern of the first metal layer M1 and the second metal layer M2 in the semiconductor back-end layer of each area of ​​a flash memory according to a preferred embodiment of the present invention, which can correspond to Figure 4 In the embodiment of the present invention, the pattern of the first metal layer M1 is changed according to the design of the misplaced branch doping region in the previous stage. Figure 6 As shown, the first metal layer M1 includes a plurality of longitudinal metal line patterns, wherein each metal line pattern has a bending portion M1a located in the source line doping region 102a ( Figure 4 ) to correspond to the misaligned branch doping region and the two straight line portions M1b ( Figure 4 ) are respectively connected to the two ends of the bending portion M1a, and the two branch doping regions 102b ( Figure 4 ) and extending in the second direction D2. Figure 4The contacts such as the bit line contact 106, the source line contact 112, the word line contact 114, the erase gate contact 116 and the control gate contact 120 described in the above can electrically connect the components related to the previous stage level to the corresponding parts of the first metal layer M1. For example, the bit line contact 106 electrically connects a branch doping region 102b to a straight line part M1b of a metal line pattern in the first metal layer M1. In the embodiment of the present invention, the pattern of the second metal layer M2 will not be affected by the design of the misaligned branch doping region, and there is no need to design a specific bending part M1a like the first metal layer M1, and all are straight and horizontal metal line patterns.

[0070] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A flash memory structure, comprising: A semiconductor substrate having an active region and a shallow trench isolation structure, wherein the active region includes a source line doping region extending in a first direction and a plurality of branch doping regions extending in a second direction and located on both sides of the source line doping region and alternately arranged along the first direction, and the branch doping regions are separated by the shallow trench isolation structures; An erase gate, located on the source line doping region and extending toward the first direction; as well as A plurality of memory cells, each of which has a floating gate located on the branch doping regions on both sides of the erase gate. 2 . The flash memory structure as claimed in claim 1 , wherein the branch doping region located on one side of the source line doping region corresponds to the shallow trench isolation structure located on the other side of the source line doping region.

3. The flash memory structure as claimed in claim 1, wherein a plurality of the branch doping regions constitute a storage block, and the center of the storage block has an erase gate zone.

4. The flash memory structure as claimed in claim 3 further comprises two control gates respectively located on the two floating gates and extending toward the first direction through a plurality of the branch doping regions, and one end of the memory block further has a control gate zone. 5 . The flash memory structure as claimed in claim 4 , wherein the control gate has a protruding portion on the control gate strip extending toward the second direction, and the control gate is connected to the first metal layer through a control gate contact on the protruding portion.

6. The flash memory structure as claimed in claim 3 further comprises two word lines respectively located outside the floating gates and extending toward the first direction through a plurality of the branch doping regions, and one end of the memory block further has a word line zone. 7 . The flash memory structure as claimed in claim 6 , wherein the source line doped region is connected to the first metal layer on the word line zone through a source line contact.

8. The flash memory structure of claim 6, wherein the word line is connected to the first metal layer through a word line contact on the word line zone.

9. The flash memory structure as claimed in claim 3, wherein the erase gate is connected to the first metal layer through an erase gate contact on the erase gate zone.

10. The flash memory structure as described in claim 1 further includes a first metal layer located on the semiconductor substrate, the first metal layer having a plurality of metal line patterns, wherein each of the metal line patterns has a bending portion located directly above the source line doping region and two straight portions located at two ends of the bending portion and directly above two branch doping regions located on both sides of the source line doping region and extending toward the second direction. 11 . The flash memory structure as claimed in claim 10 , wherein the two straight line portions of each of the metal line patterns are connected to the two branch doping regions through bit line contacts, respectively.

12. A flash memory structure comprising: A semiconductor substrate having an active region and a shallow trench isolation structure, wherein the active region includes a source line doping region extending in a first direction and a plurality of branch doping regions extending in a second direction and located on both sides of the source line doping region, and the branch doping regions are separated by the shallow trench isolation structures; An erase gate, located on the source line doping region and extending toward the first direction; A plurality of memory cells, each of the memory cells having a floating gate located on the branch doping regions on both sides of the erase gate; and The first metal layer is located on the semiconductor substrate, and the first metal layer has a plurality of metal line patterns, wherein each of the metal line patterns has a bending portion located directly above the source line doping region and two straight portions respectively connected to two ends of the bending portion and directly above two branch doping regions located on both sides of the source line doping region and extending toward the second direction.

13. The flash memory structure as claimed in claim 12, wherein the branch doping regions located on both sides of the source line doping region are alternately arranged along the second direction, and the source line doping region located on one side of the source line doping region corresponds to the shallow trench isolation structure located on the other side of the source line doping region.

14. The flash memory structure as claimed in claim 12, wherein a plurality of the branch doped regions form a memory block, and the center of the memory block has an erase gate zone.

15. The flash memory structure as claimed in claim 14, further comprising two control gates respectively located on the two floating gates and extending toward the first direction through a plurality of the branch doping regions, and one end of the memory block further has a control gate zone. 16 . The flash memory structure as claimed in claim 15 , wherein the control gate has a protruding portion extending toward the second direction on the control gate zone, and the control gate is connected to the first metal layer through a control gate contact on the protruding portion.

17. The flash memory structure as claimed in claim 14, further comprising two word lines respectively located outside the floating gates and extending toward the first direction through a plurality of the branch doping regions, and one end of the memory block further has a word line zone.

18. The flash memory structure of claim 17, wherein the source line doped region is connected to the first metal layer through a source line contact on the word line zone.

19. The flash memory structure of claim 14, wherein the erase gate is connected to the first metal layer through an erase gate contact on the erase gate zone.

20. The flash memory structure of claim 14, wherein the word line is connected to the first metal layer through a word line contact on the word line zone.

21. The flash memory structure of claim 11, wherein the two straight line portions of each of the metal line patterns are respectively connected to the two branch doping regions through a bit line contact.

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