High electron mobility transistor chip and preparation method thereof
By introducing a P-type GaN cap layer into the epitaxial layer of the GaN-based HEMT chip, the problem of chip depletion-type working mode is solved, and the normal-off characteristics without negative bias voltage are achieved, which improves the chip's safety and gate control capabilities.
Patent Information
- Application Number
- CN202411887394.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-20
- Publication Date
- 2025-04-29
AI Technical Summary
Due to the strong spontaneous polarization and piezoelectric polarization effects, GaN-based HEMT chips often show a depletion operating mode, and additional negative bias voltage is required to shut down the chip, which is not conducive to the safe operation of the chip and circuit design.
By introducing a P-type GaN cap layer into the epitaxial layer of a high electron mobility transistor chip and setting it between the gate and barrier layer, the growth rate of the cap layer is controlled so that it grows only in the area below the gate, thereby improving the energy band at the heterojunction interface of the channel layer and the barrier layer, and achieving normal-off characteristics.
No additional design of negative bias voltage is required, which improves the chip's operational safety, reduces circuit design difficulty, and improves the gate control capability of high-electron mobility transistor chips.
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Figure CN119907261A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a high electron mobility transistor chip and a method for preparing the same. Background Art
[0002] HEMT (High Electron Mobility Transistor) is a heterojunction field effect transistor, which is widely used in aerospace, communication technology, automotive electronics and switching power supply, especially in high power and high frequency application fields. HEMT chip is the basis for the preparation of electronic power devices.
[0003] In the related art, a HEMT chip mainly includes a gate, a source, a drain and an epitaxial layer.
[0004] In the GaN-based HEMT chips of the related technology, since the GaN material has strong spontaneous polarization and piezoelectric polarization effects, it often exhibits a depletion mode of operation, that is, the threshold voltage is negative, and an additional negative bias voltage needs to be designed to shut down the HEMT chip, which is very unfavorable to the safe operation and circuit design of the HEMT chip. Summary of the invention
[0005] The embodiments of the present disclosure provide a high electron mobility transistor chip and a method for manufacturing the same, which can improve the gate control capability of the high electron mobility transistor chip. The technical solution is as follows:
[0006] On the one hand, an embodiment of the present disclosure provides a high electron mobility transistor chip, including a source, a drain, a gate and an epitaxial layer;
[0007] The epitaxial layer includes a channel layer, a barrier layer and a cap layer stacked in sequence, and the cap layer is a P-type GaN layer;
[0008] The source, the drain and the gate are located on the same side of the epitaxial layer, the source and the drain are located on opposite sides of the gate, respectively, the gate is connected to a side of the cap layer facing away from the barrier layer, and the orthographic projection of the cap layer on the plane where the barrier layer is located is located within the orthographic projection of the gate on the plane where the barrier layer is located.
[0009] In an implementation of the present disclosure, an orthographic projection of the cap layer on the plane where the barrier layer is located coincides with an orthographic projection of the gate on the plane where the barrier layer is located.
[0010] In an implementation of the present disclosure, the thickness of the cap layer in the epitaxial growth direction is 70-160 nm.
[0011] In one implementation of the present disclosure, the high electron mobility transistor chip further includes a dielectric layer;
[0012] The dielectric layer is located on a side of the barrier layer facing away from the channel layer. The dielectric layer has a gate contact hole. The cap layer is at least partially located in the gate contact hole.
[0013] In one implementation of the present disclosure, the dielectric layer is a SiN layer.
[0014] In an implementation of the present disclosure, the thickness of the dielectric layer in the epitaxial growth direction is 40-60 nm.
[0015] In an implementation of the present disclosure, the high electron mobility transistor chip further includes a buffer layer and a stress release layer stacked in sequence, wherein the buffer layer and the stress release layer are both located on a side of the channel layer facing away from the barrier layer;
[0016] The buffer layer is a GaN layer, and the stress release layer is a periodically stacked AlN / AlGaN superlattice structure.
[0017] On the other hand, an embodiment of the present disclosure provides a method for preparing a high electron mobility transistor chip, the method for preparing the high electron mobility transistor chip as described in the above aspect, the method comprising:
[0018] Prepare an epitaxial layer, wherein the epitaxial layer comprises a channel layer, a barrier layer and a cap layer stacked in sequence, wherein the cap layer is a P-type GaN layer;
[0019] A source electrode, a drain electrode and a gate electrode are prepared, and the orthographic projection of the cap layer on the plane where the barrier layer is located is located within the orthographic projection of the gate electrode on the plane where the barrier layer is located.
[0020] In one implementation of the present disclosure, preparing an epitaxial layer includes:
[0021] Preparing a dielectric layer on a side of the barrier layer facing away from the channel layer;
[0022] Etching a gate contact hole on the dielectric layer;
[0023] The cap layer is obtained by epitaxial growth inside the gate contact hole.
[0024] In one implementation of the present disclosure, the cap layer is obtained by epitaxially growing the inner side of the gate contact hole, including:
[0025] The growth rate of the capping layer is controlled so that the lateral growth rate of the capping layer is greater than the longitudinal growth rate of the capping layer.
[0026] The beneficial effects brought by the technical solution provided by the embodiments of the present disclosure include at least:
[0027] The epitaxial layer includes a cap layer, which is a P-type GaN layer. The cap layer is arranged between the gate and the barrier layer, and the cap layer can improve the energy band at the heterojunction interface of the channel layer and the barrier layer, and make it higher than the Fermi level when the gate bias is 0V, thereby depleting the two-dimensional electron gas in the area below the gate, thereby realizing the normally-off characteristic. In addition, since the orthographic projection of the cap layer on the plane where the barrier layer is located is located within the orthographic projection of the gate on the plane where the barrier layer is located, the cap layer is only located in the area below the gate, ensuring the two-dimensional electron gas in the channel, thereby improving the gate control capability of the high electron mobility transistor chip.
[0028] That is to say, the high electron mobility transistor chip provided by the embodiment of the present disclosure does not need to design an additional negative bias voltage, which effectively improves the operation safety and reduces the difficulty of circuit design. In addition, the cap layer is only located in the area below the gate, which ensures the two-dimensional electron gas in the channel, thereby improving the gate control ability of the high electron mobility transistor chip. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0030] Figure 1 is a schematic structural diagram of a high electron mobility transistor provided by an embodiment of the present disclosure;
[0031] Figure 2 is a flow chart of a method for preparing a high electron mobility transistor provided by an embodiment of the present disclosure;
[0032] Figure 3 is a flow chart of another method for preparing a high electron mobility transistor provided by an embodiment of the present disclosure;
[0033] Figure 4 is a schematic diagram of a preparation process of a high electron mobility transistor provided by an embodiment of the present disclosure;
[0034] Figure 5 is a schematic diagram of a preparation process of a high electron mobility transistor provided by an embodiment of the present disclosure;
[0035] Figure 6 is a schematic diagram of a preparation process of a high electron mobility transistor provided by an embodiment of the present disclosure;
[0036] Figure 7It is a schematic diagram of the preparation process of the high electron mobility transistor provided in the embodiment of the present disclosure.
[0037] Figure Number:
[0038] 10. Source;
[0039] 20. Drain;
[0040] 30. Gate;
[0041] 40. Epitaxial layer;
[0042] 410, channel layer; 420, barrier layer; 430, cap layer;
[0043] 50. Dielectric layer;
[0044] 510, hard mask layer;
[0045] 60. Gate contact hole;
[0046] 70. Buffer layer;
[0047] 80. Stress release layer;
[0048] 90. Substrate. DETAILED DESCRIPTION
[0049] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.
[0050] As a representative of the third generation of semiconductor materials, GaN is an important semiconductor material that appeared after Si and GaAs materials. It has attracted widespread attention due to its excellent properties such as large bandgap, high critical field strength, high carrier saturation velocity, and resistance to high temperature and radiation.
[0051] GaN-based high electron mobility transistors generate a conductive channel by forming a high-concentration, high-mobility two-dimensional electron gas (2DEG) at the heterojunction, thereby achieving device conduction. Due to its excellent characteristics such as high thermal conductivity, low on-resistance, and tolerance to high-frequency and high-voltage conditions, GaN-based high electron mobility transistors have become a research hotspot in the field of high-frequency and high-power devices and switching devices in recent years.
[0052] In related technologies, since GaN materials have strong spontaneous polarization and piezoelectric polarization effects, they often exhibit a depletion mode of operation, that is, the threshold voltage is negative, and an additional negative bias voltage needs to be designed to shut down the HEMT chip, which is very unfavorable to the safe operation and circuit design of the HEMT chip.
[0053] In order to solve the above technical problems, the present disclosure provides a high electron mobility transistor. Figure 1 is a schematic diagram of the structure of the high electron mobility transistor, combined with Figure 1 In this embodiment, the high electron mobility transistor includes a source 10, a drain 20, a gate 30 and an epitaxial layer 40. The epitaxial layer 40 includes a channel layer 410, a barrier layer 420 and a cap layer 430 stacked in sequence, and the cap layer 430 is a P-type GaN layer. The source 10, the drain 20 and the gate 30 are located on the same side of the epitaxial layer 40, the source 10 and the drain 20 are respectively located on opposite sides of the gate 30, the gate 30 is connected to the side of the cap layer 430 facing away from the barrier layer 420, and the orthographic projection of the cap layer 430 on the plane where the barrier layer 420 is located is located within the orthographic projection of the gate 30 on the plane where the barrier layer 420 is located.
[0054] The epitaxial layer 40 includes a cap layer 430, which is a P-type GaN layer. The cap layer 430 is arranged between the gate 30 and the barrier layer 420. The cap layer 430 can improve the energy band at the heterojunction interface of the channel layer 410 and the barrier layer 420, and make it higher than the Fermi level when the gate bias is 0V, thereby depleting the two-dimensional electron gas in the area below the gate 30, thereby realizing the normally-off characteristic. In addition, since the orthographic projection of the cap layer 430 on the plane where the barrier layer 420 is located is located within the orthographic projection of the gate 30 on the plane where the barrier layer 420 is located, the cap layer 430 is only located in the area below the gate 30, ensuring the two-dimensional electron gas in the channel, thereby improving the gate control capability of the high electron mobility transistor chip.
[0055] That is to say, the high electron mobility transistor chip provided by the embodiment of the present disclosure does not need to design an additional negative bias voltage, which effectively improves the operation safety and reduces the difficulty of circuit design. In addition, the cap layer 430 is only located in the area below the gate 30, which ensures the two-dimensional electron gas in the channel, thereby improving the gate control ability of the high electron mobility transistor chip.
[0056] Continue to see Figure 1 In this embodiment, the orthographic projection of the cap layer 430 on the plane where the barrier layer 420 is located coincides with the orthographic projection of the gate 30 on the plane where the barrier layer 420 is located.
[0057] In the above implementation, the cap layer 430 is completely disposed in the area below the gate 30, that is, sandwiched between the gate 30 and the barrier layer 420. In this way, the problem of damage to the sidewall of the cap layer 430 is effectively avoided, which is conducive to enhancing the gate control capability of the high electron mobility transistor chip.
[0058] Exemplarily, the thickness of the cap layer 430 in the epitaxial growth direction is 70-160 nm.
[0059] In the above implementation, the thickness of the cap layer 430 is designed to be the above value, which can ensure that its functionality is not affected by too small a thickness, and can also ensure that its preparation efficiency is not affected by too large a thickness.
[0060] In this embodiment, the channel layer 410 is a GaN layer, and the thickness of the channel layer 410 is 150-350 nm. The barrier layer 420 is an AlGaN layer, and the thickness of the barrier layer 420 is 15-35 nm.
[0061] In the above implementation, an AlGaN / GaN heterojunction is formed between the channel layer 410 and the barrier layer 420. Due to the influence of surface traps, if the barrier layer 420 is thinner, the electric field strength of the barrier layer 420 is greater, the current collapse will be more serious, and the saturated output power will be lower. If the barrier layer 420 is thicker, the barrier layer 420 will increase the parasitic effect and reduce the small signal gain characteristics. Therefore, designing the barrier layer 420 to the above thickness can ensure better reliability.
[0062] Continue to see Figure 1 In this embodiment, the high electron mobility transistor chip further includes a dielectric layer 50 . The dielectric layer 50 is located on the side of the barrier layer 420 facing away from the channel layer 410 . The dielectric layer 50 has a gate contact hole 60 . The cap layer 430 is at least partially located in the gate contact hole 60 .
[0063] In the above implementation, the dielectric layer 50 has a gate contact hole 60 , and the gate contact hole 60 provides an accommodation space for the cap layer 430 , which is beneficial for controlling the growth morphology of the cap layer 430 .
[0064] In this embodiment, the dielectric layer 50 is a SIN layer.
[0065] In the above implementation, the dielectric layer 50 is designed as a SIN layer, which can be used as a basis for the gate contact hole 60 .
[0066] Exemplarily, the thickness of the dielectric layer 50 in the epitaxial growth direction is 40-60 nm.
[0067] In the above implementation, the thickness of the dielectric layer 50 is designed to be the above value, which can ensure that the functionality is not affected by too small a thickness, and can also ensure that the manufacturing efficiency is not affected by too large a thickness.
[0068] Continue to see Figure 1 In this embodiment, the high electron mobility transistor chip further includes a substrate 90 , and the substrate 90 is located on a side of the channel layer 410 facing away from the barrier layer 420 .
[0069] In the above implementation, the substrate 90 provides a basis for the growth of the epitaxial layer 40 to ensure the reliability of the growth of the epitaxial layer 40 .
[0070] Exemplarily, the material of substrate 90 is any one of sapphire, Si, SiC, and GaN, which are easy to prepare and obtain.
[0071] Continue to see Figure 1 In this embodiment, the high electron mobility transistor chip further includes a buffer layer 70 and a stress release layer 80 stacked in sequence, and the buffer layer 70 and the stress release layer 80 are both located on the side of the channel layer 410 facing away from the barrier layer 420. The buffer layer 70 is a GaN layer, and the stress release layer 80 is a periodically stacked AlN / AlGaN superlattice structure.
[0072] In the above implementation, the buffer layer 70 and the stress release layer 80 are sequentially stacked between the substrate 90 and the epitaxial layer 40. The buffer layer 70 has high resistivity, reduces the background carrier concentration to reduce the current collapse of the drain 20 caused by the trap effect of the buffer layer 70. The stress release layer 80 can release a certain amount of stress to improve the quality of the epitaxial layer 40 of the electron mobility transistor finally obtained.
[0073] Exemplarily, the thickness of the buffer layer 70 in the epitaxial growth direction is 3-6 μm.
[0074] Exemplarily, the stress release layer 80 has 20 stacked layers, and the thickness of each layer is 10 nm.
[0075] Figure 2 A method for preparing a high electron mobility transistor chip provided in an embodiment of the present disclosure is provided. Figure 2 , the preparation method comprises:
[0076] Step 201 : preparing an epitaxial layer 40 .
[0077] In step 201 , the prepared epitaxial layer 40 includes a channel layer 410 , a barrier layer 420 , and a cap layer 430 stacked in sequence, and the cap layer 430 is a P-type GaN layer.
[0078] Step 202 : preparing the source electrode 10 , the drain electrode 20 and the gate electrode 30 .
[0079] In step 202 , the orthographic projection of the cap layer 430 on the plane where the barrier layer 420 is located is made to be within the orthographic projection of the gate 30 on the plane where the barrier layer 420 is located.
[0080] The high electron mobility transistor chip prepared by the preparation method provided by the embodiment of the present disclosure includes an epitaxial layer 40, and the epitaxial layer 40 includes a cap layer 430, and the cap layer 430 is a P-type GaN layer. The cap layer 430 is arranged between the gate 30 and the barrier layer 420, and the cap layer 430 can improve the energy band at the heterojunction interface of the channel layer 410 and the barrier layer 420, and make it higher than the Fermi level when the gate bias is 0V, thereby depleting the two-dimensional electron gas in the area below the gate 30, thereby realizing the normally-off characteristic. In addition, since the orthographic projection of the cap layer 430 on the plane where the barrier layer 420 is located is located within the orthographic projection of the gate 30 on the plane where the barrier layer 420 is located, the cap layer 430 is only located in the area below the gate 30, ensuring the two-dimensional electron gas in the channel, thereby improving the gate control capability of the high electron mobility transistor chip.
[0081] That is to say, the high electron mobility transistor chip prepared by the preparation method provided by the embodiment of the present disclosure does not need to design an additional negative bias voltage, which effectively improves the operation safety and reduces the difficulty of circuit design. In addition, the cap layer 430 is only located in the area below the gate 30, which ensures the two-dimensional electron gas in the channel, thereby improving the gate control ability of the high electron mobility transistor chip.
[0082] Figure 3 Another method for preparing a high electron mobility transistor chip provided in the embodiment of the present disclosure is as follows: Figure 3 , the preparation method comprises:
[0083] Step 301: Provide a substrate 90.
[0084] Optionally, the material of the substrate 90 is sapphire, SiC, Si, GaN, etc. In this embodiment, the material of the substrate 90 is sapphire.
[0085] Step 302 : preparing a buffer layer 70 on one side of the substrate 90 .
[0086] Exemplarily, the buffer layer 70 is grown by a MOCVD (Metal Organic Chemical Vapor Deposition) device, the buffer layer 70 is a GaN layer, and the thickness of the buffer layer 70 is 3-6 μm.
[0087] Step 303 : preparing a stress release layer 80 on one side of the buffer layer 70 .
[0088] Exemplarily, the stress release layer 80 is a periodically stacked AlN / AlGaN superlattice structure, the number of stacked layers is 18 to 22, and the thickness of each layer of the AlN / AlGaN superlattice structure is 8 to 12 nm.
[0089] In this embodiment, the number of stacked stress release layers 80 is 20, and the thickness of each stress release layer 80 is 10 nm.
[0090] Step 304 : sequentially preparing a channel layer 410 and a barrier layer 420 on one side of the buffer layer 70 .
[0091] Exemplarily, the channel layer 410 and the barrier layer 420 are both grown by MOCVD equipment, the channel layer 410 is a GaN layer with a thickness of 150-350 nm, and the barrier layer 420 is an AlGaN layer with a thickness of 15-35 nm.
[0092] Step 305 : preparing a dielectric layer 50 on a side of the barrier layer 420 facing away from the channel layer 410 .
[0093] Exemplarily, the dielectric layer 50 is a SiN layer, and the thickness of the dielectric layer 50 in the epitaxial growth direction is 40-60 nm.
[0094] The dielectric layer 50 is prepared by LPCVD (Low Pressure Chemical Vapor Deposition) equipment.
[0095] After step 305, a hard mask layer 510 may be formed on the side of the dielectric layer 50 facing away from the barrier layer 420 (see Figure 4 ).
[0096] Exemplarily, the hard mask layer 510 is a SiO 2 layer, and the thickness of the hard mask layer 510 in the epitaxial growth direction is 60-100 nm.
[0097] The hard mask layer 510 is prepared by PECVD (plasma enhanced chemical vapor deposition) equipment. In other embodiments, the hard mask layer 510 can also be prepared by ALD equipment or MOCVD equipment.
[0098] In the above implementation, the hard mask layer 510 covers the side of the dielectric layer 50 facing away from the barrier layer 420 to protect the dielectric layer 50 and prevent the dielectric layer 50 from being damaged when etching the gate contact hole 60 in the subsequent step 306 .
[0099] It is worth noting that in the subsequent steps, the hard mask layer 510 is removed again using a buffered oxide etch (BOE).
[0100] Step 306 : etching the dielectric layer 50 to obtain a gate contact hole 60 .
[0101] Exemplarily, step 306 is implemented by the following steps:
[0102] First, the gate contact hole 60 is positioned by photolithography, and the hard mask layer 510 is etched by dry etching technology (see Figure 5 ).
[0103] In this embodiment, the etching angle is 60° to 80°.
[0104] Of course, in other embodiments, the hard mask layer 510 can also be etched by wet etching. In this case, the hard mask layer 510 is first deposited, and then the gate contact hole 60 is grooved by photolithography. After stripping, the hard mask layer 510 is used as a mask to wet etch the dielectric layer 50, thereby obtaining the gate contact hole 60.
[0105] Then, the dielectric layer 50 is etched using an alkaline solution (see Figure 6 ).
[0106] In this embodiment, the alkaline solution is a developer, TMAH, SPM (a mixture of sulfuric acid and hydrogen peroxide), or the like.
[0107] Step 307: epitaxially grow a cap layer 430 inside the gate contact hole 60 (see Figure 7 ).
[0108] Exemplarily, in step 307 , the growth rate of the capping layer 430 is controlled such that the lateral growth rate of the capping layer 430 is greater than the longitudinal growth rate of the capping layer 430 .
[0109] The cap layer 430 is prepared by MOCVD equipment, MBE equipment, ALD equipment, etc.
[0110] Exemplarily, the P-type doping concentration of the cap layer 430 needs to be greater than 1E19, and the thickness of the cap layer 430 in the epitaxial growth direction is 40-160 nm.
[0111] The epitaxial layer 40 is prepared through steps 304 to 307 .
[0112] Step 308: Prepare the source electrode 10, the drain electrode 20 and the gate electrode 30 (see Figure 1 ).
[0113] In step 308, the source 10 and the drain 20 are respectively located on opposite sides of the gate 30, and the source 10 and the drain 20 are respectively separated from the capping layer 430, the gate 30 is connected to the side of the capping layer 430 facing away from the barrier layer 420, and the orthographic projection of the capping layer 430 on the plane where the barrier layer 420 is located is located within the orthographic projection of the gate 30 on the plane where the barrier layer 420 is located.
[0114] Exemplarily, the source electrode 10 , the drain electrode 20 and the gate electrode 30 are prepared by photolithography, etching and metal evaporation processes.
[0115] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons with ordinary skills in the field to which the present disclosure belongs. The words "first", "second", "third" and similar words used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limitation, but indicate the existence of at least one. Words such as "include" or "comprise" and similar words mean that the elements or objects appearing before "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", "top", "bottom" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.
[0116] The above does not limit the present disclosure in any form. Although the present disclosure has been disclosed as above through the embodiments, it is not used to limit the present disclosure. Any technician familiar with the profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present disclosure. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present disclosure without departing from the content of the technical solution of the present disclosure still falls within the scope of the technical solution of the present disclosure.
Claims
1. A high electron mobility transistor chip, characterized in that: It comprises a source electrode (10), a drain electrode (20), a gate electrode (30) and an epitaxial layer (40); The epitaxial layer (40) comprises a channel layer (410), a barrier layer (420) and a cap layer (430) which are stacked in sequence, and the cap layer (430) is a P-type GaN layer; The source electrode (10), the drain electrode (20) and the gate electrode (30) are located on the same side of the epitaxial layer (40); the source electrode (10) and the drain electrode (20) are respectively located on opposite sides of the gate electrode (30) (on both sides of the gate); the gate electrode (30) is connected to a side of the cap layer (430) facing away from the barrier layer (420); and the orthographic projection of the cap layer (430) on the plane where the barrier layer (420) is located is located within the orthographic projection of the gate electrode (30) on the plane where the barrier layer (420) is located.
2. The high electron mobility transistor chip according to claim 1, characterized in that: The orthographic projection of the cap layer (430) on the plane where the barrier layer (420) is located coincides with the orthographic projection of the gate (30) on the plane where the barrier layer (420) is located.
3. The high electron mobility transistor chip according to claim 1, characterized in that: The cap layer (430) has a thickness of 70 to 160 nm in the epitaxial growth direction.
4. The high electron mobility transistor chip according to claim 1, characterized in that: The high electron mobility transistor chip further comprises a dielectric layer (50); The dielectric layer (50) is located on a side of the barrier layer (420) facing away from the channel layer (410), the dielectric layer (50) has a gate contact hole (60), and the cap layer (430) is at least partially located in the gate contact hole (60).
5. The high electron mobility transistor chip according to claim 4, characterized in that: The dielectric layer (50) is a SiN layer.
6. The high electron mobility transistor chip according to claim 5, characterized in that: The thickness of the dielectric layer (50) in the epitaxial growth direction is 40-60 nm.
7. The high electron mobility transistor chip according to claim 5, characterized in that: The high electron mobility transistor chip further comprises a buffer layer (70) and a stress release layer (80) stacked in sequence, wherein the buffer layer (70) and the stress release layer (80) are both located on a side of the channel layer (410) facing away from the barrier layer (420); The buffer layer (70) is a GaN layer, and the stress release layer (80) is a periodically stacked AlN / AlGaN superlattice structure.
8. A method for preparing a high electron mobility transistor chip, characterized in that: The preparation method is used to prepare the high electron mobility transistor chip according to claim 1, and the preparation method comprises: preparing an epitaxial layer (40), wherein the epitaxial layer (40) comprises a channel layer (410), a barrier layer (420) and a cap layer (430) stacked in sequence, and the cap layer (430) is a P-type GaN layer; A source electrode (10), a drain electrode (20) and a gate electrode (30) are prepared, wherein the orthographic projection of the cap layer (430) on the plane where the barrier layer (420) is located is located within the orthographic projection of the gate electrode (30) on the plane where the barrier layer (420) is located.
9. The preparation method according to claim 8, characterized in that: Preparing an epitaxial layer (40), comprising: Preparing a dielectric layer (50) on a side of the barrier layer (420) facing away from the channel layer (410); Etching a gate contact hole (60) on the dielectric layer (50); The cap layer (430) is obtained by epitaxially growing inside the gate contact hole (60).
10. The preparation method according to claim 9, characterized in that: The cap layer (430) is obtained by epitaxially growing the inner side of the gate contact hole (60), comprising: The growth rate of the cap layer (430) is controlled so that the lateral growth rate of the cap layer (430) is greater than the longitudinal growth rate of the cap layer (430).