SOI wafer-based PMUT optimization production method

Abstract

The invention relates to a PMUT optimized production method based on an SOI wafer, and the method comprises the following steps: improving the thickness uniformity of a structural layer according to the thickness distribution of the structural layer of the SOI wafer; under the atmosphere of nitrogen and argon, a seed layer is sputtered on a structural layer, a bottom electrode layer is sputtered on the seed layer, a piezoelectric layer is deposited on the bottom electrode layer, a top electrode layer is sputtered on the piezoelectric layer, and the stress of the piezoelectric layer is adjusted by changing the argon flow velocity in the process of sputtering the bottom electrode layer and the radio frequency bias voltage in the process of depositing the piezoelectric layer. Further, the substrate curvature radius of the SOI wafer is adjusted, and the warping of the SOI wafer is reduced; a DRIE etching mode is adopted to carry out back cavity etching on an SOI wafer, the flow of passivation gas and the specific time example of the passivation gas in an etching period are increased, and a carbon fluoride polymer formed by reaction is fully deposited on the surface of the side wall of the back cavity. Compared with the prior art, the wafer level frequency consistency of the PMUT device is improved, and the large-scale production and industrialization process of the PMUT on the SOI wafer is accelerated.

Description

Technical Field

[0001] The invention relates to the technical field of PMUT production, and in particular to an optimized production method of PMUT based on SOI wafer. Background Art

[0002] The large-scale production of piezoelectric micromachined ultrasonic transducers (PMUTs) has been limited by the wafer-level inconsistency of the device's operating frequency, which results in a low industrial mass production yield of PMUTs.

[0003] PMUTs are manufactured using a silicon-on-insulator (SOI) process platform. Generally speaking, frequency consistency of PMUT devices on the wafer is critical to matching the specifications of drive electronics and improving operating efficiency.

[0004] However, the ratio of the thickness to the lateral size of the low-frequency PMUT film is usually small. Therefore, the frequency of the device is highly sensitive to the uniformity of the residual stress and the film size, which reduces the wafer-level frequency consistency of the air-coupled PMUT. With the expansion of the commercial application scope of PMUT, it is increasingly urgent to improve the wafer-level frequency consistency of the device in large-scale production. CSOI (cavity SOI) is achieved by setting a pre-processed cavity between the insulating layer and the silicon layer, and then bonding a film to the cavity, so that precise size control and improved frequency consistency can be achieved. However, the cavity process of PMUT prepared by deep reactive ion etching (DRIE) on SOI wafers is relatively complicated. Therefore, it is difficult to achieve improved wafer-level frequency consistency of PMUT devices on SOI wafers. Summary of the invention

[0005] The purpose of the present invention is to provide a PMUT optimization production method based on SOI wafer in order to overcome the defects of the above-mentioned prior art, improve the wafer-level frequency consistency of PMUT devices, and accelerate the large-scale production and industrialization process of PMUT on SOI wafer.

[0006] The purpose of the present invention can be achieved by the following technical solutions:

[0007] A PMUT optimization production method based on SOI wafer includes the following steps:

[0008] Measuring the thickness of the structural layer of the SOI wafer to obtain the thickness distribution of the structural layer of the SOI wafer, and adjusting the thickness of different areas on the top of the structural layer of the SOI wafer according to the thickness distribution of the structural layer of the SOI wafer to improve the uniformity of the thickness of the structural layer;

[0009] In a nitrogen and argon atmosphere, a seed layer is sputtered on the structural layer, a bottom electrode layer is sputtered on the seed layer, a piezoelectric layer is deposited on the bottom electrode layer, and a top electrode layer is sputtered on the piezoelectric layer, and the stress of the piezoelectric layer is adjusted by changing the argon gas flow rate during the sputtering of the bottom electrode layer and the radio frequency bias voltage during the deposition of the piezoelectric layer, thereby adjusting the substrate curvature radius of the SOI wafer and reducing the warpage of the SOI wafer;

[0010] After the sputtering and deposition are completed, the SOI wafer is back-etched by DRIE etching, and the flow rate of the passivation gas and the time ratio of the passivation gas in the etching cycle are increased, so that the fluorinated carbon polymer formed by the reaction is fully deposited on the side wall surface of the back cavity;

[0011] The etched SOI wafer is sliced ​​to obtain a PMUT.

[0012] Furthermore, the SOI wafer includes a substrate and a structural layer, wherein the substrate and the structural layer include a SiO2 insulating layer.

[0013] Furthermore, the relationship between the stress of the piezoelectric layer and the substrate curvature radius of the SOI wafer is:

[0014]

[0015] Where σ is stress, h is substrate thickness, t is piezoelectric layer thickness, R is the substrate curvature radius of the SOI wafer, E is the Young's modulus of the substrate, and v is the Poisson's ratio of the substrate. is the biaxial elastic modulus of the substrate.

[0016] Furthermore, the material of the seed layer is AlN.

[0017] Furthermore, the material of the piezoelectric layer is Al 0.8 Sc 0.2 N.

[0018] Furthermore, the material of the bottom electrode layer and the top electrode layer is Mo.

[0019] Furthermore, the method also includes back cavity diameter stability verification, and the back cavity diameter stability verification specifically includes:

[0020] A bare silicon wafer of the same size as the SOI wafer is used, and the bare silicon wafer is thinned to the same thickness as the substrate of the SOI wafer, and a SiO2 layer is deposited on the bare silicon wafer as an etch stop layer for back cavity etching, and the bare silicon wafer is back cavity etched using the same etching method as that used for back cavity etching of the SOI wafer, and the diameter of the back cavity of the bare silicon wafer is measured from the front side using an optical microscope, thereby obtaining the back cavity diameter of the SOI wafer.

[0021] Furthermore, the method also includes wafer-level frequency consistency verification of the PMUT, and the wafer-level frequency consistency verification of the PMUT specifically includes: obtaining the wafer-level frequency consistency of the PMUT by comparing the resonant frequency distribution of the PMUT and the standard deviation of the resonant frequency of the PMUT.

[0022] Furthermore, the calculation formula of the resonant frequency of the PMUT is:

[0023]

[0024] Where r is the radius of the PMUT, D is the stiffness of the thin film stack consisting of the structural layer, electrode layer and piezoelectric layer, and ρ i and t i are the density and thickness of the structural layer, electrode layer and piezoelectric layer, respectively.

[0025] Furthermore, the calculation formula of the stiffness is:

[0026]

[0027] In the formula, E i is Young's modulus, v i is the Poisson’s ratio of each film layer material in the film stack, Z i is the distance from the top surface of the i-th film layer to the neutral axis.

[0028] Compared with the prior art, the present invention has the following beneficial effects:

[0029] 1. The present invention optimizes the PMUT manufacturing process on the SOI wafer, adjusts the stress of the piezoelectric layer by changing the argon gas flow rate during the sputtering of the bottom electrode layer and the radio frequency bias voltage during the deposition of the piezoelectric layer, and reduces the warpage of the SOI wafer.

[0030] 2. The present invention measures the thickness of the structural layer of the SOI wafer to obtain the thickness distribution of the structural layer of the SOI wafer. According to the thickness distribution of the structural layer of the SOI wafer, different areas on the top of the structural layer of the SOI wafer are subjected to micro-thinning treatment, thereby improving the uniformity of the thickness of the structural layer.

[0031] 3. The present invention adopts DRIE etching method to perform back cavity etching on SOI wafer, increases the flow rate of passivation gas and the proportion of passivation gas in the etching cycle, so that the fluorinated carbon polymer formed by the reaction is fully deposited on the surface of the back cavity side wall, blocks the reaction of fluoride ions with the side wall silicon, prevents the reaction of fluoride ions with silicon, and improves the uniformity of the back cavity etching size.

[0032] 4. The present invention calculates the resonant frequency of the PMUT to obtain the resonant frequency distribution of the PMUT, and obtains the wafer-level frequency consistency of the PMUT by comparing the resonant frequency distribution of the PMUT and the standard deviation of the resonant frequency of the PMUT, thereby verifying that the optimized production method of the present invention improves the wafer-level frequency consistency of the PMUT. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A schematic diagram of a process flow of a PMUT production process optimization method for SOI wafers proposed by the present invention;

[0034] Figure 2 Thickness distribution map of silicon structure layer of SOI wafer before optimization for micro-thinning process;

[0035] Figure 3 This is the thickness distribution diagram of the silicon structure layer of the SOI wafer after micro-thinning process optimization;

[0036] Figure 4 Comparison chart before and after SOI wafer warpage optimization;

[0037] Figure 5 Schematic diagram of back cavity etching dimensions before back cavity etching optimization;

[0038] Figure 6 Schematic diagram of back cavity etching dimensions after back cavity etching optimization;

[0039] Figure 7 This is the wafer-level frequency distribution diagram of the PMUT device without any process optimization;

[0040] Figure 8 This is the wafer-level frequency distribution diagram of the PMUT device after micro-thinning, warpage optimization and back cavity etching optimization. DETAILED DESCRIPTION

[0041] The present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments. This embodiment is implemented based on the technical solution of the present invention, and provides a detailed implementation method and specific operation process, but the protection scope of the present invention is not limited to the following embodiments.

[0042] Abbreviations involved:

[0043] Silicon-On-Insulator, SOI

[0044] Piezoelectric Micromachined Ultrasonic Transducer: Piezoelectric Micromachined Ultrasonic Transducer, PMUT

[0045] Deep Reactive Ion Etching: DRIE

[0046] Example 1

[0047] This embodiment provides an optimized production method based on PMUT on SOI wafer, such as Figure 1 As shown, this embodiment specifically optimizes the production method of PMUT on an 8-inch SOI wafer, including the following steps:

[0048] S1. Measure the thickness of the structural layer of the SOI wafer to obtain the thickness distribution of the structural layer of the SOI wafer, and adjust the thickness of different areas on the top of the structural layer of the SOI wafer according to the thickness distribution of the structural layer of the SOI wafer to improve the uniformity of the thickness of the structural layer.

[0049] The silicon structure layer of the SOI wafer is measured using a Si film thickness measurement system (FILMETRICS F50). The thickness distribution of the silicon structure layer is shown in the figure below. Figure 2 The average value of the Si structure layer is 4.453 μm, the maximum thickness difference is 0.998 μm, and the standard deviation is 0.262 μm.

[0050] A high-precision surface ion milling machine (scia Trim 200) was used to perform micro-thinning on different areas of the top silicon structure layer. The thickness distribution of the Si structure layer on the optimized SOI wafer is shown in the figure below: Figure 3 As shown. The thickness of the silicon layer was adjusted by the thin film thickness fine-tuning machine. The average thickness of the silicon structure layer was 4.185μm, the standard deviation of the silicon layer thickness was reduced from the original 0.998μm to 0.542μm, and the standard deviation was reduced from 0.342μm to 0.096μm. These results show that the uniformity of the thickness of the silicon structure layer has been significantly improved.

[0051] S2. In a nitrogen and argon atmosphere, a seed layer is sputtered on the structural layer, a bottom electrode layer is sputtered on the seed layer, a piezoelectric layer is deposited on the bottom electrode layer, and a top electrode layer is sputtered on the piezoelectric layer. The stress of the piezoelectric layer is adjusted by changing the argon gas flow rate during the sputtering of the bottom electrode layer and the RF bias voltage during the deposition of the piezoelectric layer, thereby adjusting the substrate curvature radius of the SOI wafer and reducing the warping of the SOI wafer.

[0052] Due to process limitations, the produced SOI wafers exhibit a certain degree of wafer bow. The existence of SOI wafer bow can be attributed to the residual stress inside the SOI wafer. The SOI wafer includes a substrate and a structural layer, and there is a SiO2 insulating layer in the substrate and the structural layer.

[0053] In a nitrogen and argon atmosphere at 300°C, a seed layer is sputtered on the silicon structure layer, a bottom electrode layer is sputtered on the seed layer by a multi-chamber DC magnetron sputtering system, a piezoelectric layer is deposited on the bottom electrode layer, and a top electrode layer is sputtered on the piezoelectric layer. The stress of the piezoelectric layer is adjusted by changing the argon flow rate during the sputtering of the bottom electrode layer and the RF bias voltage during the deposition of the piezoelectric layer. The argon flow rate has a certain linear relationship with the RF bias voltage and the stress of the piezoelectric layer. By changing the above two variables with a certain gradient value, the argon flow rate and the RF bias voltage can be plotted as independent variables, and the stress value of the piezoelectric layer can be plotted as a dependent variable, and a multivariate trend map can be plotted as a reference. The change in the stress of the deposited piezoelectric film and the specific warpage value of the SOI wafer also has a certain linear relationship. In actual work, the stress value of the film to be deposited is reversely inferred based on the specific warpage value of the SOI wafer, and then the appropriate argon flow rate and RF bias voltage specific parameters are found based on the data chart, and the deposition menu is re-established on the DC magnetron sputtering machine to complete the optimization of the wafer warpage. Through optimization, the wafer-level stress range of the deposited piezoelectric layer can be controlled within 100MPa. Figure 4 As shown in the figure, the upward bending of the SOI wafer indicates the presence of residual compressive stress. Therefore, in the DC reactive magnetron sputtering system, during the deposition of the piezoelectric layer, the deposition parameters are controlled to cause the deposited piezoelectric layer to have a certain stress, thereby adjusting the curvature radius of the SOI wafer substrate to reduce the warpage of the SOI wafer. The material of the seed layer is AlN, and the material of the piezoelectric layer is Al 0.8 Sc 0.2 N, and the materials of the bottom electrode layer and the top electrode layer are Mo.

[0054] The relationship between the stress of the piezoelectric layer and the radius of curvature of the SOI wafer substrate is:

[0055]

[0056] Where σ is stress, h is substrate thickness, t is piezoelectric layer thickness, R is the substrate curvature radius of the SOI wafer, E is the Young's modulus of the substrate, and v is the Poisson's ratio of the substrate. is the biaxial elastic modulus of the substrate.

[0057] S3. After completing sputtering and deposition, the SOI wafer is back-etched by DRIE etching, and the flow rate of the passivation gas and the proportion of the passivation gas in the etching cycle are increased, so that the fluorinated carbon polymer formed by the reaction is fully deposited on the side wall surface of the back cavity.

[0058] When using DRIE etching, the imbalance of flow control and exhaust time of the passivation gas C4F8 and etching gas SF6 will lead to inconsistent back cavity etching diameter across the wafer. Figure 5As shown, the mean back cavity etching diameter is 507.4 μm, the maximum difference is 220.2 μm, and the standard deviation is 58.9 μm.

[0059] When etching the back cavity of an 8-inch SOI wafer, the flow rate of the passivation gas C4F8 is appropriately increased to 525 sccm, and the proportion of the passivation gas C4F8 in an etching cycle is increased from 27% to 31%. This allows the carbon fluoride polymer formed by the reaction to be fully deposited on the surface of the back cavity sidewall, blocking the reaction between fluoride ions and the sidewall silicon, thereby ensuring that the back cavity diameter is stable at the expected diameter of about 600 μm. After optimization, Figure 6 As shown, the average diameter of the back cavity etching is 598.9 μm, and the standard deviation is reduced from 58.9 μm to 1.3 μm, with a reduction of 97.8%.

[0060] The method also includes back cavity diameter stability verification, which specifically includes:

[0061] A bare silicon wafer of the same size as the SOI wafer is used, and chemical mechanical polishing (CMP) is used to thin it to the same thickness as the PMUT substrate silicon. A SiO2 layer is deposited on the bare silicon wafer using plasma enhanced chemical vapor deposition (PECVD) as an etch stop layer for back cavity etching. The bare silicon wafer is back-cavity etched using the same etching method as that used for back cavity etching of the SOI wafer. Since SiO2 is transparent, an optical microscope can be used to measure the diameter of the back cavity from the front of the bare silicon wafer, thereby obtaining the back cavity diameter of the SOI wafer.

[0062] The method also includes wafer-level frequency consistency verification of the PMUT, and the wafer-level frequency consistency verification of the PMUT specifically includes: obtaining the wafer-level frequency consistency of the PMUT by comparing the resonant frequency distribution of the PMUT and the standard deviation of the resonant frequency of the PMUT.

[0063] The calculation formula of the resonant frequency of PMUT is:

[0064]

[0065] Where r is the radius of the PMUT, D is the stiffness of the thin film stack consisting of the structural layer, electrode layer and piezoelectric layer, and ρ i and t i are the density and thickness of the structural layer, electrode layer and piezoelectric layer, respectively.

[0066] The calculation formula for stiffness is:

[0067]

[0068] In the formula, E i is Young's modulus, vi is the Poisson’s ratio of each film layer material in the film stack, Z i is the distance from the top surface of the i-th film layer to the neutral axis.

[0069] The wafer-level frequency distribution of PMUT devices without any process optimization is as follows: Figure 7 As shown, the maximum difference in device frequency is 71.62kHz, the average is 155.30kHz, and the standard deviation is 23.48kHz. The frequency at the center of the wafer is significantly higher than that at the edge. Figure 8 The figure shows the wafer-level frequency distribution of the PMUT device after process optimization. The frequency difference between devices on the wafer is 16.21kHz, the average is 171.71kHz, and the standard deviation is 5.14kHz. The wafer-level frequency offset accounts for 4.7% of the center frequency. Figure 7 and Figure 8 It can be seen that the air-coupled PMUT has excellent wafer-level frequency consistency after optimizing wafer warpage, back cavity etching and silicon structure layer thickness.

[0070] S4, slicing the etched SOI wafer to obtain PMUT.

[0071] Use chemical cleaning liquid and ultrapure water to thoroughly clean the SOI wafer to remove impurities such as particles and organic matter on the surface to ensure the quality of slicing and the reliability of subsequent processes. A layer of photoresist is evenly coated on the surface of the SOI wafer. The thickness and performance of the photoresist need to be selected according to the specific photolithography process and cutting accuracy requirements. Use a photolithography machine to transfer the pre-designed cutting pattern to the photoresist. Through the exposure and development process, the photoresist forms a specific pattern in the area to be cut, providing precise guidance for subsequent cutting. Using laser invisible cutting technology, the pulsed laser is focused inside the SOI wafer to modify the material to form a cutting crack, thereby realizing the cutting of the wafer. This method has small vibration impact, less cutting chip pollution, and small thermal stress. After the cutting is completed, the SOI wafer is naturally split along the cutting crack by expanding the adhesive film and other methods, and the wafer is divided into individual PMUTs.

[0072] The preferred specific embodiments of the present invention are described in detail above. It should be understood that a person skilled in the art can make many modifications and changes based on the concept of the present invention without creative work. Therefore, any technical solution that can be obtained by a person skilled in the art through logical analysis, reasoning or limited experiments based on the concept of the present invention on the basis of the prior art should be within the scope of protection determined by the claims.

Claims

1. A PMUT optimization production method based on SOI wafer, characterized in that: The following steps are involved: Measuring the thickness of the structural layer of the SOI wafer to obtain the thickness distribution of the structural layer of the SOI wafer, and adjusting the thickness of different areas on the top of the structural layer of the SOI wafer according to the thickness distribution of the structural layer of the SOI wafer to improve the uniformity of the thickness of the structural layer; In a nitrogen and argon atmosphere, a seed layer is sputtered on the structural layer, a bottom electrode layer is sputtered on the seed layer, a piezoelectric layer is deposited on the bottom electrode layer, and a top electrode layer is sputtered on the piezoelectric layer, and the stress of the piezoelectric layer is adjusted by changing the argon gas flow rate during the sputtering of the bottom electrode layer and the radio frequency bias voltage during the deposition of the piezoelectric layer, thereby adjusting the substrate curvature radius of the SOI wafer and reducing the warpage of the SOI wafer; After the sputtering and deposition are completed, the SOI wafer is back-etched by DRIE etching, and the flow rate of the passivation gas and the time ratio of the passivation gas in the etching cycle are increased, so that the fluorinated carbon polymer formed by the reaction is fully deposited on the side wall surface of the back cavity; The etched SOI wafer is sliced ​​to obtain a PMUT.

2. The PMUT optimization production method based on SOI wafer according to claim 1, characterized in that: The SOI wafer comprises a substrate and a structural layer, wherein the substrate and the structural layer include a SiO2 insulating layer.

3. The PMUT optimization production method based on SOI wafer according to claim 1, characterized in that: The relationship between the stress of the piezoelectric layer and the substrate curvature radius of the SOI wafer is: Where σ is stress, h is substrate thickness, t is piezoelectric layer thickness, R is the substrate curvature radius of the SOI wafer, E is the Young's modulus of the substrate, and v is the Poisson's ratio of the substrate. is the biaxial elastic modulus of the substrate.

4. The PMUT optimization production method based on SOI wafer according to claim 1, characterized in that: The material of the seed layer is AlN.

5. The PMUT optimization production method based on SOI wafer according to claim 1, characterized in that: The material of the piezoelectric layer is Al 0.8 Sc 0.2 N.

6. The method for optimizing PMUT production based on SOI wafer according to claim 1, characterized in that: The material of the bottom electrode layer and the top electrode layer is Mo.

7. The PMUT optimization production method based on SOI wafer according to claim 1, characterized in that: The method also includes back cavity diameter stability verification, which specifically includes: A bare silicon wafer of the same size as the SOI wafer is used, and the bare silicon wafer is thinned to the same thickness as the substrate of the SOI wafer, and a SiO2 layer is deposited on the bare silicon wafer as an etch stop layer for back cavity etching, and the bare silicon wafer is back cavity etched using the same etching method as that used for back cavity etching of the SOI wafer, and the diameter of the back cavity of the bare silicon wafer is measured from the front side using an optical microscope, thereby obtaining the back cavity diameter of the SOI wafer.

8. The PMUT optimization production method based on SOI wafer according to claim 1, characterized in that: The method also includes wafer-level frequency consistency verification of the PMUT, and the wafer-level frequency consistency verification of the PMUT specifically includes: obtaining the wafer-level frequency consistency of the PMUT by comparing the resonant frequency distribution of the PMUT and the standard deviation of the resonant frequency of the PMUT.

9. The method for optimizing PMUT production based on SOI wafer according to claim 8, characterized in that: The calculation formula of the resonant frequency of the PMUT is: Where r is the radius of the PMUT, D is the stiffness of the thin film stack consisting of the structural layer, electrode layer and piezoelectric layer, and ρ i and t i are the density and thickness of the structural layer, electrode layer and piezoelectric layer, respectively.

10. The method for optimizing PMUT production based on SOI wafer according to claim 9, characterized in that: The calculation formula of the stiffness is: In the formula, E i is Young's modulus, v i is the Poisson’s ratio of each film layer material in the film stack, Z i is the distance from the top surface of the i-th film layer to the neutral axis.

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