Multi-phase clock calibration method and device for SerDes transmitting terminal

Abstract

According to the embodiment of the invention, a multi-phase clock calibration device and a multi-phase clock calibration method for a SerDes transmitting terminal are provided. The apparatus includes a replicated output driver stage for generating a replicated signal proportional to an output signal of the output driver stage; a filter connected to an output of the replicated output drive stage; the analog-to-digital converter is used for receiving the filtered analog signal output by the filter and converting the filtered analog signal into a digital signal; the phase error detection unit is used for calculating an autocorrelation function between adjacent output signals and generating a phase adjustment signal according to a comparison result of the autocorrelation function; and the clock phase adjusting unit adjusts the phase of a multi-phase clock signal according to the phase adjusting signal, and the multi-phase clock signal is used for driving a multiplexer of the SerDes transmitting end to serialize the parallel digital information. According to the embodiment of the invention, the accuracy of the output signal of the SerDes transmitting end can be ensured by adjusting the multi-phase clock signal.

Description

Technical Field

[0001] The present disclosure relates to the field of optical communication technology, and in particular to a multi-phase clock calibration method and device for a SerDes transmitter. Background Art

[0002] With the continuous development of high-speed serial data transmission technology, the single-channel data rate of SerDes (serializer / deserializer) has been increased to 112GHz or even 224GHz. At such a high signal rate, in order to reduce the power consumption of the clock path, a 1 / 4 rate or 1 / 8 rate clock is usually used. However, the use of a low-rate clock will place more stringent requirements on the skew between clock phases. If the clock phase skew is large, it will affect the accuracy of data transmission.

[0003] The existing SerDes transmitter generally uses a multiplexer (MUX) to convert parallel data into serial data. The transmitter clock management circuit generally uses a buffer stage to transmit the clock signal and relies on a phase error detection circuit for calibration. The phase error detection circuit is usually implemented using logic gates. If there is a mismatch between the buffer stages connected to different paths, there will be a phase error between the clock signals output by each path, and this error cannot be detected by the existing phase error detection circuit, so it will eventually affect the accuracy of the calibration signal.

[0004] In addition, due to the different signal delays of different paths within the multiplexer, the data pulse widths output by it may be uneven. Taking a four-phase clock as an example, Figure 4 As shown in the figure, after the clock signals of different phases reach the multiplexer, different output pulse widths will be generated due to the delay difference, and the ideal output result cannot be obtained. Even if the multi-phase clock itself is calibrated, the error caused by the multiplexer cannot be solved, which in turn affects the accuracy of the analog signal output by the output driver stage.

[0005] The above problems limit the output signal accuracy of the existing SerDes transmitter and affect the reliability of high-speed data transmission. Therefore, it is necessary to improve the existing technology to optimize the clock phase calibration and improve the quality of SerDes signal transmission. Summary of the invention

[0006] In view of the problems existing in the prior art, the embodiments of the present disclosure provide a multi-phase clock calibration method and device for a SerDes transmitter, which can realize real-time dynamic calibration and ensure the accuracy of the output signal of the SerDes transmitter.

[0007] A first aspect of an embodiment of the present disclosure provides a multi-phase clock calibration device for a SerDes transmitter, which includes a replicated output driver stage, which is used to generate a replica signal proportional to the output signal of the output driver stage; a filter, which is connected to the output end of the replicated output driver stage; an analog-to-digital converter, which receives a filtered analog signal output by the filter and converts the filtered analog signal into a digital signal; a phase error detection unit, which calculates the autocorrelation function between adjacent output signals based on the output signal of the analog-to-digital converter, and generates a phase adjustment signal according to the comparison result of the autocorrelation function; a clock phase adjustment unit, which receives the phase adjustment signal from the phase error detection unit, and adjusts the phase of a multi-phase clock signal according to the phase adjustment signal, wherein the multi-phase clock signal is used to drive a multiplexer at the SerDes transmitter to serialize parallel digital information.

[0008] After being adjusted by the clock phase adjustment unit, the multi-phase clock signal is output to the multiplexer via the clock buffer stage to drive the multiplexer to serialize the multiple digital data into one digital data, and convert it into an analog signal for output through the output driver stage. Thus, the duplicate output driver stage, filter, analog-to-digital converter, phase error detection unit and clock phase adjustment unit connected between the output of the multiplexer and the clock buffer stage form a closed-loop feedback path for calibrating the multi-phase clock signal. Since the closed-loop feedback path includes the clock buffer stage and the multiplexer at the SerDes transmitter, the errors caused by the clock buffer stage and the multiplexer are also calibrated at the same time, thereby ensuring the accuracy of the output data to the greatest extent.

[0009] The input end of the duplicated output driver stage can be connected in parallel with the input end of the output driver stage of the SerDes transmitter, and the output signal can be adjusted by adjusting the number of transistors and the load value of the duplicated output driver stage.

[0010] Optionally, according to the first aspect of the embodiment of the present disclosure, the number of phases of the multi-phase clock signal is 2 N , wherein N is a positive integer, the phase error detection unit takes the output signal of the analog-to-digital converter corresponding to the reference clock signal as the starting point, calculates the autocorrelation function between each group of adjacent output signals of the analog-to-digital converter; generating the phase adjustment signal according to the comparison result of the autocorrelation function includes cyclically executing the following steps until i is taken from 1 to N: N The autocorrelation function is divided into two i-1 Groups, each containing 2 N-i+1 autocorrelation functions, compare the sum of the first half of the autocorrelation functions in each group with the sum of the second half of the autocorrelation functions, and generate an adjustment phase of (2k-1)*360 / 2 based on the comparison result. iThe phase adjustment signal of the clock signal, where k=1, 2, ..., 2 i-1 The phase adjustment signal is used to indicate whether to adjust the clock signal forward or backward so that the sum of the first half of the autocorrelation functions in the group is equal to the sum of the second half of the autocorrelation functions.

[0011] If each group contains an autocorrelation function after grouping, the sum of the autocorrelation functions is the value of the autocorrelation function. The above method of using the autocorrelation function to detect and adjust the phase difference has a fast convergence speed and higher accuracy, and is applicable to different modulation formats and rates.

[0012] Optionally, according to the first aspect of the embodiment of the present disclosure, the multi-phase clock signal is a four-phase clock signal, and its autocorrelation function is:

[0013] y 12 =E[x 1 (n)*x 2 (n)]

[0014] y 23 =E[x 2 (n)*x 3 (n)]

[0015] y 34 =E[x 3 (n)*x 4 (n)]

[0016] y 41 =E[x 4 (n)*x 1 (n+1)]

[0017] Where x1, x2, x3, and x4 are the output signals of the analog-to-digital converter, corresponding to the rising edges of the reference clock signal, the clock signal delayed by 90 degrees, the clock signal delayed by 180 degrees, and the clock signal delayed by 270 degrees in the four-phase clock signal, respectively. n represents the period of the four-phase clock signal, and y 12 ,y 23、 y 34 ,y 41 is an autocorrelation function between adjacent output signals, and generating a phase adjustment signal according to the comparison result of the autocorrelation function includes generating a phase adjustment signal according to |y 12 |+|y 23 |with|y 34 |+|y 41 | The comparison result generates a phase adjustment signal corresponding to a clock signal delayed by 180 degrees; according to |y 12 |with|y 23 The comparison result of | generates a phase adjustment signal corresponding to the clock signal delayed by 90 degrees, according to |y 34 |with|y41 The comparison result generates a phase adjustment signal corresponding to the clock signal delayed by 270 degrees.

[0018] Optionally, according to the first aspect of the embodiment of the present disclosure, the number of phases of the multi-phase clock signal is 2 N The operating frequency of the analog-to-digital converter is 1 / (M*2 N +1), M is an integer not less than 1.

[0019] Optionally, according to the first aspect of the embodiment of the present disclosure, the multi-phase clock signal is a four-phase clock signal, and its autocorrelation function is:

[0020] y 12 =E[x 1 (n)*x 2 (n+1)]

[0021] y 23 =E[x 2 (n+1)*x 3 (n+2)]

[0022] y 34 =E[x 3 (n+2)*x 4 (n+3)]

[0023] y 41 =E[x 4 (n+3)*x 1 (n+4)]

[0024] where x 1 、x 2 、x 3 、x 4 The rising edges of the reference clock signal, the clock signal delayed by 90 degrees, the clock signal delayed by 180 degrees, and the clock signal delayed by 270 degrees in the four-phase clock signal are respectively corresponding, and n represents the period of the four-phase clock signal. The phase adjustment signal is generated according to the comparison result of the autocorrelation function, including the following steps: 12 |+|y 23 |with|y 34 |+|y 41 | The comparison result generates a phase adjustment signal corresponding to a clock signal delayed by 180 degrees; according to |y 12 |with|y 23 The comparison result of | generates a phase adjustment signal corresponding to the clock signal delayed by 90 degrees, according to |y 34 |with|y 41 The comparison result generates a phase adjustment signal corresponding to the clock signal delayed by 270 degrees.

[0025] Optionally, according to the first aspect of the embodiment of the present disclosure, the filter is a low-pass filter, and the cutoff frequency of the low-pass filter is related to the value of the autocorrelation function.

[0026] A second aspect of an embodiment of the present disclosure provides a multi-phase clock calibration method for a SerDes transmitter, which includes generating a replicated analog signal proportional to an analog signal output by an output driver stage of the SerDes transmitter; low-pass filtering the replicated analog signal; converting the filtered replicated analog signal into a digital signal as an output signal through an analog-to-digital converter; calculating the autocorrelation function of adjacent output signals, and generating a phase adjustment signal based on a comparison result of the autocorrelation function; and adjusting the phase of the multi-phase clock signal according to the phase adjustment signal, wherein the multi-phase clock signal is used to drive a multiplexer at the SerDes transmitter to serialize parallel digital data.

[0027] According to a second aspect of the embodiment of the present disclosure, the number of phases of the multi-phase clock signal is 2 N , wherein N is a positive integer, the calculating of the autocorrelation function of adjacent output signals includes taking the output signal of the analog-to-digital converter corresponding to the reference clock signal as the starting point, calculating the autocorrelation function between each group of adjacent output signals of the analog-to-digital converter; the generating of the phase adjustment signal according to the comparison result of the autocorrelation function includes cyclically executing the following steps until i is taken from 1 to N: taking the calculated 2 N The autocorrelation function is divided into two i-1 Groups, each containing 2 N-i+1 autocorrelation functions, compare the sum of the first half of the autocorrelation functions in each group with the sum of the second half of the autocorrelation functions, and generate an adjustment phase of (2k-1)*360 / 2 based on the comparison result. i The phase adjustment signal of the clock signal, where k=1, 2, ..., 2 i-1 The phase adjustment signal is used to indicate whether to adjust the clock signal forward or backward so that the sum of the first half of the autocorrelation functions in the group is equal to the sum of the second half of the autocorrelation functions.

[0028] According to a second aspect of the embodiment of the present disclosure, the number of phases of the multi-phase clock signal is 2 N The operating frequency of the analog-to-digital converter is 1 / (M*2 N +1), M is an integer not less than 1.

[0029] According to a second aspect of the embodiment of the present disclosure, the filter is a low-pass filter, and the cut-off frequency of the low-pass filter is related to the value of the autocorrelation function.

[0030] It is not necessary to achieve all the advantages described above at the same time for any device or method to implement the present disclosure. Other features and advantages of the present disclosure will be described in the subsequent description embodiments, and partly become apparent from the description embodiments, or be understood by implementing the present disclosure. The purposes and advantages of the embodiments of the present disclosure can be realized and obtained by the structures indicated in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0032] Figure 1 A schematic block diagram showing a calibration device for a multi-phase clock at a SerDes transmitter according to an embodiment of the present disclosure;

[0033] Figure 2 Show Figure 1 A schematic diagram of an output signal of an analog-to-digital converter and a corresponding clock signal of a calibration device for a multi-phase clock at a SerDes transmitter in the embodiment shown;

[0034] Figure 3 A schematic flow chart of a method for calibrating an error of a four-phase clock signal according to an embodiment of the present disclosure is shown;

[0035] Figure 4 FIG. 1 is a schematic diagram showing a comparison between an output pulse width generated by a multiplexer in the prior art and an ideal pulse width. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. The various different embodiments can be combined with each other to form other embodiments not shown in the following description. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0037] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second" and similar words used in the present disclosure specification and claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not necessarily indicate a quantity restriction. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0038] Figure 1 A schematic block diagram of a multi-phase clock calibration device for a SerDes transmitter according to an embodiment of the present disclosure is shown. Figure 1 1 shows an example in which the SerDes transmitter converts 64 parallel signals into one serial digital signal through a 64:4 multiplexer 110 and a 4:1 multiplexer 120. The four-phase clock signal is input to the 4:1 multiplexer 120 via the clock buffer stage 140 to drive it to serialize the four digital signals into one digital signal. The 4:1 multiplexer 120 outputs the generated one serial digital signal to the output driver stage 130. The output driver stage 130 converts the digital signal into an analog signal for output.

[0039] The multi-phase clock calibration device 100 of the SerDes transmitter includes a duplicate output driver stage 101 , a filter 102 , an analog-to-digital converter (ADC) 103 , a phase error detection unit 104 and a clock phase adjustment unit 105 . Figure 1 A four-phase clock signal is shown as an example of a multi-phase clock signal.

[0040] The four-phase clock signals are represented by ck0, ck90, ck180 and ck270, which correspond to the reference clock signal, the clock signal delayed by 90 degrees, the clock signal delayed by 180 degrees and the clock signal delayed by 270 degrees, respectively. Each phase signal lags 90 degrees relative to the previous phase and is input to the clock phase adjustment unit 105. The clock signal after phase adjustment is transmitted to the 4:1 multiplexer 120 via the clock buffer stage 140 to sample the four digital signals output by the multiplexer 110, so as to realize the serialization of parallel data.

[0041] In order to ensure that the 4:1 multiplexer 120 outputs an accurate signal, the duplicate output driver stage 101 is connected in parallel to the input end of the output driver stage 130 to obtain an output signal Vcp that is the same as or proportional to the output signal Vout of the output driver stage 130. For example, the output driver stage 130 can be implemented using a transistor driver. The duplicate output driver stage can obtain an output signal that is proportional to the output driver stage by adjusting the number of transistors and the load value.

[0042] The output signal Vcp is input to the filter 102 for filtering. The filter 102 is a low-pass filter, which can adjust the amplitude of the signal input to the analog-to-digital converter 103. By adjusting the cutoff frequency of the filter, the size of the autocorrelation function value calculated by the phase error detection unit 104 can be adjusted. For example, the cutoff frequency of the low-pass filter can be set to 3dB.

[0043] The analog signal output from the filter 102 is input to the analog-to-digital converter 103 . Figure 2 Shows Figure 1 The schematic diagram of the output signal of the analog-to-digital converter and its corresponding clock signal of the SerDes transmitter multi-phase clock calibration device of the embodiment shown in FIG. Figure 2 As shown, the digital signal obtained by the analog-to-digital converter 103 is x 1 (n), x 2 (n), x 3 (n), x 4 (n), x 1 (n+1), x 2 (n+1), x 3 (n+1)..., can correspond to the rising edges of clock signals ck0, ck90, ck180, ck270 respectively, and n represents the signal period.

[0044] The phase error detection unit 104 extracts the phase deviation of the four-phase clock by calculating the autocorrelation function of adjacent output signals of the analog-to-digital converter. The calculation method of the autocorrelation function between every two adjacent signals can be specifically as follows:

[0045] y 12 =E[x 1 (n)*x 2 (n)]

[0046] y 23 =E[x 2 (n)*x 3 (n)]

[0047] y 34 =E[x 3 (n)*x4 (n)]

[0048] y 41 =E[x 4 (n)*x 1 (n+1)]

[0049] Thus, the autocorrelation function between every two adjacent signals is obtained. When the signal output by the 4:1 multiplexer is an ideal signal, y12=y23=y34=y41. If the signal output by the 4:1 multiplexer is not an ideal signal, the equation does not hold, and the phase of the multi-phase clock signal can be adjusted according to the size relationship between the calculated autocorrelation functions. The phase error detection unit 104 sends a phase adjustment signal to the clock phase adjustment unit 105 according to the size relationship between the autocorrelation functions. The clock phase adjustment unit 105 adjusts the phase of the input four-phase clock according to the phase adjustment signal. Thus, the clock phase is adjusted according to the relative size of each autocorrelation function, and the clock phase adjustment unit 105 can calibrate the output signal of the 4:1 multiplexer into an accurate signal.

[0050] The multiplexer of the embodiment of the present disclosure is not limited to the above multiplexer, and an 8:1 multiplexer can also be used as needed. The multi-phase clock signal corresponds to the multiplexer. The calibration device of the embodiment of the present disclosure is not limited to calibrating a four-phase clock signal, and can also be applied to phase calibration of other multi-phase clock signals.

[0051] Figure 3 A schematic flow chart of a method for performing error calibration on a four-phase clock signal according to a magnitude relationship of an autocorrelation function according to an embodiment of the present disclosure is shown.

[0052] In step 301, the autocorrelation function y is calculated based on the output signal of the analog-to-digital converter. 12 ,y 23、 y 34 ,y 41 .

[0053] In step 302, compare |y 12 |+|y 23 |with|y 34 |+|y 41 | size, if |y 12 |+|y 23 | is relatively large, adjust the rising edge of ck180 later. If |y 34 |+|y 41 | is relatively large, adjust the rising edge of ck180 forward until |y 12 |+|y 23 |=|y 34 |+|y 41|.

[0054] In step 303, compare |y 12 |with|y 23 | size, if |y 12 | is relatively large, then adjust the rising edge of ck90 later. If |y 23 | is relatively large, then adjust the rising edge of ck90 forward until |y 12 |=|y 23 |.

[0055] Similarly, compare |y 34 |with|y 41 | size, if |y 34 | is relatively large, adjust the rising edge of ck270 later. If |y 41 | is relatively large, adjust the rising edge of ck270 forward until |y 34 |=|y 41 |.

[0056] After the above adjustment, the signal output by the 4:1 multiplexer is accurate, avoiding the error of the output signal at the transmitter.

[0057] According to a further embodiment of the present disclosure, the power consumption of phase error calibration can be reduced by reducing the operating frequency of the analog-to-digital converter and the error detection circuit. Since the 4:1 multiplexer outputs a high-speed signal, the power consumption will be relatively large when background calibration is used. By changing the calculation method of the autocorrelation function as shown below, the operating frequency of the analog-to-digital converter and the error detection circuit only needs to be 1 / 5 of that of the transmitting end. The following calculation method still calculates the autocorrelation function between each group of adjacent outputs of the analog-to-digital converter, but the delay between two adjacent output signals is larger.

[0058] y 12 =E[x 1 (n)*x 2 (n+1)]

[0059] y 23 =E[x 2 (n+1)*x 3 (n+2)]

[0060] y 34 =E[x 3 (n+2)*x 4 (n+3)]

[0061] y 41 =E[x 4 (n+3)*x 1 (n+4)]

[0062] The above autocorrelation function is also applicable to the phase error calibration method described above, thereby realizing calibration of the four-phase clock signal.

[0063] According to a further embodiment of the present disclosure, the above method is also applicable to a two-phase clock signal, an eight-phase clock signal or a clock signal with more phases. N , where N is a positive integer, the adjustment steps are as follows: (1) Taking the analog-to-digital converter output corresponding to the reference clock signal as the starting point, calculate the autocorrelation function between each group of adjacent outputs of the analog-to-digital converter, where each group of adjacent outputs corresponds to two adjacent clock signals in the multi-phase clock signal; (2) Let i be from 1 to N, and repeat the following steps: divide the calculated autocorrelation function into two i-1 Groups, each containing 2 N-i+1 The sum of the first half of the autocorrelation functions in each group is compared with the sum of the second half of the autocorrelation functions. The corresponding phase is (2k-1)*360 / 2 according to the comparison result. i The phase adjustment signal of the clock signal, where k=1, 2,...2 i-1 The phase adjustment signal is used to indicate whether to adjust the clock signal forward or backward so that the sum of the first half of the autocorrelation functions in the group is equal to the sum of the second half of the autocorrelation functions; the clock phase adjustment unit adjusts the phase according to the phase adjustment signal.

[0064] Considering the reduction of power consumption of phase error calibration, for a phase number of 2 N The multi-phase clock signal can make the operating frequency of the analog-to-digital converter 1 / (2 N +1), or the operating frequency of the analog-to-digital converter can be set to 1 / (M*2 N +1), M is an integer not less than 1, and the operating frequency of the analog-to-digital converter can be further reduced by adjusting the M value.

[0065] The disclosed embodiment can calibrate the errors of the clock transmission path and the multiplexer used for digital signal serialization while calibrating the clock signal, thereby improving and ensuring the accuracy of the output signal to the greatest extent. The disclosed embodiment can be used for both foreground calibration and background calibration. In addition, the frequency of the analog-to-digital converter and the phase error detection circuit can be flexibly configured to reduce the power consumption and chip area of ​​the background calibration.

[0066] The above description is merely an exemplary embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. The protection scope of the present disclosure is determined by the appended claims.

Claims

1. A multi-phase clock calibration device for a SerDes transmitter, characterized in that include: A replicated output driver stage for generating a replica signal proportional to an output signal of the output driver stage of the SerDes transmitter; a filter connected to an output of the replicated output driver stage; an analog-to-digital converter, which receives the filtered analog signal output by the filter and converts the filtered analog signal into a digital signal; a phase error detection unit, which calculates an autocorrelation function between adjacent output signals based on the output signal of the analog-to-digital converter, and generates a phase adjustment signal according to a comparison result of the autocorrelation function; The clock phase adjustment unit receives the phase adjustment signal from the phase error detection unit and adjusts the phase of the multi-phase clock signal according to the phase adjustment signal. The multi-phase clock signal is used to drive the multiplexer at the SerDes transmitting end to serialize the parallel digital data.

2. The multi-phase clock calibration device according to claim 1, characterized in that: The number of phases of the multi-phase clock signal is 2 N , wherein N is a positive integer, the phase error detection unit takes the output signal of the analog-to-digital converter corresponding to the reference clock signal as the starting point, and calculates the autocorrelation function between each group of adjacent output signals of the analog-to-digital converter; the phase adjustment signal is generated according to the comparison result of the autocorrelation function, including cyclically executing the following steps until i is taken from 1 to N: N The autocorrelation function is divided into two i-1 Groups, each containing 2 N-i+1 autocorrelation functions, compare the sum of the first half of the autocorrelation functions in each group with the sum of the second half of the autocorrelation functions, and generate the corresponding phase (2k-1)*360 / 2 according to the comparison result. i The phase adjustment signal of the clock signal, where k=1,2,...,2 i-1 The phase adjustment signal is used to indicate whether to adjust the clock signal forward or backward so that the sum of the first half of the autocorrelation functions in the group is equal to the sum of the second half of the autocorrelation functions.

3. The multi-phase clock calibration device according to claim 1 or 2, characterized in that: The multi-phase clock signal is a four-phase clock signal, and its autocorrelation function is: y 12 =E[x1(n)*x2(n)], y 23 =E[x2(n)*x3(n)], y 34 =E[x3(n)*x4(n)], y 41 =E[x4(n)*x1(n+1)]? Where x1, x2, x3, and x4 are the output signals of the analog-to-digital converter, corresponding to the rising edges of the reference clock signal, the clock signal delayed by 90 degrees, the clock signal delayed by 180 degrees, and the clock signal delayed by 270 degrees in the four-phase clock signal, respectively. n represents the period of the four-phase clock signal, and y 12 ,y 23、 y 34 ,y 41 is an autocorrelation function between adjacent output signals, and generating a phase adjustment signal according to the comparison result of the autocorrelation function includes generating a phase adjustment signal according to |y 12 |+|y 23 |with|y 34 |+|y 41 | The comparison result generates a phase adjustment signal corresponding to a clock signal delayed by 180 degrees; according to |y 12 |with|y 23 The comparison result of | generates a phase adjustment signal corresponding to the clock signal delayed by 90 degrees, according to |y 34 |with|y 41 The comparison result generates a phase adjustment signal corresponding to the clock signal delayed by 270 degrees.

4. The multi-phase clock calibration device according to claim 1 or 2, characterized in that: The number of phases of the multi-phase clock signal is 2 N The operating frequency of the analog-to-digital converter is 1 / (M*2 N +1), M is an integer not less than 1.

5. The multi-phase clock calibration device according to claim 4, characterized in that The multi-phase clock signal is a four-phase clock signal, and its autocorrelation function is: y 12 =E[x1(n)*x2(n+1)], y 23 =E[x2(n+1)*x3(n+2)], y 34 =E[x3(n+2)*x4(n+3)], y 41 =E[x4(n+3)*x1(n+4)]? Wherein x1, x2, x3, and x4 correspond to the rising edges of the reference clock signal, the clock signal delayed by 90 degrees, the clock signal delayed by 180 degrees, and the clock signal delayed by 270 degrees in the four-phase clock signal, respectively, and n represents the period of the four-phase clock signal. The phase adjustment signal generated according to the comparison result of the autocorrelation function includes generating a phase adjustment signal according to |y 12 |+|y 23 |with|y 34 |+|y 41 | The comparison result generates a phase adjustment signal corresponding to a clock signal delayed by 180 degrees; according to |y 12 |with|y 23 The comparison result of | generates a phase adjustment signal corresponding to the clock signal delayed by 90 degrees, according to |y 34 |with|y 41 The comparison result generates a phase adjustment signal corresponding to the clock signal delayed by 270 degrees.

6. The multi-phase clock calibration device according to claim 1, characterized in that The filter is a low-pass filter, and the cut-off frequency of the low-pass filter is related to the value of the autocorrelation function.

7. The multi-phase clock calibration device according to claim 1, characterized in that The input end of the duplicated output driver stage is connected in parallel with the input end of the output driver stage of the SerDes transmitter, and the output signal thereof is adjusted by adjusting the number of transistors and the load value of the duplicated output driver stage.

8. A multi-phase clock calibration method for a SerDes transmitter, characterized in that include: Generate a replica analog signal proportional to the analog signal output by the output driver stage of the SerDes transmitter; low-pass filtering the copied analog signal; converting the filtered replicated analog signal into a digital signal as an output signal through an analog-to-digital converter; Calculating autocorrelation functions of adjacent output signals, and generating a phase adjustment signal according to a comparison result of the autocorrelation functions; The phase of a multi-phase clock signal is adjusted according to a phase adjustment signal, and the multi-phase clock signal is used to drive a multiplexer at a SerDes transmitting end to serialize parallel digital data.

9. The multi-phase clock calibration method according to claim 8, characterized in that The number of phases of the multi-phase clock signal is 2 N , wherein N is a positive integer, the calculating of the autocorrelation function of adjacent output signals includes taking the output signal of the analog-to-digital converter corresponding to the reference clock signal as the starting point, calculating the autocorrelation function between each group of adjacent output signals of the analog-to-digital converter; the generating of the phase adjustment signal according to the comparison result of the autocorrelation function includes cyclically executing the following steps until i is taken from 1 to N: taking the calculated 2 N The autocorrelation function is divided into two i-1 Groups, each containing 2 N-i+1 autocorrelation functions, compare the sum of the first half of the autocorrelation functions in each group with the sum of the second half of the autocorrelation functions, and generate an adjustment phase of (2k-1)*360 / 2 based on the comparison result. i The phase adjustment signal of the clock signal, where k=1,2,...,2 i-1 The phase adjustment signal is used to indicate whether to adjust the clock signal forward or backward so that the sum of the first half of the autocorrelation functions in the group is equal to the sum of the second half of the autocorrelation functions.

10. The multi-phase clock calibration method according to claim 8 or 9, characterized in that The multi-phase clock signal is a four-phase clock signal, and its autocorrelation function is: y 12 =E[x1(n)*x2(n)], y 23 =E[x2(n)*x3(n)], y 34 =E[x3(n)*x4(n)], y 41 =E[x4(n)*x1(n+1)]? Where x1, x2, x3, and x4 are the output signals of the analog-to-digital converter, corresponding to the rising edges of the reference clock signal, the clock signal delayed by 90 degrees, the clock signal delayed by 180 degrees, and the clock signal delayed by 270 degrees in the four-phase clock signal, respectively. n represents the period of the four-phase clock signal, and y 12 ,y 23、 y 34 ,y 41 is an autocorrelation function between adjacent output signals, and generating a phase adjustment signal according to the comparison result of the autocorrelation function includes generating a phase adjustment signal according to |y 12 |+|y 23 |with|y 34 |+|y 41 | The comparison result generates a phase adjustment signal corresponding to a clock signal delayed by 180 degrees; according to |y 12 |with|y 23 The comparison result of | generates a phase adjustment signal corresponding to the clock signal delayed by 90 degrees, according to |y 34 |with|y 41 The comparison result generates a phase adjustment signal corresponding to the clock signal delayed by 270 degrees.

11. The multi-phase clock calibration method according to claim 8 or 9, characterized in that: The number of phases of the multi-phase clock signal is 2 N The operating frequency of the analog-to-digital converter is 1 / (M*2 N +1), M is an integer not less than 1.

12. The multi-phase clock calibration method according to claim 8 or 9, characterized in that: The copied analog signal is low-pass filtered using a low-pass filter having a cutoff frequency related to the magnitude of the value of the autocorrelation function.

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