Multifunctional BGA packaging structure and method

Abstract

The invention relates to the technical field of chip packaging, in particular to a multifunctional BGA packaging structure and method. Comprising a substrate, the front surface of the substrate is provided with a wafer, the back surface of the substrate is provided with a first electric connection structure, and the side surface of the substrate is provided with a plurality of side pads. Compared with the prior art, the solid state disk has the advantages that the memories and the controller are designed to be provided with the bonding pads on the side edges, and then the memories and the controller are bonded from the bonding pads on the side faces, so that the overall area is reduced, the memories and the controller can be directly interconnected, and the read-write speed and the power supply integrity of the solid state disk are also improved.

Description

Technical Field

[0001] The invention relates to the technical field of chip packaging, in particular to a multifunctional BGA packaging structure and method. Background Art

[0002] The existing memory packaging type is mainly ordinary BGA packaging. This product has standard parts characteristics. The final packaged products have a uniform package size and number of balls, but the solder balls are all located on the back of the substrate. This limits the signal transmission port and cannot fully guarantee the high-speed reading and writing capabilities of stored data and power supply stability.

[0003] And, if Fig.10 As shown, in the solid-state drive product, the distance between the storage packaging particles and between the control chip and the storage packaging particles is relatively far, resulting in a relatively large layout area of ​​the entire SSD. Summary of the invention

[0004] The present invention provides a multifunctional BGA packaging structure and method to overcome the deficiencies of the prior art.

[0005] To achieve the above purpose, a multifunctional BGA packaging structure is designed, including a substrate, a wafer is provided on the front side of the substrate, a first electrical connection structure is provided on the back side of the substrate, and a plurality of side pads are provided on the side of the substrate.

[0006] The side pad is provided with a second electrical connection structure.

[0007] The outer side of the second electrical connection structure is provided with an electroplated tin layer.

[0008] A plastic package is disposed outside the wafer, and a portion of the second electrical connection structure is exposed by the plastic package.

[0009] The wafer is a memory wafer or a controller wafer.

[0010] To achieve the above purpose, a multifunctional BGA packaging method is designed, comprising the following steps: S1, evenly arrange a number of side pads on the side of the substrate, and then electrically connect the gold fingers on the surface of the substrate to the side pads; S2, forming a second electrical connection structure on the side pad; S3, mounting a wafer on the front side of the substrate, and electrically connecting the wafer to the gold finger through a bonding wire; S4, plastic sealing; S5, forming a first electrical connection structure on the back side of the substrate; S6, cutting into individual chips, where the second electrical connection structure is exposed on the side of the individual chips after cutting.

[0011] The method further includes step S7 of forming a tin-plated layer on the outer side of the second electrical connection structure.

[0012] The method further includes step S8, bonding the plurality of chips together via a second electrical connection structure on the side of the chip.

[0013] Compared with the prior art, the present invention designs the memory and the controller with pads on the side, and then bonds the memory and the controller from the side pads. Not only does the overall area become smaller, the memories and controllers can be directly interconnected, and the read and write speed and power integrity of the solid-state drive are also improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a structural schematic diagram of the present invention.

[0015] Figure 2 It is a schematic diagram of step S1 of the present invention.

[0016] Figure 3 It is a schematic diagram of step S2 of the present invention.

[0017] Figure 4 It is a schematic diagram of step S3 of the present invention.

[0018] Figure 5 It is a schematic diagram of steps S4 to S6 of the present invention.

[0019] Figure 6 It is a schematic diagram of step S7 of the present invention.

[0020] Figure 7 This is a top view of the side pad obtained by the present invention.

[0021] Figure 8 for Figure 7 Side view at A in the middle.

[0022] Fig. 9 It is a schematic diagram of the present invention when used.

[0023] Fig.10 It is a schematic diagram of the prior art before the improvement of the present invention. DETAILED DESCRIPTION

[0024] The present invention will be further described below with reference to the accompanying drawings. Example

[0025] like Figure 1 As shown, a wafer 2 is disposed on the front of the substrate 1, a first electrical connection structure 3 is disposed on the back of the substrate 1, and a plurality of side pads 4 are disposed on the side of the substrate 1 for bonding between chips. A second electrical connection structure 5 is disposed on the side pads 4.

[0026] The outer side of the second electrical connection structure 5 is provided with an electroplated tin layer 6 .

[0027] A plastic package 7 is provided outside the wafer 2 for protection, and the plastic package 7 exposes part of the second electrical connection structure 5 to ensure that adjacent chips can be bonded, while part of the second electrical connection structure 5 is wrapped in the plastic package 7 for protection.

[0028] Wafer 2 is a memory wafer or a controller wafer.

[0029] During specific use, the first electrical connection structure 3 and the second electrical connection structure 5 are selected from one or more of solder balls and bumps to complete the electrical connection.

[0030] like Figures 2 to 9 As shown, the multifunctional BGA packaging method in this embodiment includes the following steps: S1, evenly arrange a number of side pads 4 on the side of the substrate 1, and then electrically connect the gold fingers 8 on the surface of the substrate 1 to the side pads 4; S2, forming a second electrical connection structure 5 on the side pad 4; S3, mounting the wafer 2 on the front side of the substrate 1, and electrically connecting the wafer 2 to the gold finger 8 through the bonding wire 9; S4, plastic sealing; S5, forming a first electrical connection structure 3 on the back side of the substrate 1; S6, cutting into individual chips, where the second electrical connection structure 5 is exposed on the side of the individual chips after cutting.

[0031] S7 , forming a tin-plated layer 6 on the outer side of the second electrical connection structure 5 .

[0032] S8, a plurality of chips are bonded to each other through the second electrical connection structure 5 on the side of the chip, and then pasted to the solid state hard disk PCB board through a thermal compression bonding process.

[0033] When used specifically, the number of side pads can be set according to functional requirements. Then the chips are bonded side by side by thermal compression bonding to maximize the use of the PCB area, or to reduce the PCB area when the hard disk capacity is fixed, while improving the read and write speed and power integrity of the memory.

[0034] In specific use, the control device used in the solid-state hard drive can be made into a side metal pad in the same way, and then the control device can be bonded to the side of the memory using the same thermal compression bonding technology. This allows the control device to perform the shortest distance signal control and power supply to the memory device, thereby improving the electrical performance and the read and write capabilities of the memory.

Claims

1. A multifunctional BGA packaging structure, comprising a substrate, characterized in that: The front side of the substrate (1) is provided with a wafer (2), the back side of the substrate (1) is provided with a first electrical connection structure (3), and the side surfaces of the substrate (1) are provided with a plurality of side pads (4).

2. A multifunctional BGA packaging structure according to claim 1, characterized in that: A second electrical connection structure (5) is provided on the side pad (4).

3. A multifunctional BGA packaging structure according to claim 2, characterized in that: The second electrical connection structure (5) is provided with an electroplated tin layer (6) on the outer side.

4. The multifunctional BGA packaging structure according to claim 1, characterized in that: A plastic package (7) is provided on the outside of the wafer (2), and a portion of the second electrical connection structure (5) is exposed from the plastic package (7).

5. The multifunctional BGA packaging structure according to claim 1, characterized in that: The wafer (2) is a memory wafer or a controller wafer.

6. A multifunctional BGA packaging method, characterized in that: The steps include: S1, evenly arranging a plurality of side pads (4) on the side of the substrate (1), and then electrically connecting the gold fingers (8) on the surface of the substrate (1) to the side pads (4); S2, forming a second electrical connection structure (5) on the side pad (4); S3, mounting a wafer (2) on the front side of the substrate (1), and electrically connecting the wafer (2) and the gold finger (8) via a welding wire (9); S4, plastic sealing; S5, forming a first electrical connection structure (3) on the back side of the substrate (1); S6, cutting into individual chips, wherein a portion of the second electrical connection structure (5) is exposed on the side surface of the individual chips after cutting.

7. A multifunctional BGA packaging method according to claim 6, characterized in that: The method further comprises step S7 of forming a tin-plated layer (6) on the outer side of the second electrical connection structure (5).

8. A multifunctional BGA packaging method according to claim 6, characterized in that: The method further comprises step S8, bonding the plurality of chips together via a second electrical connection structure (5) on the side of the chip.

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